CN107968642A - A kind of dual bootstrap sampling switch circuit of low voltage application - Google Patents
A kind of dual bootstrap sampling switch circuit of low voltage application Download PDFInfo
- Publication number
- CN107968642A CN107968642A CN201810024829.3A CN201810024829A CN107968642A CN 107968642 A CN107968642 A CN 107968642A CN 201810024829 A CN201810024829 A CN 201810024829A CN 107968642 A CN107968642 A CN 107968642A
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- pmos tube
- tube
- grid
- nmos tube
- charging capacitor
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Classifications
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
- H03K17/51—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used
- H03K17/56—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices
- H03K17/687—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices the devices being field-effect transistors
- H03K17/6871—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices the devices being field-effect transistors the output circuit comprising more than one controlled field-effect transistor
- H03K17/6872—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices the devices being field-effect transistors the output circuit comprising more than one controlled field-effect transistor using complementary field-effect transistors
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M1/00—Analogue/digital conversion; Digital/analogue conversion
- H03M1/12—Analogue/digital converters
- H03M1/34—Analogue value compared with reference values
- H03M1/38—Analogue value compared with reference values sequentially only, e.g. successive approximation type
- H03M1/46—Analogue value compared with reference values sequentially only, e.g. successive approximation type with digital/analogue converter for supplying reference values to converter
- H03M1/466—Analogue value compared with reference values sequentially only, e.g. successive approximation type with digital/analogue converter for supplying reference values to converter using switched capacitors
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- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Electronic Switches (AREA)
Abstract
The present invention relates to CMOS technical field of analog integrated circuit design.The invention discloses a kind of dual bootstrap sampling switch circuit of low voltage application, including charging circuit, switching voltage control circuit, charging capacitor unit and sampling switch path, the charging capacitor unit includes charging capacitor Cb1 and Cb2, when clock signal clkb is the first level, the charging circuit is used to control supply voltage to carry out charged in parallel to charging capacitor Cb1 and Cb2, and be grounded the control terminal of sampling switch path, close sampling switch path；When clock signal clkb is second electrical level, the switching voltage control circuit is used to control charging capacitor Cb1 and Cb2 to power for the control terminal of sampling switch path after connecting, and opens sampling switch path and is sampled.The present invention can realize that switch control voltage is lifted for twice under extremely low supply voltage, complete the conducting and shut-off of sampling switch path, and signal sampling precision is high.
Description
Technical field
The invention belongs to CMOS technical field of analog integrated circuit design, more particularly to a kind of low voltage application it is double from
Lift sampling switch circuit.
Background technology
In wearable physiological signal detection chip, the supply voltage of low-power consumption gradually-appoximant analog-digital converter may be as low as
200-300mV.And the threshold voltage of transistor is still maintained at 300mV or so.If still continue to use traditional gain bootstrap switch to come
Signal sampling is completed, supply voltage approaches or the threshold voltage less than transistor at this time, and be easy to causeing switching transistor can not
The situation of conducting.Also it is only switching transistor is in weak transoid shape even if supply voltage is suitable with transistor threshold voltage
State, still can cause declining to a great extent for signal sampling precision.
The content of the invention
A kind of dual bootstrap sampling switch circuit it is an object of the invention to provide low voltage application is above-mentioned to solve
Problem.
To achieve the above object, the technical solution adopted by the present invention is：A kind of dual bootstrap sampling switch of low voltage application
Circuit, including charging circuit, switching voltage control circuit, charging capacitor unit and sampling switch path, the charging capacitor list
Member includes charging capacitor Cb1 and Cb2, and when clock signal clkb is the first level, the charging circuit is used to control power supply electric
Pressure carries out charging capacitor Cb1 and Cb2 charged in parallel, and the control terminal of sampling switch path is grounded, and closes sampling switch and leads to
Road；When clock signal clkb is second electrical level, the switching voltage control circuit is used to control charging capacitor Cb1 and Cb2 to go here and there
Power after connection for the control terminal of sampling switch path, open sampling switch path and sampled.
Further, the charging circuit include NMOS tube NM0, NM1, NM2, NM3 and NM4 and PMOS tube PM0 and
The grid of PM5, the NMOS tube NM0 meet clock signal clkb, and the source electrode ground connection of NMOS tube NM0, the drain electrode of NMOS tube NM0, which connects, fills
The bottom crown node b1 of capacitance Cb1；The grid of NMOS tube NM1 meets clock signal clkb, and the source electrode of NMOS tube NM1 is grounded,
The drain electrode of NMOS tube NM1 connects the grid of PMOS tube PM0, and the grid of NMOS tube NM2 connects clock signal clkb, the source of NMOS tube NM2
Pole is grounded, and the drain electrode of NMOS tube NM2 meets the bottom crown node b2 of charging capacitor Cb2, and the grid of NMOS tube NM3 connects clock signal
The source electrode ground connection of clkb, NMOS tube NM3, the drain electrode of NMOS tube NM3 connects the grid of PMOS tube PM5, when the grid of NMOS tube NM4 connects
The source electrode ground connection of clock signal clkb, NMOS tube NM4, the drain electrode of NMOS tube NM4 meet the control terminal Vsh, PMOS of sampling switch path
The source electrode of pipe PM0 meets supply voltage VDD, and the drain electrode of PMOS tube PM0 meets top crown the node t1, PMOS tube PM5 of charging capacitor Cb1
Source electrode meet supply voltage VDD, the drain electrode of PMOS tube PM5 meets the top crown node t2 of charging capacitor Cb2.
Further, the switching voltage control circuit includes PMOS tube PM1, PM2, PM3 and PM4, the PMOS tube
The grid of PM1 meets clock signal clkb, and the source electrode of PMOS tube PM1 meets top crown the node t1, PMOS tube PM1 of charging capacitor Cb1
Drain electrode connect the grid of PMOS tube PM0, the grid of PMOS tube PM2 meets clock signal clkb, and the source electrode of PMOS tube PM2 connects charging electricity
The drain electrode for holding bottom crown the node b2, PMOS tube PM2 of Cb2 connects the top crown node t1 of charging capacitor Cb1, the grid of PMOS tube PM3
Pole meets clock signal clkb, and the source electrode of PMOS tube PM3 meets the top crown node t2 of charging capacitor Cb2, and the drain electrode of PMOS tube PM3 connects
The grid of PMOS tube PM5, the grid of PMOS tube PM4 meet clock signal clkb, and the source electrode of PMOS tube PM4 connects sampling switch path
The drain electrode of control terminal Vsh, PMOS tube PM4 meet the top crown node t2 of charging capacitor Cb2.
Further, the sampling switch path include NMOS tube NMS1, NMS2 and NMS3 and PMOS tube PMH and
The grid of PMS1, NMOS tube NMS1 meet clock signal clk, and the source electrode of NMOS tube NMS1 connects the bottom crown node of charging capacitor Cb1
The drain electrode of b1, NMOS tube NMS1 meet input signal Vin, and the grid of PMOS tube PMS1 meets clock signal clkb, PMOS tube PMS1's
Source electrode meets input signal Vin, and the drain electrode of PMOS tube PMS1 meets the bottom crown node b1 of charging capacitor Cb1, NMOS tube NMS2's
Source electrode meets input signal Vin, and the grid of NMOS tube NMS2 is the control terminal Vsh of sampling switch path, the drain electrode of NMOS tube NMS2
The drain electrode of PMOS tube PMH is connect, the source electrode of PMOS tube PMH connects reference voltage Vref, and the grid of PMOS tube PMH meets clock signal clk,
The source electrode of NMOS tube NMS3 connects the drain electrode of PMOS tube PMH, and the grid of NMOS tube NMS3 connects the grid of NMOS tube NMS2, NMOS tube
The drain electrode of NMS3 is signal output part Vout.
The advantageous effects of the present invention：
The metal-oxide-semiconductor of sampling switch path is controlled voltage increase to twice by the present invention by double capacitances series connection bootstrap configuration
Supply voltage, the conducting of metal-oxide-semiconductor when realizing low supply voltage；The virtual cmos switch of clock signal control, effectively reduces electricity
Influence of the lotus injection effect to metal-oxide-semiconductor, improves signal sampling precision；T-shaped metal-oxide-semiconductor network, in non-sampled clock phase, reduces
The influence of subthreshold value charge leakage, further increases signal sampling precision.The present invention have it is low leakage, sampling with high precision it is excellent
Point, suitable for the gradually-appoximant analog-digital converter structure of low supply voltage.
Brief description of the drawings
Fig. 1 is the circuit diagram of the specific embodiment of the invention；
Fig. 2 is the phase diagram of the clock signal clk and clkb of the specific embodiment of the invention；
Fig. 3 is the spectrum analysis simulation result figure of the output signal of the specific embodiment of the invention.
Embodiment
In conjunction with the drawings and specific embodiments, the present invention is further described.
As shown in Figure 1, a kind of dual bootstrap sampling switch circuit of low voltage application, including charging circuit, switching voltage control
Circuit, charging capacitor unit and sampling switch path processed, the charging capacitor unit include charging capacitor Cb1 and Cb2, work as clock
When signal clkb is the first level (being high level in this specific embodiment), the charging circuit is used to control supply voltage to filling
Capacitance Cb1 and Cb2 carry out charged in parallel, and the control terminal of sampling switch path is grounded, and close sampling switch path；At that time
When clock signal clkb is second electrical level (being low level in this specific embodiment), the switching voltage control circuit is filled for control
Power after capacitance Cb1 and Cb2 series connection for the control terminal of sampling switch path, open sampling switch path and sampled.
In this specific embodiment, the charging circuit includes NMOS tube NM0, NM1, NM2, NM3 and NM4 and PMOS tube
PM0 and PM5, the switching voltage control circuit include PMOS tube PM1, PM2, PM3 and PM4, and the sampling switch path includes
NMOS tube NMS1, NMS2 and NMS3 and PMOS tube PMH and PMS1.Certainly, in other embodiments, above-mentioned each metal-oxide-semiconductor
Corresponding other transistors can also be used to replace, such as double pole triode, this is that those skilled in the art can be real easily
Existing, no longer describe in detail.
The grid of the NMOS tube NM0 connects clock signal clkb, the source electrode ground connection of NMOS tube NM0, the drain electrode of NMOS tube NM0
Meet the bottom crown node b1 of charging capacitor Cb1；The grid of NMOS tube NM1 meets clock signal clkb, and the source electrode of NMOS tube NM1 connects
Ground, the drain electrode of NMOS tube NM1 connect the grid of PMOS tube PM0, and the grid of NMOS tube NM2 meets clock signal clkb, NMOS tube NM2's
Source electrode is grounded, and the drain electrode of NMOS tube NM2 meets the bottom crown node b2 of charging capacitor Cb2, and the grid of NMOS tube NM3 connects clock signal
The source electrode ground connection of clkb, NMOS tube NM3, the drain electrode of NMOS tube NM3 connects the grid of PMOS tube PM5, when the grid of NMOS tube NM4 connects
The source electrode ground connection of clock signal clkb, NMOS tube NM4, the drain electrode of NMOS tube NM4 connect grid (the sampling switch path of NMOS tube NMS2
Control terminal Vsh), the source electrode of PMOS tube PM0 meets supply voltage VDD, and the drain electrode of PMOS tube PM0 connects the upper pole of charging capacitor Cb1
The source electrode of compaction point t1, PMOS tube PM5 meet supply voltage VDD, and the drain electrode of PMOS tube PM5 connects the top crown knot of charging capacitor Cb2
Point t2.
The grid of the PMOS tube PM1 meets clock signal clkb, and the source electrode of PMOS tube PM1 connects the upper pole of charging capacitor Cb1
The drain electrode of compaction point t1, PMOS tube PM1 connect the grid of PMOS tube PM0, and the grid of PMOS tube PM2 meets clock signal clkb, PMOS
The drain electrode that the source electrode of pipe PM2 meets bottom crown the node b2, PMOS tube PM2 of charging capacitor Cb2 connects the top crown knot of charging capacitor Cb1
The grid of point t1, PMOS tube PM3 meet clock signal clkb, and the source electrode of PMOS tube PM3 connects the top crown node of charging capacitor Cb2
The drain electrode of t2, PMOS tube PM3 connect the grid of PMOS tube PM5, and the grid of PMOS tube PM4 meets clock signal clkb, PMOS tube PM4's
Source electrode connects the grid of NMOS tube NMS2, and the drain electrode of PMOS tube PM4 meets the top crown node t2 of charging capacitor Cb2.
The grid of NMOS tube NMS1 meets clock signal clk, in this specific embodiment, clock signal clk and clock signal
Clkb is non-overlapping reverse clock signal, specifically as shown in Fig. 2, the source electrode of NMOS tube NMS1 connects the lower pole of charging capacitor Cb1
The drain electrode of compaction point b1, NMOS tube NMS1 meet input signal Vin, and the grid of PMOS tube PMS1 connects clock signal clkb, PMOS tube
The source electrode of PMS1 meets input signal Vin, and the drain electrode of PMOS tube PMS1 connects the bottom crown node b1 of charging capacitor Cb1, NMOS tube
The source electrode of NMS2 meets input signal Vin, and the grid of NMOS tube NMS2 is the control terminal Vsh, NMOS tube NMS2 of sampling switch path
Drain electrode connect the drain electrode of PMOS tube PMH, the source electrode of PMOS tube PMH connects reference voltage Vref, and the grid of PMOS tube PMH connects clock letter
Number clk, the source electrode of NMOS tube NMS3 connect the drain electrode of PMOS tube PMH, and the grid of NMOS tube NMS3 connects the grid of NMOS tube NMS2,
The drain electrode of NMOS tube NMS3 is signal output part Vout.
When clock signal clk is low level, clkb is high level, NMOS tube NM0, NM1, NM2, NM3 and NM4 and
PMOS tube PM0 and PM5 are turned on, PMOS tube PM1, PM2, PM3 and PM4 shut-off.Wherein NMOS tube NM0 is turned on charging capacitor Cb1
Bottom crown node b1 ground connection, the top crown node t1 of charging capacitor Cb1 is connect power supply by NMOS tube NM1 and PMOS tube PM0 conductings
Voltage VDD, supply voltage VDD is charged to by the voltage on charging capacitor Cb1；NMOS tube NM2 is turned under charging capacitor Cb2
Pole plate node b2 is grounded, and the top crown node t2 of charging capacitor Cb2 is connect supply voltage by NMOS tube NM3 and PMOS tube PM5 conductings
VDD, supply voltage VDD is charged to by the voltage on charging capacitor Cb2；NMOS tube NM4 is turned on, and the grid of NMOS tube NMS2 is connect
Ground so that NMOS tube NMS2 is closed.
When clock signal clk is high level, clkb is low level, NMOS tube NM0, NM1, NM2, NM3 and NM4 and
PMOS tube PM0 and PM5 are turned off, PMOS tube PM1, PM2, PM3 and PM4 conducting.NMOS tube NMS1 and PMOS tube PMS1 compositions at the same time
The conducting of virtual cmos switch, PMOS tube PM1 and PM2 conducting are by the lower pole of the top crown of charging capacitor Cb1 and charging capacitor Cb2
Plate is connected；PMOS tube PM3 and PM4 turn on the grid that the top crown of charging capacitor Cb2 is connected to NMOS tube NMS2, realize two
The series connection of a capacitance, and the bottom crown node b1 of charging capacitor Cb1 is connected to the source electrode of NMOS tube NMS2 by cmos switch,
So as to which the grid-control voltage of NMOS tube NMS2 to be promoted to twice of supply voltage VDD.
In addition, the virtual cmos switch of NMOS tube NMS1 and PMOS tube PMS1 composition clock controls, on the one hand reduces electric charge
Influence of the injection effect to NMOS tube NMS2, on the other hand virtually cmos switch also improves the amplitude of oscillation of signal, so as to improve
Signal sampling precision.
On the other hand, since on-off circuit is operated in low supply voltage environment, most of metal-oxide-semiconductor is all in subthreshold value work
Make state, sub-threshold leakage can reduce the sampling precision of signal.The present invention is by NMOS tube NMS3, NMOS tube NMS2 and PMOS tube
PMH collectively constitutes T-shaped network, and when clock signal clk is low, the voltage for maintaining node VH (drain electrode of NMOS tube NMS2) is ginseng
Voltage Vref is examined, reduces influence of the subthreshold value charge leakage to sampling precision, so as to improve signal sampling precision.
Fig. 3 is the spectrum analysis simulation result of sampling switch circuit in the present embodiment.It can be seen that in supply voltage 0.25V, it is defeated
When to enter signal frequency be 1.9kHz, output sinad ratio (SNDR) reaches 50.53dB, and technique effect is good.
The metal-oxide-semiconductor of sampling switch path is controlled voltage increase to twice by the present invention by double capacitances series connection bootstrap configuration
Supply voltage, the conducting of metal-oxide-semiconductor when realizing low supply voltage；The virtual cmos switch of clock signal control, effectively reduces electricity
Influence of the lotus injection effect to metal-oxide-semiconductor, improves signal sampling precision；T-shaped metal-oxide-semiconductor network, in non-sampled clock phase, reduces
The influence of subthreshold value charge leakage, further increases signal sampling precision.The present invention have it is low leakage, sampling with high precision it is excellent
Point, suitable for the gradually-appoximant analog-digital converter structure of low supply voltage.
Although specifically showing and describing the present invention with reference to preferred embodiment, those skilled in the art should be bright
In vain, do not departing from the spirit and scope of the present invention that the appended claims are limited, in the form and details can be right
The present invention makes a variety of changes, and is protection scope of the present invention.
Claims (4)
- A kind of 1. dual bootstrap sampling switch circuit of low voltage application, it is characterised in that：Controlled including charging circuit, switching voltage Circuit, charging capacitor unit and sampling switch path, the charging capacitor unit include charging capacitor Cb1 and Cb2, when clock is believed When number clkb is the first level, the charging circuit, which is used to controlling supply voltage to carry out parallel connection to charging capacitor Cb1 and Cb2, to be filled Electricity, and the control terminal of sampling switch path is grounded, close sampling switch path；When clock signal clkb is second electrical level, The switching voltage control circuit is used to control charging capacitor Cb1 and Cb2 to power for the control terminal of sampling switch path after connecting, Sampling switch path is opened to be sampled.
- 2. the dual bootstrap sampling switch circuit of low voltage application according to claim 1, it is characterised in that：The charging electricity Road includes NMOS tube NM0, NM1, NM2, NM3 and NM4 and PMOS tube PM0 and PM5, the grid of the NMOS tube NM0 connect clock The source electrode ground connection of signal clkb, NMOS tube NM0, the drain electrode of NMOS tube NM0 meet the bottom crown node b1 of charging capacitor Cb1；NMOS The grid of pipe NM1 meets clock signal clkb, the source electrode ground connection of NMOS tube NM1, and the drain electrode of NMOS tube NM1 connects the grid of PMOS tube PM0 Pole, the grid of NMOS tube NM2 meet clock signal clkb, the source electrode ground connection of NMOS tube NM2, and the drain electrode of NMOS tube NM2 connects charging electricity The grid for holding bottom crown the node b2, NMOS tube NM3 of Cb2 connects clock signal clkb, the source electrode ground connection of NMOS tube NM3, NMOS tube The drain electrode of NM3 connects the grid of PMOS tube PM5, and the grid of NMOS tube NM4 meets clock signal clkb, and the source electrode of NMOS tube NM4 is grounded, The drain electrode of NMOS tube NM4 meets the control terminal Vsh of sampling switch path, and the source electrode of PMOS tube PM0 connects supply voltage VDD, PMOS tube The source electrode that the drain electrode of PM0 meets top crown the node t1, PMOS tube PM5 of charging capacitor Cb1 meets supply voltage VDD, PMOS tube PM5's Drain electrode meets the top crown node t2 of charging capacitor Cb2.
- 3. the dual bootstrap sampling switch circuit of low voltage application according to claim 2, it is characterised in that：The switch electricity Pressure control circuit includes PMOS tube PM1, PM2, PM3 and PM4, and the grid of the PMOS tube PM1 connects clock signal clkb, PMOS tube The drain electrode that the source electrode of PM1 meets top crown the node t1, PMOS tube PM1 of charging capacitor Cb1 connects the grid of PMOS tube PM0, PMOS tube The grid of PM2 meets clock signal clkb, and the source electrode of PMOS tube PM2 meets bottom crown the node b2, PMOS tube PM2 of charging capacitor Cb2 The grid of the drain electrode top crown node t1, PMOS tube PM3 that meet charging capacitor Cb1 connect clock signal clkb, the source of PMOS tube PM3 The drain electrode that pole meets top crown the node t2, PMOS tube PM3 of charging capacitor Cb2 connects the grid of PMOS tube PM5, the grid of PMOS tube PM4 Pole meets clock signal clkb, and the source electrode of PMOS tube PM4 meets the control terminal Vsh of sampling switch path, and the drain electrode of PMOS tube PM4, which connects, fills The top crown node t2 of capacitance Cb2.
- 4. the dual bootstrap sampling switch circuit of low voltage application according to claim 3, it is characterised in that：The sampling is opened Close path and connect clock signal including NMOS tube NMS1, NMS2 and NMS3 and PMOS tube PMH and PMS1, the grid of NMOS tube NMS1 The source electrode of clk, NMOS tube NMS1 meet the bottom crown node b1 of charging capacitor Cb1, and the drain electrode of NMOS tube NMS1 connects input signal The grid of Vin, PMOS tube PMS1 meet clock signal clkb, and the source electrode of PMOS tube PMS1 meets input signal Vin, PMOS tube PMS1 The source electrode of the drain electrode bottom crown node b1, NMOS tube NMS2 that meet charging capacitor Cb1 meet input signal Vin, NMOS tube NMS2's Grid is the control terminal Vsh of sampling switch path, and the drain electrode of NMOS tube NMS2 connects the drain electrode of PMOS tube PMH, the source of PMOS tube PMH Pole connects reference voltage Vref, and the grid of PMOS tube PMH meets clock signal clk, and the source electrode of NMOS tube NMS3 connects the leakage of PMOS tube PMH Pole, the grid of NMOS tube NMS3 connect the grid of NMOS tube NMS2, and the drain electrode of NMOS tube NMS3 is signal output part Vout.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201810024829.3A CN107968642A (en) | 2018-01-11 | 2018-01-11 | A kind of dual bootstrap sampling switch circuit of low voltage application |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201810024829.3A CN107968642A (en) | 2018-01-11 | 2018-01-11 | A kind of dual bootstrap sampling switch circuit of low voltage application |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN107968642A true CN107968642A (en) | 2018-04-27 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201810024829.3A Withdrawn CN107968642A (en) | 2018-01-11 | 2018-01-11 | A kind of dual bootstrap sampling switch circuit of low voltage application |
Country Status (1)
| Country | Link |
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| CN (1) | CN107968642A (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110907711A (en) * | 2019-11-20 | 2020-03-24 | 武汉鸿志高测电气技术有限公司 | Nuclear phase and phasing device and method |
| CN111049508A (en) * | 2019-12-31 | 2020-04-21 | 湖南国科微电子股份有限公司 | Method for inhibiting leakage current of sampling switch and sampling switch |
| CN113014240A (en) * | 2019-12-19 | 2021-06-22 | 圣邦微电子（北京）股份有限公司 | Control circuit of signal switch tube and analog switch circuit |
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| CN101577545A (en) * | 2008-05-07 | 2009-11-11 | 中国科学院电子学研究所 | Dual bootstrap and voltage compensation technology-based A/D converter sampling switch |
| WO2015135168A1 (en) * | 2014-03-13 | 2015-09-17 | 深圳普得技术有限公司 | Led driving circuit compatible with silicon-controlled dimmer |
| CN105119604A (en) * | 2015-09-21 | 2015-12-02 | 东南大学 | Bootstrap switch circuit suitable for sampling of an analog-to-digital converter in a low power and voltage condition |
| CN106160743A (en) * | 2016-07-06 | 2016-11-23 | 电子科技大学 | A kind of boot-strapped switch circuit for sampling hold circuit |
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2018
- 2018-01-11 CN CN201810024829.3A patent/CN107968642A/en not_active Withdrawn
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101577545A (en) * | 2008-05-07 | 2009-11-11 | 中国科学院电子学研究所 | Dual bootstrap and voltage compensation technology-based A/D converter sampling switch |
| WO2015135168A1 (en) * | 2014-03-13 | 2015-09-17 | 深圳普得技术有限公司 | Led driving circuit compatible with silicon-controlled dimmer |
| CN105119604A (en) * | 2015-09-21 | 2015-12-02 | 东南大学 | Bootstrap switch circuit suitable for sampling of an analog-to-digital converter in a low power and voltage condition |
| CN106160743A (en) * | 2016-07-06 | 2016-11-23 | 电子科技大学 | A kind of boot-strapped switch circuit for sampling hold circuit |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110907711A (en) * | 2019-11-20 | 2020-03-24 | 武汉鸿志高测电气技术有限公司 | Nuclear phase and phasing device and method |
| CN113014240A (en) * | 2019-12-19 | 2021-06-22 | 圣邦微电子（北京）股份有限公司 | Control circuit of signal switch tube and analog switch circuit |
| CN113014240B (en) * | 2019-12-19 | 2022-10-14 | 圣邦微电子（北京）股份有限公司 | Control circuit of signal switch tube and analog switch circuit |
| CN111049508A (en) * | 2019-12-31 | 2020-04-21 | 湖南国科微电子股份有限公司 | Method for inhibiting leakage current of sampling switch and sampling switch |
| CN111049508B (en) * | 2019-12-31 | 2023-10-31 | 湖南国科微电子股份有限公司 | Method for inhibiting leakage current of sampling switch and sampling switch |
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