CN111049508A - Method for inhibiting leakage current of sampling switch and sampling switch - Google Patents
Method for inhibiting leakage current of sampling switch and sampling switch Download PDFInfo
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- H03K17/51—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used
- H03K17/56—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices
Abstract
The invention discloses a method for inhibiting leakage current of a sampling switch and the sampling switch, wherein the on-resistance of a switch tube can not change along with the change of input signal voltage by controlling the difference of gate leakage voltages of a first MOS switch tube and a second MOS switch tube to be kept unchanged when the sampling switch enters a sampling stage; by controlling the drain voltage of the second MOS switch tube to be kept as the voltage of the first power supply when the sampling switch enters the holding stage, the voltage of the output signal of the sampling switch can not change along with the change of the voltage of the input signal.
Description
Technical Field
The invention relates to the technical field of analog integrated circuits, in particular to a method for inhibiting leakage current of a sampling switch and the sampling switch.
Background
In recent years, with the further improvement of performance indexes of analog-to-digital converters, especially with the continuous development of integrated circuit process technologies, research on high-precision analog-to-digital converters is more and more intensive. A successive approximation analog-to-digital converter (SAR ADC) is an ultra-low power consumption analog-to-digital converter with high precision and low conversion rate, and is widely applied to wearable equipment, medical equipment and other equipment. The sampling switch is a very important module in SAR ADC, and the performance of the sampling switch greatly affects the performance of the SAR ADC.
In the prior art, the sampling switch can keep high linearity by a gate voltage bootstrap technology. However, with the further development and progress of the process, many circuits adopt the very advanced process, such as 14nm, 22nm, etc., so that the area of the circuit can be reduced, the cost of the chip can be saved, and the power consumption of the circuit can be reduced. However, the advanced process has some problems, one of which is the leakage problem at the source and drain ends of the sampling switch, and the leakage problem affects the performance of the sampling switch.
Disclosure of Invention
In order to solve the above technical problems, the present invention provides a method for suppressing a leakage current of a sampling switch and the sampling switch, which can suppress the leakage current of the sampling switch and improve the reliability of the sampling switch.
The invention provides a sampling switch on one hand, which comprises a first MOS switch tube, a second MOS switch tube, a grid voltage lifting circuit, a grid voltage releasing circuit and a leakage voltage holding circuit;
the drain electrode of the first MOS switch tube is connected with an input signal, the source electrode of the first MOS switch tube is connected with the drain electrode of the second MOS switch tube, the grid electrode of the first MOS switch tube is connected with the grid electrode of the second MOS switch tube, and the source electrode of the second MOS switch tube is connected with an output signal;
the grid voltage boosting circuit is respectively connected with the grid electrode of the first MOS switch tube, the grid electrode of the second MOS switch tube and the drain electrode of the first MOS switch tube, and is used for boosting the grid voltage of the first MOS switch tube and the grid voltage of the second MOS switch tube under the control of a first clock signal, controlling the first MOS switch tube and the second MOS switch tube to be conducted, and keeping the grid leakage voltage difference of the first MOS switch tube and the second MOS switch tube unchanged when the first MOS switch tube and the second MOS switch tube are conducted;
the grid voltage release circuit is respectively connected with the grid electrode of the first MOS switch tube and the grid electrode of the second MOS switch tube and is used for releasing the grid voltage of the first MOS switch tube and the grid voltage of the second MOS switch tube under the control of a second clock signal and controlling the first MOS switch tube and the second MOS switch tube to be disconnected; wherein the second clock signal is an inverted signal of the first clock signal;
and the drain voltage holding circuit is respectively connected with a first power supply and the drain electrode of the second MOS switch tube and is used for holding the drain electrode voltage of the second MOS switch tube as the voltage of the first power supply under the control of the second clock signal.
Preferably, the gate voltage boost circuit includes:
the circuit comprises a bootstrap capacitor, a capacitor charging branch, a capacitor discharging branch and a grid voltage boosting branch;
the capacitor charging branch is respectively connected with a second power supply, the grid electrode of the first MOS switch tube, the grid electrode of the second MOS switch tube and the upper polar plate of the bootstrap capacitor and is used for charging the bootstrap capacitor;
the capacitor discharge branch is respectively connected with a lower pole plate of the bootstrap capacitor, a drain electrode of the first MOS switch tube and the ground and is used for discharging the bootstrap capacitor;
the grid voltage boosting branch circuit is respectively connected with the grid electrode of the first MOS switch tube, the grid electrode of the second MOS switch tube, the drain electrode of the first MOS switch tube and the grid voltage bleeder circuit, and is also connected with a connection node of the capacitor charging branch circuit and the upper polar plate of the bootstrap capacitor, and is used for boosting the grid voltage of the first MOS switch tube and the second MOS switch tube into the sum of the voltage of the input signal and the voltage of the second power supply under the control of the first clock signal by utilizing the characteristic that the total charge stored in the bootstrap capacitor is unchanged.
Preferably, the capacitor charging branch comprises a first PMOS transistor, a gate of the first PMOS transistor is connected to a gate of the first MOS switch transistor and a gate of the second MOS switch transistor, a source of the first PMOS transistor is connected to the second power supply, and a drain of the first PMOS transistor is connected to an upper plate of the bootstrap capacitor and the gate voltage boost branch.
Preferably, the capacitor discharge branch includes a first NMOS transistor, a gate of the first NMOS transistor is connected to the first clock signal, a drain of the first NMOS transistor is connected to the lower plate of the bootstrap capacitor and the gate voltage boosting branch, and a source of the first NMOS transistor is grounded.
Preferably, the gate voltage boosting branch circuit includes a phase inverter, a second PMOS transistor, a second NMOS transistor and a third NMOS transistor, a drain of the second PMOS transistor is connected to a connection node between the capacitor charging branch circuit and an upper electrode plate of the bootstrap capacitor, a source of the second PMOS transistor is connected to a gate of the first MOS transistor, a gate of the second NMOS transistor, a gate of the third NMOS transistor and the gate voltage bleeder circuit, a gate of the second PMOS transistor is simultaneously connected to a drain of the third NMOS transistor and a signal output end of the phase inverter, a drain of the second NMOS transistor is connected to a source of the third NMOS transistor, a connection fulcrum between the bootstrap capacitor and the capacitor discharging branch circuit, a source of the second NMOS transistor is connected to a drain of the first MOS transistor, and a gate of the second NMOS transistor is connected to a gate of the first MOS transistor, The gate of the second MOS switch tube and the gate of the third NMOS tube, the source of the third NMOS tube is connected with the connection node of the bootstrap capacitor and the capacitor discharge branch, the drain of the third NMOS tube is connected with the signal output end of the phase inverter, the gate of the third NMOS tube is connected with the gate of the first MOS switch tube and the gate of the second MOS switch tube, the signal input end of the phase inverter is connected with the first clock signal, and the phase inverter is also respectively connected with the second power supply and the connection node of the bootstrap capacitor and the capacitor discharge branch.
Preferably, the gate voltage relief circuit includes a fourth NMOS transistor and a fifth NMOS transistor, a drain of the fourth NMOS transistor is connected to the gate of the first MOS switch transistor, the gate of the second MOS switch transistor, and the gate voltage boost circuit, respectively, a gate of the fourth NMOS transistor is connected to the second power supply, a source of the fourth NMOS transistor is connected to the drain of the fifth NMOS transistor, a gate of the fifth NMOS transistor is connected to the second clock signal, and a source of the fifth NMOS transistor is grounded.
Preferably, the drain voltage holding circuit includes a sixth NMOS transistor, a source of the sixth NMOS transistor is connected to the first power supply, a drain of the sixth NMOS transistor is connected to a drain of the second MOS switch transistor, and a gate of the sixth NMOS transistor is connected to the second clock signal.
The invention also provides a method for suppressing the leakage current of a sampling switch, which is applied to a sampling switch circuit, wherein the sampling switch circuit comprises a first MOS switch tube, a second MOS switch tube, a grid voltage boost circuit, a grid voltage bleeder circuit and a leakage voltage holding circuit, the drain electrode of the first MOS switch tube is connected with an input signal, the source electrode of the first MOS switch tube is connected with the drain electrode of the second MOS switch tube, the grid electrode of the first MOS switch tube is connected with the grid electrode of the second MOS switch tube, the source electrode of the second MOS switch tube is connected with an output signal, the grid voltage boost circuit is respectively connected with the grid electrode of the first MOS switch tube, the grid electrode of the second MOS switch tube and the drain electrode of the first MOS switch tube, the grid voltage bleeder circuit is respectively connected with the grid electrode of the first MOS switch tube and the grid electrode of the second MOS switch tube, the leakage voltage holding circuit is respectively connected with a first power supply and the drain electrode of the second MOS switch tube, the method for suppressing the leakage current of the sampling switch comprises the following steps:
under the control of a first clock signal, the grid voltage of the first MOS switch tube and the grid voltage of the second MOS switch tube are boosted by using the grid voltage boosting circuit, the first MOS switch tube and the second MOS switch tube are controlled to be conducted so as to sample the input signal, and the grid leakage voltage difference of the first MOS switch tube and the second MOS switch tube is kept unchanged when the first MOS switch tube and the second MOS switch tube are conducted;
under the control of a second clock signal, the grid voltage of the first MOS switching tube and the grid voltage of the second MOS switching tube are released by using the grid voltage release circuit, and the first MOS switching tube and the second MOS switching tube are controlled to be disconnected so as to keep the input signal; under the control of the second clock signal, the drain voltage of the second MOS switch tube is kept to be the voltage of the first power supply by using the drain voltage keeping circuit; wherein the second clock signal is an inverted signal of the first clock signal.
The invention has at least the following beneficial effects:
according to the invention, the voltage difference between the grid and the drain of the first MOS switch tube and the second MOS switch tube is controlled to be kept unchanged when the sampling switch enters a sampling stage, so that the on-resistance of the switch tube is not changed along with the change of the voltage of an input signal; by controlling the drain voltage of the second MOS switch tube to be kept as the voltage of the first power supply when the sampling switch enters the holding stage, the voltage of the output signal of the sampling switch can be enabled not to change along with the change of the voltage of the input signal, so that the leakage current of the sampling switch is restrained, and the reliability of the sampling switch is improved.
Drawings
In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings needed to be used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only some embodiments described in the present application, and other drawings can be obtained by those skilled in the art without creative efforts.
FIG. 1 is a circuit diagram of a conventional sampling switch;
FIG. 2 is an equivalent circuit diagram of a gate voltage bootstrapped switch circuit;
fig. 3 is a circuit structure diagram of a sampling switch according to an embodiment of the present invention;
FIG. 4 is an equivalent circuit diagram of a successive approximation analog-to-digital converter circuit;
FIG. 5 is a state diagram of capacitors in a differential capacitor array after sampling of a successive approximation analog-to-digital converter circuit is completed;
FIG. 6 is a diagram illustrating a trend of voltage changes of capacitor plates in a differential capacitor array after sampling of a successive approximation analog-to-digital converter circuit is completed;
fig. 7 is a circuit structure diagram of another sampling switch according to an embodiment of the present invention;
fig. 8 is a flowchart illustrating a method for suppressing leakage current of a sampling switch according to an embodiment of the present invention.
Detailed Description
The core of the invention is to provide a method for inhibiting leakage current of a sampling switch and the sampling switch, which can ensure that the on-resistance of a switch tube does not change along with the change of the voltage of an input signal when the sampling switch enters a sampling stage and the voltage of an output signal of the sampling switch does not change along with the change of the voltage of the input signal when the sampling switch enters a holding stage, thereby inhibiting the leakage current of the sampling switch, improving the reliability of the sampling switch,
in order to make the objects, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are some, but not all, embodiments of the present invention. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
Fig. 1 shows a circuit of a common sampling switch, wherein Clks is a clock control signal. When Clks is high level, MOS switch Ms is closed to sample the input signal, and when Clks is low level, MOS switch Ms is opened to hold the input signal. However, since the amplitude of the input signal is varied, the on-resistance of the MOS switch Ms is varied with the variation of the amplitude of the input voltage, so that the voltage at the sampling capacitor Cs is non-linear. Therefore, a gate voltage bootstrapped switch is generally used.
Fig. 2 shows an equivalent circuit of a gate-voltage bootstrapped switch circuit in the prior art, in which VDD is a power supply voltage, Clksb and Clks are clock control signals, and Vin is an input signal. When the clock control signal Clksb is at high level, the switches s1, s2, s5 are closed, the switches s3, s4 are opened, the voltage of the upper plate of the bootstrap capacitor C1 is VDD, the voltage of the lower plate is 0, the gate voltage of the switch tube Ms is 0, and the circuit is in the hold stage. When Clksb is at a low level, the switches s1, s2 and s5 are switched off, the switches s3 and s4 are switched on, the two electrode plates of the bootstrap capacitor C1 float, the voltage difference between the electrode plates is VDD, and when an input signal Vin changes, the grid voltage of the switch tube Ms is Vin + VDD, so that the grid voltage of the switch tube Ms and the voltage difference of the input voltage are the same in a sampling stage and are fixed to VDD, the on-resistance of the sampling switch does not change along with the amplitude of the input voltage, and the non-linear performance of the sampling circuit is better.
However, as mentioned in the background art, there is a leakage problem between the source and drain of the switch transistor Ms, and the leakage problem affects the performance of the sampling switch. Specifically, after sampling by the sampling switch is finished, the switching tube Ms is in an off state, and the voltage of the sampling capacitor Cs is theoretically kept at a fixed value. However, when the input voltage changes, because there is a leakage problem at the source and drain ends of the switch tube Ms, even if the switch tube Ms is disconnected, there is a leakage current flowing into or out of the sampling capacitor Cs, which causes the voltage on the sampling capacitor Cs to change, thereby affecting the performance of the sampling switch. It should be noted that the magnitude of the leakage current is related to the magnitude of the voltage difference between the two terminals of the switch tube Ms, and the larger the voltage difference between the two terminals, the larger the leakage current.
In view of the above, an aspect of the present invention provides a sampling switch, referring to fig. 3, the sampling switch includes:
the circuit comprises a first MOS switch tube Ms1, a second MOS switch tube Ms2, a grid voltage boosting circuit 1, a grid voltage bleeder circuit 2 and a leakage voltage holding circuit 3;
the drain electrode of the first MOS switch tube Ms1 is connected with the input signal Vin, the source electrode of the first MOS switch tube Ms1 is connected with the drain electrode of the second MOS switch tube Ms2, the gate electrode of the first MOS switch tube Ms1 is connected with the gate electrode of the second MOS switch tube Ms2, and the source electrode of the second MOS switch tube Ms2 is connected with the output signal Von;
the gate voltage boosting circuit 1 is respectively connected with the gate of the first MOS switch tube Ms1, the gate of the second MOS switch tube Ms2 and the drain of the first MOS switch tube Ms1, and is configured to boost the gate voltages of the first MOS switch tube Ms1 and the second MOS switch tube Ms2 under the control of the first clock signal Clks, control the first MOS switch tube Ms1 and the second MOS switch tube Ms2 to be turned on, and keep the gate-drain voltage difference between the first MOS switch tube Ms1 and the second MOS switch tube Ms2 when turned on unchanged;
the gate voltage bleeder circuit 2 is respectively connected with the gate of the first MOS switch tube Ms1 and the gate of the second MOS switch tube Ms2, and is used for bleeding gate voltages of the first MOS switch tube Ms1 and the second MOS switch tube Ms1 under the control of the second clock signal Clksb and controlling the first MOS switch tube Ms1 and the second MOS switch tube Ms2 to be disconnected; wherein the second clock signal Clksb is an inverse signal of the first clock signal Clks;
the drain voltage holding circuit 3 is respectively connected to the first power supply and the drain of the second MOS switch transistor Ms2, and is used for holding the drain voltage of the second MOS switch transistor Ms2 as the voltage of the first power supply under the control of the second clock signal Clksb.
In the embodiment of the present invention, two switching tubes for sampling are provided, and are respectively a first MOS switching tube Ms1 and a second MOS switching tube Ms2, where a drain of the first MOS switching tube Ms1 is connected to the input signal Vin, and a source of the second MOS switching tube Ms2 is connected to the output signal Von. When the first clock signal Clks is at a high level, the gate voltage of the first MOS switch tube Ms1 and the gate voltage of the second MOS switch tube Ms2 are raised by the gate voltage raising circuit 1, so that the first MOS switch tube Ms1 and the second MOS switch tube Ms2 can both be turned on, the sampling switch enters a sampling stage, at this time, the gate voltage difference between the first MOS switch tube Ms1 and the second MOS switch tube Ms2 when turned on is controlled by the gate voltage raising circuit 1 to be kept unchanged, and the on-resistance of the sampling switch can not be changed along with the change of the voltage of the input signal Vin; when the second clock signal Clksb is at high level, the gate voltage of the first MOS switch tube Ms1 and the second MOS switch tube Ms1 is controlled by the gate voltage bleeder circuit 2 to be bled, so that the first MOS switch tube Ms1 and the second MOS switch tube Ms2 are both turned off, the sampling switch enters the holding stage, at this time, the drain voltage of the second MOS switch tube Ms2 is held as the voltage of the first power supply by the drain voltage holding circuit 3, compared with the prior art, after the sampling is finished, a fixed potential, that is, the voltage of the first power supply, is connected to the input end of the switch tube, and it can be seen that the voltage of the output signal Von of the sampling switch will not change with the voltage change of the input signal Vin when the sampling switch enters the holding stage.
Specifically, the first MOS switch tube Ms1 and the second MOS switch tube Ms2 may both be NMOS tubes, and the voltage of the first power supply may be half of the reference voltage of the lower plate in the rear-stage differential capacitive array capacitor.
Fig. 4 shows an equivalent circuit of a successive approximation type analog-to-digital converter circuit, wherein input signals to be input are Vip and Vin respectively, and a lower plate in a differential capacitor array is selectively connected with one of a reference voltage vref and a ground voltage gnd respectively through a switch. After sampling is finished, the state of the capacitor in the differential capacitor array capacitor is shown in fig. 5, the comparator determines the output value of the highest bit of the ADC by comparing the sizes of Vip and Vin, the next step of capacitor turnover is judged, if Vip is larger than Vin, the capacitance of the highest bit of the lower half part is changed from 0 to 1, at the moment, the plate voltage of the capacitance of the lower half part is changed into Vin +0.5Vref, the capacitance of the upper half part is not turned, and the next comparator determines the output value of the next bit of the ADC by comparing the voltage values of Vin +0.5Vref and Vip; if Vip < Vin, the highest capacitance of the upper half part is changed from 0 to 1, at this time, the plate voltage of the upper half part capacitance is changed into Vip +0.5Vref, and the lower half part capacitance is not turned over. The next time the comparator determines the output value of the next bit of the ADC by comparing the voltage values of Vip +0.5Vref and Vin. By analogy, the voltage changes of the upper and lower capacitor electrode plates in the differential capacitor array capacitor can be obtained as shown in fig. 6.
It can be seen that the voltage of the two plates of the capacitor in the latter stage differential capacitor array capacitor is close to half of the reference voltage Vref, i.e. 0.5 Vref. In the embodiment of the invention, the drain electrode of the second MOS switch tube Ms2 is connected with a fixed potential which is half of a reference voltage, so that the voltage difference between two ends of the switch tube in the conversion process can be reduced, the voltage on the sampling capacitor is not changed along with the change of the input voltage after the sampling is finished, and the voltage difference between the source electrode and the drain electrode at the end of the second MOS switch tube Ms2 is reduced in the holding stage of the sampling switch because the voltage of Von is closer to half of the reference voltage, thereby inhibiting the leakage current of the switch tube and improving the reliability of the sampling switch.
As a preferred embodiment of the present invention, the gate voltage boost circuit 1 includes:
a bootstrap capacitor C2, a capacitor charging branch 11, a capacitor discharging branch 12 and a gate voltage boosting branch 13;
the capacitor charging branch 11 is respectively connected to the second power supply VDD, the gate of the first MOS switch tube Ms1, the gate of the second MOS switch tube Ms2, and the upper plate of the bootstrap capacitor C2, and is configured to charge the bootstrap capacitor C2;
the capacitor discharge branch 12 is respectively connected to a lower plate of the bootstrap capacitor C2, a drain of the first MOS switch tube Ms1, and ground, and is configured to discharge the bootstrap capacitor C2;
the gate voltage boosting branch circuit 13 is respectively connected to the gate of the first MOS switch tube Ms1, the gate of the second MOS switch tube Ms2, the drain of the first MOS switch tube Ms1, and the gate voltage bleeder circuit 2, and is further connected to a connection node between the capacitor charging branch circuit 11 and the upper plate of the bootstrap capacitor C2, and is configured to boost the gate voltages of the first MOS switch tube Ms1 and the second MOS switch tube Ms2 to the sum of the voltage Vin of the input signal and the voltage VDD of the second power supply under the control of the first clock signal Clks by using the characteristic that the total charge stored in the bootstrap capacitor C2 is not changed.
Referring to fig. 7, in some embodiments of the present invention, the capacitor charging branch 11 includes a first PMOS transistor M1, a gate of the first PMOS transistor M1 is connected to the gate of the first MOS switch transistor Ms1 and the gate of the second MOS switch transistor Ms2, a source of the first PMOS transistor M1 is connected to the second power VDD, and a drain of the first PMOS transistor M1 is connected to the upper plate of the bootstrap capacitor C2 and the gate voltage boosting branch 13.
As a preferred embodiment of the present invention, the capacitor discharging branch 12 includes a first NMOS transistor M2, a gate of the first NMOS transistor M2 is connected to the first clock signal Clks, a drain of the first NMOS transistor M2 is connected to a lower plate of the bootstrap capacitor C2 and the gate voltage boosting branch 13, and a source of the first NMOS transistor M2 is grounded.
As a preferred embodiment of the present invention, the gate voltage boost branch comprises an inverter, a second PMOS transistor M3, a second NMOS transistor M4 and a third NMOS transistor M5, the drain of the second PMOS transistor M3 is connected to the connection node between the capacitor charging branch 11 and the upper plate of the bootstrap capacitor C2, the source of the second PMOS transistor M3 is connected to the gate of the first MOS switch transistor Ms1, the gate of the second MOS switch transistor Ms2, the gate of the second NMOS transistor M4, the gate of the third NMOS transistor M5 and the gate voltage bleeder circuit 2, the gate of the second PMOS transistor M3 is simultaneously connected to the drain of the third NMOS transistor M5 and the signal output terminal of the inverter, the drain of the second NMOS transistor M4 is connected to the source of the third NMOS transistor M5, the connection pivot of the bootstrap capacitor C2 and the capacitor discharging branch 12, the source of the second NMOS transistor M4 is connected to the drain of the first MOS switch transistor Ms1, the gate of the second NMOS transistor M4 is connected to the gate of the first switch transistor Ms1, the gate of the second NMOS transistor M67 2 6 and the gate of the second MOS transistor M5, the source of the third NMOS transistor M5 is connected to the connection node between the bootstrap capacitor C2 and the capacitor discharge branch 12; the drain of the third NMOS transistor M5 is connected to the signal output terminal of the inverter, the gate of the third NMOS transistor M5 is connected to the gate of the first MOS switch transistor Ms1 and the gate of the second MOS switch transistor Ms2, the signal input terminal of the inverter is connected to the first clock signal Clks, and the inverter is further connected to the second power supply VDD and the connection node between the bootstrap capacitor C2 and the capacitor discharge branch 12, respectively.
As a preferred embodiment of the present invention, the gate voltage bleeder circuit 2 includes a fourth NMOS transistor M6 and a fifth NMOS transistor M7, a drain of the fourth NMOS transistor M6 is connected to the gate of the first MOS switch transistor Ms1, the gate of the second MOS switch transistor Ms2, and the gate voltage boost circuit 1, respectively, a gate of the fourth NMOS transistor M6 is connected to the second power VDD, a source of the fourth NMOS transistor M6 is connected to the drain of the fifth NMOS transistor M7, a gate of the fifth NMOS transistor M7 is connected to the second clock signal Clksb, and a source of the fifth NMOS transistor M7 is grounded.
In a preferred embodiment of the present invention, the drain holding circuit 3 includes a sixth NMOS transistor M8, a source of the sixth NMOS transistor M8 is connected to the first power supply, a drain of the sixth NMOS transistor M8 is connected to a drain of the second MOS switch transistor Ms2, and a gate of the sixth NMOS transistor M8 is connected to the second clock signal Clksb.
Specifically, the inverter includes a seventh NMOS transistor M9 and a third PMOS transistor M10, and the second power supply VDD is an operating power supply.
In the embodiment of the invention, the circuit principle of the sampling switch is as follows:
when the first clock signal Clks is at high level and the second clock signal Clksb is at low level, the sampling switch enters the sampling stage, the seventh NMOS transistor M9 is turned on, the gate of the second PMOS transistor M3 is grounded, so that the second PMOS transistor M3 is turned on, the gate voltages of the second NMOS transistor M4, the third NMOS transistor M5, the first MOS switch transistor Ms1 and the second MOS switch transistor Ms2 are raised, the first PMOS transistor M1, the first NMOS transistor M2 and the sixth NMOS transistor M8 are turned off, the second NMOS transistor M4 is turned on, the first MOS switch transistor Ms1 and the second MOS switch transistor Ms2 are both closed, at this time, the bootstrap capacitor C2 is connected to the drains of the first MOS switch transistor Ms1 and the second MOS switch transistor Ms2, since the total charge stored in the capacitor C2 does not change, the gate voltages of the first MOS switch transistor Ms1 and the second MOS switch transistor Ms2 are raised to the gate voltage of the first MOS switch transistor Ms1, and the gate voltage of the second MOS switch transistor Ms1 is raised to VDD, and the gate voltage of the second MOS switch transistor Ms2 is changed, the output voltage Von also changes, and at the same time, the gate voltages of the first MOS switch tube Ms1 and the second MOS switch tube Ms2 also change with the input voltage Vin, so that the gate-to-drain voltage difference of the switch tubes in the sampling stage can be kept unchanged.
When the first clock signal Clks is at low level and the second clock signal Clksb is at high level, the sampling switch enters into the holding stage, the first PMOS transistor M1, the first NMOS transistor M2 and the third PMOS transistor M10 are turned on, the gate of the second PMOS transistor M3 is connected to the second power voltage VDD, the second PMOS transistor M3 and the second NMOS transistor M4 are turned off, the first MOS switch transistor Ms1 and the second MOS switch transistor Ms2 are both turned off, at this time, the sixth NMOS transistor M8 is turned on, the voltage between the first MOS switch transistor Ms1 and the second MOS switch transistor Ms2 is fixed and 0.5Vref, so that the voltage of the output signal Von does not change with the change of the input signal Von during the holding stage of the sampling switch, and since the voltage of the output signal Von will approach to 0.5Vref more and more during the conversion, the voltage difference between the source and drain of the sampling switch Ms at the second MOS switch 2 is reduced, thereby reducing the leakage voltage difference of the sampling switch Ms leakage, the performance of the sampling switch is improved.
The above-described embodiments describe the structure of the sampling switch, and a method for suppressing the leakage current of the sampling switch applied to the sampling switch will be described below.
Referring to fig. 8, another aspect of the present invention provides a method for suppressing leakage current of a sampling switch, which is applied to a sampling switch circuit, the sampling switch circuit includes a first MOS switch, a second MOS switch, and a gate voltage boosting circuit, grid voltage bleeder circuit and leakage voltage holding circuit, input signal is connected to the drain electrode of first MOS switch tube, the drain electrode of second MOS switch tube is connected to the source electrode of first MOS switch tube, the grid electrode of second MOS switch tube is connected to the grid electrode of first MOS switch tube, output signal is connected to the source electrode of second MOS switch tube, grid voltage lifting circuit connects the grid electrode of first MOS switch tube respectively, the grid electrode of second MOS switch tube and the drain electrode of first MOS switch tube, grid voltage bleeder circuit connects the grid electrode of first MOS switch tube and the grid electrode of second MOS switch tube respectively, leakage voltage holding circuit connects the drain electrode of first power and second MOS switch tube respectively, the method of suppressing the sampling switch leakage current includes:
s100, under the control of a first clock signal, utilizing a grid voltage boosting circuit to boost grid voltages of a first MOS switching tube and a second MOS switching tube, controlling the first MOS switching tube and the second MOS switching tube to be conducted so as to sample an input signal, and keeping the grid leakage voltage difference of the first MOS switching tube and the second MOS switching tube unchanged when the first MOS switching tube and the second MOS switching tube are conducted;
in this embodiment, when the first clock signal is at a high level, the gate voltage of the first MOS switch tube and the gate voltage of the second MOS switch tube are raised by the gate voltage raising circuit, so that the first MOS switch tube and the second MOS switch tube are both turned on, the sampling switch enters a sampling stage, the gate leakage voltage difference between the first MOS switch tube Ms1 and the second MOS switch tube Ms2 controlled by the gate voltage raising circuit when turned on is kept unchanged, and the on-resistance of the sampling switch is not changed along with the change of the voltage of the input signal.
S200, under the control of a second clock signal, utilizing a grid voltage relief circuit to relieve grid voltages of a first MOS switching tube and a second MOS switching tube, and controlling the first MOS switching tube and the second MOS switching tube to be disconnected so as to keep an input signal; under the control of a second clock signal, the drain voltage of the second MOS switch tube is kept to be the voltage of the first power supply by using a drain voltage keeping circuit; wherein the second clock signal is an inverted signal of the first clock signal.
In this embodiment, when the second clock signal is at a high level, the gate voltage of the first MOS switch tube and the gate voltage of the second MOS switch tube are controlled to be released by the gate voltage release circuit, so that the first MOS switch tube and the second MOS switch tube are both turned off, the sampling switch enters a holding stage, at this time, the drain voltage of the second MOS switch tube is held as the voltage of the first power supply by the leakage voltage holding circuit, and after sampling is completed, since a fixed potential, i.e., the voltage of the first power supply, is connected to the input end of the switch tube, the voltage of the output signal of the sampling switch will not change with the change of the voltage of the input signal when the sampling switch enters the holding stage.
The embodiments in the present description are described in a progressive manner, each embodiment focuses on differences from other embodiments, and the same and similar parts among the embodiments are referred to each other. It is further noted that, in the present specification, relational terms such as first and second, and the like are used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Also, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising an … …" does not exclude the presence of other identical elements in a process, method, article, or apparatus that comprises the element.
The previous description of the disclosed embodiments is provided to enable any person skilled in the art to make or use the present invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other embodiments without departing from the spirit or scope of the invention. Thus, the present invention is not intended to be limited to the embodiments shown herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.
Claims (8)
1. A sampling switch is characterized by comprising a first MOS switch tube, a second MOS switch tube, a grid voltage lifting circuit, a grid voltage bleeder circuit and a leakage voltage holding circuit;
the drain electrode of the first MOS switch tube is connected with an input signal, the source electrode of the first MOS switch tube is connected with the drain electrode of the second MOS switch tube, the grid electrode of the first MOS switch tube is connected with the grid electrode of the second MOS switch tube, and the source electrode of the second MOS switch tube is connected with an output signal;
the grid voltage boosting circuit is respectively connected with the grid electrode of the first MOS switch tube, the grid electrode of the second MOS switch tube and the drain electrode of the first MOS switch tube, and is used for boosting the grid voltage of the first MOS switch tube and the grid voltage of the second MOS switch tube under the control of a first clock signal, controlling the first MOS switch tube and the second MOS switch tube to be conducted, and keeping the grid leakage voltage difference of the first MOS switch tube and the second MOS switch tube unchanged when the first MOS switch tube and the second MOS switch tube are conducted;
the grid voltage release circuit is respectively connected with the grid electrode of the first MOS switch tube and the grid electrode of the second MOS switch tube and is used for releasing the grid voltage of the first MOS switch tube and the grid voltage of the second MOS switch tube under the control of a second clock signal and controlling the first MOS switch tube and the second MOS switch tube to be disconnected; wherein the second clock signal is an inverted signal of the first clock signal;
and the drain voltage holding circuit is respectively connected with a first power supply and the drain electrode of the second MOS switch tube and is used for holding the drain electrode voltage of the second MOS switch tube as the voltage of the first power supply under the control of the second clock signal.
2. The sampling switch of claim 1, wherein the gate voltage boost circuit comprises:
the circuit comprises a bootstrap capacitor, a capacitor charging branch, a capacitor discharging branch and a grid voltage boosting branch;
the capacitor charging branch is respectively connected with a second power supply, the grid electrode of the first MOS switch tube, the grid electrode of the second MOS switch tube and the upper polar plate of the bootstrap capacitor and is used for charging the bootstrap capacitor;
the capacitor discharge branch is respectively connected with a lower pole plate of the bootstrap capacitor, a drain electrode of the first MOS switch tube and the ground and is used for discharging the bootstrap capacitor;
the grid voltage boosting branch circuit is respectively connected with the grid electrode of the first MOS switch tube, the grid electrode of the second MOS switch tube, the drain electrode of the first MOS switch tube and the grid voltage bleeder circuit, and is also connected with a connection node of the capacitor charging branch circuit and the upper polar plate of the bootstrap capacitor, and is used for boosting the grid voltage of the first MOS switch tube and the second MOS switch tube into the sum of the voltage of the input signal and the voltage of the second power supply under the control of the first clock signal by utilizing the characteristic that the total charge stored in the bootstrap capacitor is unchanged.
3. The sampling switch according to claim 2, wherein the capacitor charging branch comprises a first PMOS transistor, a gate of the first PMOS transistor is connected to a gate of the first MOS switch transistor and a gate of the second MOS switch transistor, a source of the first PMOS transistor is connected to the second power supply, and a drain of the first PMOS transistor is connected to an upper plate of the bootstrap capacitor and the gate voltage boosting branch.
4. The sampling switch according to claim 2, wherein the capacitor discharging branch comprises a first NMOS transistor, a gate of the first NMOS transistor is connected to the first clock signal, a drain of the first NMOS transistor is connected to the lower plate of the bootstrap capacitor and the gate voltage boosting branch, and a source of the first NMOS transistor is grounded.
5. The sampling switch according to claim 2, wherein the gate voltage boosting branch circuit comprises an inverter, a second PMOS transistor, a second NMOS transistor and a third NMOS transistor, a drain of the second PMOS transistor is connected to a connection node between the capacitor charging branch circuit and an upper electrode plate of the bootstrap capacitor, a source of the second PMOS transistor is connected to a gate of the first MOS transistor, a gate of the second NMOS transistor, a gate of the third NMOS transistor and the gate voltage bleeding circuit, a gate of the second PMOS transistor is simultaneously connected to a drain of the third NMOS transistor and a signal output end of the inverter, a drain of the second NMOS transistor is connected to a source of the third NMOS transistor, a connection fulcrum between the bootstrap capacitor and the capacitor discharging branch circuit, a source of the second NMOS transistor is connected to a drain of the first MOS transistor, and a gate of the second NMOS transistor is connected to a gate of the first MOS transistor, a drain of the first NMOS transistor, a gate of the second NMOS transistor is connected to a connection fulcrum between the gate of the first MOS, The gate of the second MOS switch tube and the gate of the third NMOS tube, the source of the third NMOS tube is connected with the connection node of the bootstrap capacitor and the capacitor discharge branch, the drain of the third NMOS tube is connected with the signal output end of the phase inverter, the gate of the third NMOS tube is connected with the gate of the first MOS switch tube and the gate of the second MOS switch tube, the signal input end of the phase inverter is connected with the first clock signal, and the phase inverter is also respectively connected with the second power supply and the connection node of the bootstrap capacitor and the capacitor discharge branch.
6. The sampling switch of claim 1, wherein the gate voltage bleeder circuit comprises a fourth NMOS transistor and a fifth NMOS transistor, a drain of the fourth NMOS transistor is connected to the gate of the first MOS transistor, the gate of the second MOS transistor, and the gate voltage boost circuit, respectively, a gate of the fourth NMOS transistor is connected to the second power supply, a source of the fourth NMOS transistor is connected to a drain of the fifth NMOS transistor, a gate of the fifth NMOS transistor is connected to the second clock signal, and a source of the fifth NMOS transistor is grounded.
7. The sampling switch according to any one of claims 1 to 6, wherein the drain hold circuit comprises a sixth NMOS transistor, a source of the sixth NMOS transistor is connected to the first power supply, a drain of the sixth NMOS transistor is connected to a drain of the second MOS switch transistor, and a gate of the sixth NMOS transistor is connected to the second clock signal.
8. A method for suppressing leakage current of a sampling switch is characterized in that the method is applied to a sampling switch circuit, the sampling switch circuit comprises a first MOS switch tube, a second MOS switch tube, a grid voltage boosting circuit, a grid voltage bleeder circuit and a leakage voltage holding circuit, the drain electrode of the first MOS switch tube is connected with an input signal, the source electrode of the first MOS switch tube is connected with the drain electrode of the second MOS switch tube, the grid electrode of the first MOS switch tube is connected with the grid electrode of the second MOS switch tube, the source electrode of the second MOS switch tube is connected with an output signal, the grid voltage boosting circuit is respectively connected with the grid electrode of the first MOS switch tube, the grid electrode of the second MOS switch tube and the drain electrode of the first MOS switch tube, the grid voltage bleeder circuit is respectively connected with the grid electrode of the first MOS switch tube and the grid electrode of the second MOS switch tube, the leakage voltage holding circuit is respectively connected with a first power supply and the drain electrode of the second MOS switch tube, the method for suppressing the leakage current of the sampling switch comprises the following steps:
under the control of a first clock signal, the grid voltage of the first MOS switch tube and the grid voltage of the second MOS switch tube are boosted by using the grid voltage boosting circuit, the first MOS switch tube and the second MOS switch tube are controlled to be conducted so as to sample the input signal, and the grid leakage voltage difference of the first MOS switch tube and the second MOS switch tube is kept unchanged when the first MOS switch tube and the second MOS switch tube are conducted;
under the control of a second clock signal, the grid voltage of the first MOS switching tube and the grid voltage of the second MOS switching tube are released by using the grid voltage release circuit, and the first MOS switching tube and the second MOS switching tube are controlled to be disconnected so as to keep the input signal; under the control of the second clock signal, the drain voltage of the second MOS switch tube is kept to be the voltage of the first power supply by using the drain voltage keeping circuit; wherein the second clock signal is an inverted signal of the first clock signal.
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| CN112910464A (en) * | 2021-01-14 | 2021-06-04 | 湖南国科微电子股份有限公司 | Sampling switch, analog-to-digital converter and electronic equipment |
| CN117544150A (en) * | 2024-01-09 | 2024-02-09 | 杰华特微电子股份有限公司 | High-side sampling circuit and power supply system |
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| CN110365325A (en) * | 2018-04-11 | 2019-10-22 | 中芯国际集成电路制造(上海)有限公司 | Boot-strapped switch circuit, sampling and keep module and electronic device |
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| CN117544150A (en) * | 2024-01-09 | 2024-02-09 | 杰华特微电子股份有限公司 | High-side sampling circuit and power supply system |
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