CN113078905A

CN113078905A - Sample hold circuit, analog-to-digital converter and wifi chip

Info

Publication number: CN113078905A
Application number: CN202110344042.7A
Authority: CN
Inventors: 何力; 杨奕
Original assignee: Kweifa Semiconductor Suzhou Co ltd
Current assignee: Kweifa Semiconductor Suzhou Co ltd
Priority date: 2021-03-30
Filing date: 2021-03-30
Publication date: 2021-07-06

Abstract

The invention discloses a sample-and-hold circuit, an analog-digital converter and a wifi chip, wherein the sample-and-hold circuit comprises a clock generation sub-circuit, a grid voltage bootstrap sub-circuit and a sampling field effect tube, the grid voltage bootstrap sub-circuit outputs a second control signal for controlling the sampling hold circuit to be in a tracking stage to a grid electrode of the sampling field effect tube, the voltage of the second control signal is the sum of a conducting voltage and an input voltage of a signal input end, and the conducting voltage is greater than the input voltage of an external power supply; the circuit can not introduce non-ideal harmonic waves, eliminates the interference of input voltage of a signal input end to the sampling field effect transistor, can not generate negative influence on the output signal-to-noise ratio of the analog-to-digital converter, simultaneously reduces the on-resistance of the sampling field effect transistor due to the fact that the on-voltage greater than the input voltage is included, improves the response speed of a switch, ensures that the input signal and the output signal of the sampling holding circuit are in strict linear relation, and improves the performance of the circuit.

Description

Sample hold circuit, analog-to-digital converter and wifi chip

Technical Field

The present invention relates to a sample-and-hold circuit, and more particularly, to an analog-to-digital converter and a wifi chip having the sample-and-hold circuit.

Background

In the process of sampling an analog input signal, an analog-to-digital converter (ADc) mostly has a sample-and-hold circuit, and the sample-and-hold circuit is used for stabilizing the continuously changing analog input signal and alternately performing two stages of tracking and holding.

The existing sample-and-hold circuit has some problems, such as linear distortion, and the sampled signal acquired by the sample-and-hold circuit has non-ideal harmonic, so that when the circuit is used in a high-precision analog-to-digital converter, the output signal-to-noise ratio of the analog-to-digital converter is negatively affected. When the problem of linear distortion is solved, other electrical components are introduced in the prior art, the parasitic capacitance of the circuit is inevitably increased, the on-resistance is increased, and the overall speed of the circuit is slowed down, so that the overall performance is affected.

Disclosure of Invention

In order to solve the linear distortion of the sample-and-hold circuit in the prior art and improve other problems introduced when the problems are solved, the invention aims to provide a sample-and-hold circuit, an analog-to-digital converter and a wifi chip which do not introduce non-ideal harmonics, do not have negative influence on the output signal-to-noise ratio of the analog-to-digital converter and have high response speed.

In order to achieve the above object, an embodiment of the present invention provides a sample-and-hold circuit, including a clock generating sub-circuit, a gate voltage bootstrap sub-circuit, and a sampling fet, where the gate voltage bootstrap sub-circuit is respectively connected to an external power supply, a gate of the sampling fet, the clock generating sub-circuit, and a signal input terminal, the clock generating sub-circuit inputs a clock signal, the gate voltage bootstrap sub-circuit is configured to alternately output a first control signal and a second control signal to the gate of the sampling fet according to the clock signal and/or a signal output by the clock generating sub-circuit, the first control signal controls the sample-and-hold circuit to be in a hold stage, the second control signal controls the sample-and-hold circuit to be in a tracking stage, and a voltage of the second control signal is a sum of a turn-on voltage and an input voltage of the signal input terminal, the turn-on voltage is greater than an input voltage of the external power supply.

As a further improvement of the present invention, the gate voltage bootstrap sub-circuit includes a charge transfer unit and a node voltage reset unit, an input end of the charge transfer unit is connected to the source of the sampling field-effect transistor and inputs the input voltage of the signal input end, and an output end thereof is connected to the gate of the sampling field-effect transistor, and the charge transfer unit includes a first switch, a bootstrap unit and a second switch that are sequentially arranged along a current direction;

according to a clock signal clk and/or an inverted clock signal clkb complementary to the clock signal clk, the node voltage reset unit resets a node V3 between the first switch and the bootstrap unit, a node V4 between the bootstrap unit and the second switch, and a node V1 between the second switch and the gate of the sampling fet.

As a further improvement of the present invention, the clock generation sub-circuit is configured to input a clock signal clk and output a switch control signal clkt, when the sample-and-hold circuit switches from the hold phase to the tracking phase, the instantaneous level output by the switch control signal clkt changes abruptly and returns to the original level again, and the voltage of the node V4 rises from the low level and is greater than the sum of the external power supply and the input voltage of the signal input terminal.

As a further improvement of the present invention, the charge transfer unit further includes NMOS transistors M3 and M4 connected between the first switch and the bootstrap unit, gates of the NMOS transistors M3 and M4 both input the switch control signal clkt, the switch control signal clkt is continuously input at a low level, the transient level jump is switched from a low level to a high level, a drain of the NMOS transistor M3 is connected in series with a source of the NMOS transistor M4, a source of the NMOS transistor M3 is short-circuited with the drain of the NMOS transistor M4, and the drain of the NMOS transistor M3 and the source of the NMOS transistor M4 are at a node V2.

As a further improvement of the present invention, the clock generation sub-circuit includes a first inverter INV1 AND a second inverter INV2 respectively connected to the clock signal input terminal, the first inverter INV1 outputs the inverted clock signal clkb, the output terminal of the first inverter INV2 AND the clock signal input terminal are simultaneously connected to the input terminal of the AND gate AND, the output terminal of the AND gate AND outputs the switch control signal clkt.

As a further improvement of the present invention, the first switch is configured as an NMOS transistor M2, the gate of which is connected to the clock signal clk or the node V1, the second switch is configured as a PMOS transistor M8, the gate of which is connected to the inverted clock signal clkb or the node V2, and the bootstrap unit is configured as a MOS transistor with short-circuited capacitance or drain.

As a further improvement of the present invention, the node voltage reset unit includes:

one end of the NMOS tube M5 is connected with the node V3, and the other end of the NMOS tube is grounded and is controlled by the inverted clock signal clkb;

a PMOS transistor M6 with one end connected to the node V4 and the other end connected to an external power supply and controlled by the node V1;

a PMOS transistor M9 with one end connected to the node V2 and the other end connected to the external power source and controlled by the clock signal clk;

and an NMOS transistor M7 having one end connected to the node V1 and the other end connected to ground and controlled by the inverted clock signal clkb.

As a further improvement of the present invention, the gate voltage bootstrap sub-circuit further includes an operational amplifier, a positive phase input terminal of the operational amplifier is connected to the signal input terminal, and a negative phase input terminal thereof is short-circuited with an output terminal thereof and connected to the first switch.

To achieve one of the above objects, an embodiment of the present invention provides an analog-to-digital converter including the above sample-and-hold circuit.

To achieve one of the above objects, an embodiment of the present invention provides a wifi chip, which includes the above sample-and-hold circuit.

Compared with the prior art, the invention has the following beneficial effects: the circuit can not introduce non-ideal harmonic waves, eliminates the interference of input voltage of a signal input end to the sampling field effect transistor, can not generate negative influence on the output signal-to-noise ratio of the analog-to-digital converter, simultaneously reduces the on-resistance of the sampling field effect transistor due to the fact that the on-voltage greater than the input voltage is included, improves the response speed of a switch, ensures that the input signal and the output signal of the sampling holding circuit are in strict linear relation, and improves the performance of the circuit.

Drawings

FIG. 1 is a circuit block diagram of a sample-and-hold circuit according to an embodiment of the present invention;

FIG. 2 is a circuit block diagram of a sample-and-hold circuit according to another embodiment of the present invention;

Detailed Description

The present invention will be described in detail below with reference to specific embodiments shown in the drawings. These embodiments are not intended to limit the present invention, and structural, methodological, or functional changes made by those skilled in the art according to these embodiments are included in the scope of the present invention.

An embodiment of the present invention provides a sample-and-hold circuit, an analog-to-digital converter, and a wifi chip, where the sample-and-hold circuit does not introduce non-ideal harmonics, does not negatively affect the output signal-to-noise ratio of the analog-to-digital converter, and has a fast response speed.

As described in the background, many of the analog-to-digital converters are provided with a sample-and-hold circuit, which stabilizes the input of the analog signal by alternately operating in the tracking phase and the holding phase. The analog-to-digital converter of the embodiment is also used in a wifi chip, namely the sampling hold circuit is arranged in the wifi chip.

Specifically, the sample-and-hold circuit of the present embodiment, as shown in fig. 1 to fig. 2, includes a clock generation sub-circuit, a gate voltage bootstrap sub-circuit, and a sampling field-effect transistor, where the gate voltage bootstrap sub-circuit is respectively connected to an external power supply, a gate of the sampling field-effect transistor, the clock generation sub-circuit, and a signal input end, and the clock generation sub-circuit inputs a clock signal.

Two output ends of the grid voltage bootstrap sub-circuit are respectively connected with a grid electrode and a drain/source electrode of the sampling field effect tube so as to provide fixed grid source voltage for the sampling field effect tube, a signal input end is connected with one drain/source electrode of the sampling field effect tube so as to input an external analog signal to the sampling field effect tube, and the other drain/source electrode of the sampling field effect tube is connected with a signal output end so as to output the sampled analog signal. The sampling fet in this embodiment employs an NMOS transistor M1, which is turned on when a high level signal is input to its gate, and turned off when a low level signal is input to its gate, and the source of the NMOS transistor M1 inputs an analog signal and the drain thereof is connected to a signal output terminal.

The sample-and-hold circuit further comprises a holding capacitor C1, which is connected to the signal output terminal at one end and to ground at the other end to hold the sampled analog signal.

The grid voltage bootstrap sub-circuit is configured to alternately output a first control signal and a second control signal to the grid of the sampling field effect transistor according to the clock signal and/or the signal output by the clock generation sub-circuit, wherein the first control signal controls the sampling and holding circuit to be in a holding phase, and the second control signal controls the sampling and holding circuit to be in a tracking phase. The first control signal is a low level signal for controlling the NMOS transistor M1 to be turned off, the second control signal is a high level signal for controlling the NMOS transistor M1 to be turned on, the voltage of the second control signal is the sum of a turn-on voltage and an input voltage of the signal input terminal, the turn-on voltage is greater than the input voltage of the external power supply, and may also be recorded as the voltage of the second control signal is equal to k + Vdd + Vin, where k > 1, Vdd is the input voltage of the external power supply, and Vin is the input voltage of the signal input terminal.

And quantitative analysis, when the sample-and-hold circuit is in a tracking stage, the output voltage Vout of the signal output end meets the following conditions:

wherein the content of the first and second substances,

in the above equation, β is determined by the process and size of the NMOS transistor, Vth is the threshold voltage of the NMOS transistor, and s is the laplace operator, and it can be seen from the above equation that Vout and Vin have a strict linear relationship.

Particularly, when the problem that Vout and Vin have a strict linear relationship is solved, the introduced gate voltage self-raising sub-circuit inevitably introduces a large parasitic capacitance into the whole circuit, so that the gate voltage input to the NMOS transistor M1 is reduced compared with an ideal value, and may even be lower than the threshold voltage, and the overall speed of the circuit is affected. Therefore, K × Vdd-Vth is larger than Vdd-Vth of the conventional circuit, so that the problem that Vdd-Vth is smaller than 0 is avoided, and the value of K × Vdd-Vth is larger, so that the on-resistance of the NMOS transistor M1 is smaller, and the switching speed is faster.

Further, the gate voltage bootstrap sub-circuit includes a charge transfer unit and a node voltage reset unit, an input end of the charge transfer unit is connected to the source electrode of the sampling field effect transistor and inputs the input voltage of the signal input end, an output end of the charge transfer unit is connected to the gate electrode of the sampling field effect transistor, and the charge transfer unit includes a first switch, a bootstrap unit and a second switch which are sequentially arranged along a current direction;

Further, the clock generation sub-circuit is configured to input a clock signal clk and output a switch control signal clkt, when the sample-and-hold circuit switches from the hold phase to the tracking phase, the instantaneous level of the output of the switch control signal clkt changes abruptly and returns to the original level again, at this time, the voltage of the node V4 rises from the low level and is greater than the sum of the external power supply and the input voltage of the signal input terminal.

The sudden change of the instantaneous level means that, for example, the original level is a low level, the low level is kept in the holding phase clkt, but the level of the switch control signal clkt suddenly rises while the sample-and-hold circuit switches from the holding phase to the tracking phase, and then quickly falls back to the low level, and thereafter the switch control signal clkt maintains the low level even if the circuit still maintains the tracking phase until the sudden change occurs again at the moment when the circuit switches from the holding phase to the tracking phase again. If the original level is high level, the original level is suddenly reduced to low level at the moment when the circuit is switched from the keeping stage to the tracking stage, and then the original level is restored to high level.

Specifically, the charge transfer unit further includes NMOS transistors M3 and M4 connected between the first switch and the bootstrap unit, the gates of the NMOS transistors M3 and M4 both input the switch control signal clkt, the switch control signal clkt is continuously input with a low level, the transient level abrupt change is switched from the low level to the high level, the drain of the NMOS transistor M3 is connected in series with the source of the NMOS transistor M4, the source of the NMOS transistor M3 is short-circuited with the drain of the NMOS transistor M4, the drain of the NMOS transistor M3 and the source of the NMOS transistor M4 are a node V2, a node V3 is between the drain of the NMOS transistor M4 and the bootstrap unit, and a node between the first switch and the signal input terminal is labeled as V0.

The above-mentioned NMOS transistors M3 and M4 are suddenly changed from low level to high level corresponding to the switching control signal clkt, and of course, the NMOS transistors M3 and M4 may be replaced by PMOS transistors, at this time, the instantaneous sudden change of the switching control signal clkt is suddenly changed from high level to low level, and the specific structure thereof can be adjusted correspondingly by those skilled in the art according to the above-mentioned published principle.

In conjunction with this specific structure, the abrupt change in the instantaneous level of the switch control signal clkt output during the switching of the circuit from the hold phase to the tracking phase is to make the NMOS transistors M3 and M4 conduct only for a moment. At this moment, the purpose of boosting the voltage of the V3 node from the voltage of the V2 node can be achieved. The reason why the switch is turned on for a moment is that after V2 pushes up V3, NMOS transistors M3 and M4 are both turned off, thereby isolating the V2 node from the V0 node, so that the V0 node directly affects the change of the V3 node, otherwise V2 affects V0, and thus V3 cannot follow the change of V0. In addition, the influence of the parasitic capacitance at the node V2 can be avoided, and the specific boosting process and further principles refer to the working principle part below.

The specific structure of the clock generation sub-circuit is shown in fig. 1 or 2, the clock generation sub-circuit includes a first inverter INV1 AND a second inverter INV2 respectively connected to a clock signal input end, the first inverter INV1 outputs the inverted clock signal clkb, an output end of the first inverter INV2 AND the clock signal input end are simultaneously connected to an input end of an AND gate AND, AND an output end of the AND gate AND outputs the switch control signal clkt.

When the clock signal clk is at a low level, the inverted clock signal clkb output through the first inverter INV1 is at a high level, the level output by the AND gate AND is at a low level, AND when the clock signal clk is switched from a low level to a high level, the inverted clock signal clkb output through the first inverter INV1 is at a low level. At this time, clkt generates a voltage Vdd pulse with a duration INV2, and the NMOS transistor M4 is turned on during the duration INV2 under the action of the clkt pulse. The instantaneous time of the instantaneous mutation is the INV2 delay length.

If the NMOS transistors M3 AND M4 are replaced by PMOS transistors, the above abrupt change needs to be made by changing the AND gate AND of the clock generation sub-circuit to the nand gate when the high level is abruptly changed to the low level AND then restored to the high level.

Further, the first switch is configured as an NMOS transistor M2, a gate of which is connected to the clock signal clk or the node V1, the second switch is configured as a PMOS transistor M8, a gate of which is connected to the inverted clock signal clkb or the node V2, and the bootstrap unit is configured as a capacitor C2 or a MOS transistor with a shorted drain and source, as shown in fig. 1 and fig. 2, respectively. The voltage at the node V4 can be boosted to k × Vdd + Vin by the bootstrap effect of the bootstrap unit, and the boosting process is referred to the following working principle.

In this embodiment, the gate of the NMOS transistor M2 is connected to the node V1, and the gate of the PMOS transistor M8 is connected to the node V2. The effect of this is that in the following phase, the actual voltage value of V1 is greater than the high signal of clk, so the turn-on performance of NMOS transistor M2 is better after node V1 is connected. When clk goes high, the voltage at node V2 does not go transient and does not interfere with the voltage at V4 through the gate-source parasitic capacitance of M8.

And, the node voltage reset unit includes:

one end of the NMOS tube M5 is connected with the node V3, the other end of the NMOS tube M5 is grounded and is controlled by the inverted clock signal clkb, when the grid of the NMOS tube M5 is connected with a low level signal, the node V3 is grounded, and the voltage drop is 0;

the PMOS transistor M6 is connected with the node V4 at one end and the external power supply at the other end and is controlled by the node V1, and when the grid of the PMOS transistor M6 is connected with a low-level signal, the voltage of the node V4 is raised to the voltage VDD of the external power supply;

the PMOS tube M9 is connected with the node V2 at one end and an external power supply at the other end and is controlled by a clock signal clk, and when the grid of the PMOS tube M9 is connected with a low-level signal, the voltage of the node V2 is raised to the voltage VDD of the external power supply;

one end of the NMOS tube M7 is connected with the node V1, the other end is grounded and is controlled by the inverted clock signal clkb, when the gate of the NMOS tube M7 is connected with a low level signal, the node V1 is grounded, and the voltage is dropped to 0.

Further, the gate voltage bootstrap sub-circuit further includes an operational amplifier OP1, a non-inverting input terminal of the operational amplifier OP1 is connected to the signal input terminal, and an inverting input terminal thereof is shorted with an output terminal thereof and is connected to the first switch. A unity gain buffer is formed, which has the function of making V0 equal to Vin, and making V0 have driving capability, so that the magnitude of V0 signal does not change due to the change of load intensity of the node connected with it, and the operational amplifier OP1 is not provided, which has the function of making the following effect better.

Specifically, the operating principle of the circuit is as follows:

a maintaining stage:

when the clock signal clk is at 0 (low, 0), clkb generated via the inverter INV1 is 1 (high, Vdd). At this time, the NMOS transistors M5 and M7 (with gates connected to clkb) and the PMOS transistor M9 (with gates connected to clk) are both turned on. The voltage drop of the node V1 is 0 under the action of the NMOS transistor M7, the voltage drop of the node V3 is 0 under the action of the NMOS transistor M5, the voltage of the node V2 becomes Vdd under the action of the PMOS transistor M9, the gate of the PMOS transistor M6 is connected to V1, the PMOS transistor M6 is turned on at this time, and the voltage of the node V4 rises to Vdd. The voltage between the nodes V4 and V3 is Vdd, and the capacitor C2 stores the charge Q Vdd × C2. At this time, since V1 is equal to 0, the NMOS transistor M1 is in the off state, and the value of Vout remains unchanged, that is, when clk is equal to 0, the sample-and-hold circuit is in the hold phase.

A tracking stage:

when the clock signal clk changes from 0 to 1 (from 0 to Vdd), the inverted clock signal clkb falls from Vdd to 0. At this time, the NMOS transistors M5 and M7 and the PMOS transistor M9 are all disconnected. When the clock signal clk rises from 0 to Vdd, the switch control signal clkt generates a high-level pulse with a pulse width delayed by INV 2. The NMOS transistor M4 will turn on during the time delay of INV2 under the action of clkt pulse. Before the NMOS transistor M4 is turned on, since V2 is high voltage and V3 is low voltage (participate in the holding phase), when the NMOS transistor M4 is turned on, the voltage of V2 decreases and the voltage of V3 increases, V4 and V3 are ac-coupled via C2 (or MOS transistor with short drain-source), and V4 increases under the effect of V3 increasing. The gate of the PMOS transistor M8 is connected to V2, and the gate voltage of the PMOS transistor M8 is reduced, so that the PMOS transistor M8 is turned on, and V1 is raised under the action of V4. The gate of the PMOS transistor M6 is connected to V1, so M6 is turned off. After the clkt high-level pulse returns to the low level, the NMOS transistor M4 continues to keep the off state, and at this time, the voltage of V1 rises, the gate voltage of NMOS transistor M2 rises, and M2 turns on, so V0 becomes V3. In addition, the gate of the NMOS transistor M3 is also connected to low level clkt, at this time, M3 is turned off, and V2 keeps low level, so that the PMOS transistor M8 keeps on. The output terminal of the operational amplifier OP1 is connected to the negative input terminal, and V0 is Vin. At this time, V0 is equal to V3, M6, M7 and M9 are disconnected, the node (V4) where the upper plate of the capacitor C2 is located is in a high-impedance state, and there is no path for the charge to flow, so that the charge stored in the capacitor C2 remains unchanged, and when V3 changes, V4 changes by the same magnitude as V3. V4 starts from the time when clk is 0, the voltage is Vdd, then it rises under the action of V3, before V4 changes following V3, the initial voltage of V4 is set to satisfy V4 k Vdd (at this time, k > 1 since it rises under the action of V3 on the basis of Vdd, so that k reaches 1.5), and after V4 changes following V3, the value satisfies: v4 k Vdd + V3 k Vdd + V0 k Vdd + Vin. At this time, the PMOS transistor M8 is turned on, so V1 is equal to V4.

Briefly, the tracking phase is divided into two steps, the first step is to raise the gate voltage of the NMOS transistor M1: after the rising edge of the clock signal clk comes, the switch control signal clkt is turned on for a short time, and the gate voltage of the NMOS transistor M1 is raised to k × Vdd by redistribution of the node V2; the second step is that after the gate voltage of the NMOS transistor M1 is turned on briefly along with the switch control signal clkt, Vin is added to the gate voltage of the NMOS transistor M1 on the basis of Vdd through the action of the operational amplifier OP1, the NMOS transistor M2, the capacitor C2 (or a MOS transistor with a short drain-source) and the PMOS transistor M8, so that k × Vdd + Vin is reached, and the on-resistance of the NMOS transistor M1 does not change with the change of the input signal Vin (the specific reason is given by the above formula).

So when clk is 1, the gate voltage V1 of M1 satisfies: v1 ═ k × Vdd + Vin, that is, the voltage of the second control signal is the sum of the on-voltage and the input voltage of the signal input terminal, and the on-voltage is greater than the input voltage of the external power supply, thereby achieving the purpose of the above-mentioned scheme.

Compared with the prior art, the embodiment has the following beneficial effects:

the circuit can not introduce non-ideal harmonic waves, eliminates the interference of input voltage of a signal input end to the sampling field effect transistor, can not generate negative influence on the output signal-to-noise ratio of the analog-to-digital converter, simultaneously reduces the on-resistance of the sampling field effect transistor due to the fact that the on-voltage greater than the input voltage is included, improves the response speed of a switch, ensures that the input signal and the output signal of the sampling holding circuit are in strict linear relation, and improves the performance of the circuit.

It should be understood that although the present description refers to embodiments, not every embodiment contains only a single technical solution, and such description is for clarity only, and those skilled in the art should make the description as a whole, and the technical solutions in the embodiments can also be combined appropriately to form other embodiments understood by those skilled in the art.

The above-listed detailed description is only a specific description of a possible embodiment of the present invention, and they are not intended to limit the scope of the present invention, and equivalent embodiments or modifications made without departing from the technical spirit of the present invention should be included in the scope of the present invention.

Claims

1. The utility model provides a sample-and-hold circuit, includes clock generation sub-circuit, grid voltage bootstrap sub-circuit and sampling field effect transistor, the grid voltage is from lifting the sub-circuit and external power supply respectively, sampling field effect transistor's grid, clock generation sub-circuit and signal input part are connected, clock generation sub-circuit input clock signal, its characterized in that:

the grid voltage bootstrap sub-circuit is configured to alternately output a first control signal and a second control signal to the grid of the sampling field effect transistor according to the clock signal and/or the signal output by the clock generation sub-circuit, the first control signal controls the sample-hold circuit to be in a hold phase, the second control signal controls the sample-hold circuit to be in a tracking phase, the voltage of the second control signal is the sum of a turn-on voltage and the input voltage of the signal input end, and the turn-on voltage is larger than the input voltage of the external power supply.

2. The sample-and-hold circuit of claim 1, wherein the gate voltage bootstrap sub-circuit comprises a charge transfer unit and a node voltage reset unit, an input end of the charge transfer unit is connected to a source electrode of the sampling field-effect transistor and inputs an input voltage of the signal input end, an output end of the charge transfer unit is connected to a gate electrode of the sampling field-effect transistor, and the charge transfer unit comprises a first switch, a bootstrap unit and a second switch which are sequentially arranged along a current direction;

3. The sample-and-hold circuit of claim 2, wherein the clock generation sub-circuit is configured to input a clock signal clk and output a switch control signal clkt, and when the sample-and-hold circuit switches from a hold phase to a tracking phase, the instantaneous level of the output of the switch control signal clkt changes abruptly and returns to the original level again, and the voltage of the node V4 rises from a low level and is greater than the sum of the external power supply and the input voltage of the signal input terminal.

4. The sample-and-hold circuit of claim 3, wherein the charge transfer unit further comprises NMOS transistors M3 and M4 connected between the first switch and the bootstrap unit, gates of the NMOS transistors M3 and M4 are both inputted with the switch control signal clkt, the switch control signal clkt is continuously inputted with a low level, the transient level jump is switched from a low level to a high level, a drain of the NMOS transistor M3 is connected in series with a source of the NMOS transistor M4, a source of the NMOS transistor M3 is short-circuited with a drain of the NMOS transistor M4, and a drain of the NMOS transistor M3 and a source of the NMOS transistor M4 are a node V2.

5. The sample-AND-hold circuit of claim 3, wherein the clock generation sub-circuit comprises a first inverter INV1 AND a second inverter INV2 connected to a clock signal input terminal, respectively, wherein the first inverter INV1 outputs the inverted clock signal clkb, wherein an output terminal of the first inverter INV2 AND the clock signal input terminal are connected to an input terminal of an AND gate, AND wherein an output terminal of the AND gate outputs the switch control signal clkt.

6. The sample-and-hold circuit of claim 4, wherein the first switch is configured as an NMOS transistor M2 with its gate connected to the clock signal clk or the node V1, the second switch is configured as a PMOS transistor M8 with its gate connected to the inverted clock signal clkb or the node V2, and the bootstrap unit is configured as a capacitor or a drain-source-shorted MOS transistor.

7. The sample-and-hold circuit of claim 6, wherein the node voltage reset unit comprises:

8. The sample-and-hold circuit of claim 2, wherein the gate voltage bootstrap sub-circuit further comprises an operational amplifier, a non-inverting input terminal of the operational amplifier is connected to the signal input terminal, an inverting input terminal of the operational amplifier is shorted with an output terminal of the operational amplifier, and the operational amplifier is connected to the first switch.

9. An analog-to-digital converter comprising a sample-and-hold circuit as claimed in any one of claims 1 to 8.

10. A wifi chip characterized in that it includes the sample-and-hold circuit of any of claims 1-8.