CN114172518A

CN114172518A - Sampling hold circuit and analog-to-digital converter

Info

Publication number: CN114172518A
Application number: CN202210131713.6A
Authority: CN
Inventors: 何力; 杨奕
Original assignee: Shandong Zhaotong Microelectronics Co ltd
Current assignee: Shandong Zhaotong Microelectronics Co ltd
Priority date: 2022-02-14
Filing date: 2022-02-14
Publication date: 2022-03-11

Abstract

The invention relates to the field of integrated circuits, and discloses a sample-and-hold circuit and an analog-digital converter.A source voltage of a first NMOS is a voltage of an input signal in a sampling stage, and because a sampling linearization module enables a grid voltage of the first NMOS to be the voltage of the input signal plus a driving voltage, the subtraction of the grid voltage of the first NMOS and the source voltage of the first NMOS is equal to the addition of the voltage of the input signal plus the driving voltage and the subtraction of the voltage of the input signal, finally, the voltage division of the first NMOS is irrelevant to the voltage of the input signal, so that an output signal of the sample-and-hold circuit is in a linear relation with the input signal, and the precision of the integrated circuit is ensured.

Description

Sampling hold circuit and analog-to-digital converter

Technical Field

The present invention relates to the field of integrated circuits, and in particular, to a sample-and-hold circuit and an analog-to-digital converter.

Background

A sample-and-hold circuit is commonly used in the field of integrated circuits, and is used for sampling and holding the voltage of an input signal at a certain period in a time domain, as shown in fig. 1, in a sample-and-hold circuit in the prior art, when a clock signal Clk is at a high level, an NMOS is turned on, an output signal Vout changes along with the input signal Vin, and the stage is a sampling stage; when the clock signal Clk is at a low level, the NMOS is turned off, and the output signal Vout is a value when the falling edge of the clock signal Clk comes, and is continuously held until the rising edge of the clock signal Clk comes, which is a hold stage. In the sampling phase, since the NMOS voltage division is also related to the voltage of the input signal, the voltage of the output signal Vout is not linearly related to the voltage of the input signal Vin, so that the precision of the integrated circuit is affected when the sample-and-hold circuit is applied, for example, the output signal-to-noise ratio of the analog-to-digital converter is affected when the sample-and-hold circuit is applied to a high-precision analog-to-digital converter.

Disclosure of Invention

The invention aims to provide a sample-and-hold circuit and an analog-to-digital converter, which can make the partial voltage of a first NMOS independent of the voltage of an input signal, thereby making the output signal of the sample-and-hold circuit linearly related to the input signal and ensuring the precision of an integrated circuit.

In order to solve the above technical problem, the present invention provides a sample-and-hold circuit, which includes a first NMOS, a first capacitor, a sampling linearization module, a hold module, and a control module;

when the clock signal is at a low level, the control module is used for controlling the holding module to be in a working state so that the sampling holding circuit is in a holding stage;

when the clock signal is at a high level, the control module is used for controlling the sampling linearization module to be in a working state so that the sampling hold circuit is in a sampling stage, and controlling the voltage of the grid electrode of the first NMOS to be the voltage of the input signal plus the driving voltage;

the input end of the control module is used for inputting the clock signal, and the output end of the control module is respectively connected with the control end of the holding module and the control end of the sampling linearization module;

the output end of the holding module is connected with the grid electrode of the first NMOS, the input end of the sampling linearization module is used for inputting an input signal, the first output end of the sampling linearization module is connected with the grid electrode of the first NMOS, and the second output end of the sampling linearization module is connected with the source electrode of the first NMOS;

and the drain electrode of the first NMOS is connected with the first end of the first capacitor, the connected common end is used as the output end of the sample-and-hold circuit, and the second end of the first capacitor is grounded.

Preferably, the sampling linearization module comprises an operational amplifier and a voltage supply module;

the non-inverting input end of the operational amplifier is used as the input end of the sampling linearization module, and the common end of the inverting input end of the operational amplifier, which is connected with the output end of the operational amplifier and is connected with the output end of the operational amplifier, is used as the second output end of the sampling linearization module;

the voltage providing module is used for controlling the voltage of the output end of the voltage providing module to be the voltage of the input signal plus the driving voltage when the sampling linearization module is in a working state;

the control end of the voltage providing module is used as the control end of the sampling linearization module, the input end of the voltage providing module is connected with the output end of the operational amplifier, and the output end of the voltage providing module is used as the first output end of the sampling linearization module.

Preferably, the holding module includes a second NMOS, a gate of the second NMOS is connected to the output end of the first inverter, a source of the second NMOS is grounded, and a drain of the second NMOS serves as the output end of the holding module.

Preferably, the control module comprises a first inverter, a second inverter and an and gate, and the voltage supply module comprises a third NMOS, a fourth NMOS, a fifth NMOS, a sixth NMOS, a first PMOS, a second PMOS, a third PMOS and an energy storage element;

the input end of the first inverter is used for inputting the clock signal, and the output end of the first inverter is connected with the grid electrode of the sixth NMOS;

the input end of the second inverter is used for inputting the clock signal, the output end of the second inverter is connected with the first input end of the AND gate, the second input end of the AND gate is used for inputting the clock signal, and the output end of the AND gate is respectively connected with the grid of the fourth NMOS and the grid of the fifth NMOS;

the drain of the third NMOS is used as the input terminal of the voltage providing module, the drain of the third NMOS is connected to the source of the fourth NMOS and the drain of the fifth NMOS respectively, the drain of the fourth NMOS is connected to the source of the fifth NMOS, the gate of the third PMOS is used for inputting the clock signal, the drain of the fifth NMOS is connected to the first end of the energy storage element, the second end of the energy storage element is connected to the drain of the first PMOS, the common end of the connection between the second end of the energy storage element and the drain of the first PMOS is connected to the source of the second PMOS, the source of the first PMOS is connected to the power supply, the gate of the first PMOS is connected to the gate of the first NMOS, the common end of the connection between the drain of the second PMOS and the gate of the third NMOS is used as the output terminal of the voltage providing module, the source of the sixth NMOS is grounded, and the drain of the sixth NMOS is connected to the first end of the energy storage element, the source electrode of the third PMOS is connected with the power supply, the drain electrode of the third PMOS is connected with the grid electrode of the second PMOS, and the connected public end is connected with the source electrode of the fifth NMOS.

Preferably, the energy storage element is a second capacitor, a first end of the second capacitor is used as a first end of the energy storage element, and a second end of the second capacitor is used as a second end of the energy storage element.

Preferably, the energy storage element is a fourth PMOS, a gate of the fourth PMOS serves as a first end of the energy storage element, and a common end of the source and the drain which are connected and connected serves as a second end of the energy storage element.

In order to solve the above technical problem, the present invention further provides an analog-to-digital converter, including the above sample-and-hold circuit.

The invention provides a sample-and-hold circuit and an analog-to-digital converter, wherein in a sampling stage, the source voltage of a first NMOS is the voltage of an input signal, and since a sampling linearization module enables the grid voltage of the first NMOS to be the voltage of the input signal plus a driving voltage, the subtraction of the grid voltage of the first NMOS from the source voltage of the first NMOS is equal to the voltage of the input signal plus the driving voltage and then the subtraction of the voltage of the input signal, finally, the voltage division of the first NMOS is irrelevant to the voltage of the input signal, so that the output signal of the sample-and-hold circuit is in a linear relation with the input signal, and the precision of an integrated circuit is ensured.

Drawings

In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings needed in the prior art and the embodiments will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art to obtain other drawings without creative efforts.

FIG. 1 is a circuit diagram of a prior art sample and hold circuit;

FIG. 2 is a schematic diagram of a sample-and-hold circuit according to the present invention;

fig. 3 is a circuit diagram of another sample-and-hold circuit provided by the present invention.

Detailed Description

The core of the invention is to provide a sample-and-hold circuit and an analog-to-digital converter, which can make the partial voltage of a first NMOS irrelevant to the voltage of an input signal, thereby making the output signal of the sample-and-hold circuit in linear relation with the input signal and ensuring the precision of an integrated circuit.

In order to make the objects, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are some, but not all, embodiments of the present invention. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.

Referring to fig. 2, fig. 2 is a schematic structural diagram of a sample-and-hold circuit provided in the present invention, the circuit includes a first NMOS1, a first capacitor 2, a sample-and-linearize module 3, a hold module 4, and a control module 5;

when the clock signal is at a low level, the control module 5 is used for controlling the holding module 4 to be in a working state so that the sample-and-hold circuit is in a holding stage;

when the clock signal is at a high level, the control module 5 is configured to control the sampling linearization module 3 to be in a working state so that the sample-and-hold circuit is in a sampling phase, and control the voltage of the gate of the first NMOS1 to be the voltage of the input signal plus the driving voltage;

the input end of the control module 5 is used for inputting a clock signal, and the output end of the control module 5 is respectively connected with the control end of the holding module 4 and the control end of the sampling linearization module 3;

the output end of the holding module 4 is connected with the gate of the first NMOS1, the input end of the sampling linearization module 3 is used for inputting an input signal, the first output end of the sampling linearization module 3 is connected with the gate of the first NMOS1, and the second output end of the sampling linearization module 3 is connected with the source of the first NMOS 1;

the drain of the first NMOS1 is connected to the first terminal of the first capacitor 2, and the common terminal of the first NMOS1 is connected as the output terminal of the sample-and-hold circuit, and the second terminal of the first capacitor 2 is grounded.

Referring to fig. 1, fig. 1 is a circuit diagram of a sample-and-hold circuit in the prior art, where Vin is a voltage of an input signal, Vout is a voltage of an output signal, Clk is a square wave signal, and when the sample-and-hold circuit is in a sampling phase, the voltage of Clk is fixed, and VDD is set, then Vout = Vin a (VDD-Vin-Vth)/(C s + a (VDD-Vin-Vth)), where a is determined by a process and a size of an NMOS transistor, Vth is a threshold voltage of the NMOS transistor, s is a laplacian operator, and C is a capacity of a first capacitor 2. From the above equation, Vout and Vin are not in a linear relationship, and the output signal obtained by using the sample-and-hold circuit in the prior art may have non-ideal harmonics of the input signal, which is not suitable for application in a high-precision digital-to-analog converter.

In order to solve the above technical problem, the sample-and-hold circuit provided by the present invention controls the voltage of the gate of the first NMOS1 to be the voltage of the input signal plus the driving voltage during the sampling phase, specifically, when the clock signal is at a low level, the control module 5 controls the holding module 4 to be in an operating state, and the holding module 4 controls the voltage of the gate of the first NMOS1 to turn off the first NMOS1, so that the sample-and-hold circuit is in the holding phase. When the clock signal is at a high level, the control module 5 controls the sampling linearization module 3 to be in an operating state, and the sampling linearization module 3 controls the voltage of the gate of the first NMOS1 to be the voltage of the input signal plus the driving voltage to turn on the first NMOS1, so that the sample-and-hold circuit is in a sampling phase. When the sampling and holding circuit is in a sampling stage, the output signal of the sampling and holding circuit changes along with the input signal, and the voltage of the output signal and the voltage of the input signal satisfy the following relation: vout = Vin × a (Vq + Vin-Vth)/(C × s + a (Vq + Vin-Vth)) = Vin × a (Vq-Vth)/(C × s + a (Vq-Vth)), and Vq is a driving voltage, and as can be seen from the above equation, Vout and Vin are in a linear relationship. Since Vout and Vin are in a linear relationship during the sampling phase, Vout and Vin are also in a linear relationship during the holding phase.

In summary, in the sample-and-hold circuit provided by the present invention, in the sampling stage, the source voltage of the first NMOS1 is the voltage of the input signal, and since the sampling linearization module 3 makes the gate voltage of the first NMOS1 be the voltage of the input signal plus the driving voltage, the subtraction of the gate voltage of the first NMOS1 and the source voltage of the first NMOS1 is equal to the voltage of the input signal plus the driving voltage and then the subtraction of the voltage of the input signal, it is seen that finally the divided voltage of the first NMOS1 is independent of the voltage of the input signal, so that the output signal of the sample-and-hold circuit is in a linear relationship with the input signal, and the accuracy of the integrated circuit is ensured.

On the basis of the above-described embodiment:

as a preferred embodiment, the sampling linearization module 3 includes an operational amplifier 31 and a voltage supply module 32;

the non-inverting input end of the operational amplifier 31 serves as the input end of the sampling linearization module 3, and the common end of the inverting input end of the operational amplifier 31, which is connected with the output end of the operational amplifier 31 and is connected with the output end of the operational amplifier 31, serves as the second output end of the sampling linearization module 3;

the voltage providing module 32 is configured to control the voltage at the output end of the voltage providing module 32 to be the voltage of the input signal plus the driving voltage when the sampling linearization module 3 is in the working state;

the control terminal of the voltage providing module 32 is used as the control terminal of the sampling linearization module 3, the input terminal of the voltage providing module 32 is connected to the output terminal of the operational amplifier 31, and the output terminal of the voltage providing module 32 is used as the first output terminal of the sampling linearization module 3.

In the present embodiment, the sampling linearization module 3 achieves the purpose of controlling the voltage of the gate of the first NMOS1 to be the voltage of the input signal plus the driving voltage through the operational amplifier 31 and the voltage providing module 32. Specifically, since the voltage at the non-inverting input terminal of the operational amplifier 31 is the voltage of the input signal, and the operational amplifier 31 has the virtual short characteristic, the voltage at the inverting input terminal of the operational amplifier 31 is also the voltage of the input signal, and the output terminal of the operational amplifier 31 is connected to the inverting input terminal of the operational amplifier 31, the voltage at the output terminal of the operational amplifier 31 is also the voltage of the input signal, and when the output terminal of the operational amplifier 31 is connected to the source of the first NMOS1, the voltage at the gate of the first NMOS1 can change in accordance with the voltage of the input signal when the first NMOS1 is turned on.

The input end of the voltage providing module 32 is connected to the output end of the operational amplifier 31, so that the output voltage of the voltage providing module 32 includes the voltage of the input signal, the voltage providing module 32 itself can also output the driving voltage, the output end of the voltage providing module 32 is connected to the gate of the first NMOS1, and when the sampling linearization module 3 is in the working state, the purpose that the voltage of the gate of the first NMOS1 is the voltage of the input signal plus the driving voltage is achieved.

In summary, when the sample-and-hold circuit is in the sampling stage, the voltage of the gate of the first NMOS1 is the voltage of the input signal plus the driving voltage, so that the divided voltage of the first NMOS1 is unrelated to the voltage of the input signal, and thus the output signal of the sample-and-hold circuit is linearly related to the input signal, and the accuracy of the integrated circuit is ensured.

As a preferred embodiment, the holding module 4 includes a second NMOS, a gate of the second NMOS is connected to the output terminal of the first inverter, a source of the second NMOS is grounded, and a drain of the second NMOS serves as the output terminal of the holding module 4.

As shown in fig. 3, fig. 3 is a circuit diagram of another sample-and-hold circuit provided by the present invention.

In this embodiment, when the clock signal is low, the output of the first inverter is high, the second NMOS is turned on, the node V1 falls to 0 under the action of the second NMOS, the first NMOS1 is in an off state, the value of Vout remains unchanged, and the sample-and-hold circuit is in a hold stage.

As a preferred embodiment, the control module 5 includes a first inverter, a second inverter and an and gate, and the voltage providing module 32 includes a third NMOS311, a fourth NMOS312, a fifth NMOS313, a sixth NMOS314, a first PMOS315, a second PMOS316, a third PMOS317 and an energy storage element 318;

the input end of the first inverter is used for inputting a clock signal, and the output end of the first inverter is connected with the grid electrode of the sixth NMOS 314;

the input end of the second inverter is used for inputting a clock signal, the output end of the second inverter is connected with the first input end of the AND gate, the second input end of the AND gate is used for inputting the clock signal, and the output end of the AND gate is respectively connected with the grid of the fourth NMOS312 and the grid of the fifth NMOS 313;

the drain of the third NMOS311 is used as the input terminal of the voltage providing module 32, the drain of the third NMOS311 is connected to the source of the fourth NMOS312 and the drain of the fifth NMOS313, the drain of the fourth NMOS312 is connected to the source of the fifth NMOS313, the gate of the third PMOS317 is used for inputting a clock signal, the drain of the fifth NMOS313 is connected to the first end of the energy storage element 318, the second end of the energy storage element 318 is connected to the drain of the first PMOS315, and the common terminal of the connection between the drain of the energy storage element 318 and the source of the second PMOS316 is connected to the power supply, the gate of the first PMOS315 is connected to the gate of the first NMOS1, the common terminal of the connection between the drain of the second PMOS316 and the gate of the third NMOS311 is used as the output terminal of the voltage providing module 32, the source of the sixth NMOS314 is grounded, the drain of the sixth NMOS314 is connected to the first terminal of the energy storage element 318, the source of the third PMOS317 is connected to the power supply, and the common terminal of the drain of the third PMOS317 is connected to the gate of the second PMOS316 and the source of the fifth NMOS 313.

In this embodiment, when the clock signal is at a low level, the output of the first inverter is at a high level, and at this time, the second NMOS and the sixth NMOS314 are both turned on, and the third PMOS317 is also turned on. The node V1 is lowered to 0 by the second NMOS, the node V3 is lowered to 0 by the sixth NMOS314, the node V2 is changed to the power voltage VDD by the third PMOS317, the first PMOS315 is turned on at this time, the voltage of the node V4 is raised to VDD, the voltage between the node V4 and the node V3 is VDD, the charge Q = VDD × C2 stored in the energy storage element 318, and C2 is the capacity of the energy storage element 318.

When the clock signal changes from low level to high level, the first inverter outputs low level, and the sixth NMOS314, the second NMOS, and the third PMOS317 are all turned off. The second inverter has a delay function, and if the delay time of the second inverter is INV2, the output of the and gate will generate a pulse with a pulse width INV2 and a magnitude VDD when the clock signal changes from low level to high level. The fifth NMOS313 is turned on during the INV2 time. Before the fifth NMOS313 is turned on, the voltage of the node V3 is low because the voltage of the node V2 is high, and when the fifth NMOS313 is turned on, the voltage of the node V2 is lowered and the voltage of the node V3 is raised. The node V4 is ac-coupled to the node V3 via the energy storage element 318, and the voltage at the node V4 is increased by the node V3. The gate of the second PMOS316 is connected to V2, the voltage of the gate of the second PMOS316 decreases, the second PMOS316 is turned on, the voltage of the node V1 increases under the action of the node V4, and the voltage of the node V4 gradually decreases. The gate of the first PMOS315 is connected to the node V1, and the first PMOS315 is disconnected. The fifth NMOS313 continues to maintain the off state after the pulse with the pulse width INV2 and the magnitude VDD has passed, at which time the voltage of the node V1 increases, the voltage of the gate of the third NMOS311 increases, the third NMOS311 turns on, and the voltage of the node V0 is equal to the voltage of the node V3. In addition, the gate of the fourth NMOS312 is also connected to the output of the and gate, and at this time, the fourth NMOS312 is turned off, the node V2 is kept low, and the second PMOS316 is turned on. The output terminal and the inverting input terminal of the operational amplifier 31 are connected to form a unity gain buffer, which aims to make the voltage at the node V0 equal to the voltage of the input signal and make the node V0 have driving capability and not change due to the change of the load of the connected node. At this time, since the voltage at the node V0 is equal to the voltage at the node V3, the node V4 at the first end of the energy storage element 318 is in a high-impedance state, and there is no path for the charges to flow, so the charges stored in the energy storage element 318 remain unchanged, and when the voltage at the node V3 changes, the voltage at the node V4 changes as the voltage at the node V3 changes.

The voltage of the node V4 starts from the time when the clock signal is at a low level, the voltage is VDD, and then rises under the action of the node V3, before the node V4 changes following the node V3, the voltage of the node V4 is assumed to satisfy V4= k VDD (k is greater than 1, and may be generally 1.5), and after the node V4 changes following the node V3, V4= k VDD + V3= k VDD + V0= k VDD + Vin. Since the second PMOS316 is on at this time, the voltage at the node V1 is equal to the voltage at the node V4, so when the clock signal is high, the voltage V1= k × VDD + Vin at the gate of the first NMOS 1. The grid voltage of the first NMOS1 is equal to the voltage of the input signal plus the driving voltage in the sampling stage, and finally the voltage division of the first NMOS1 is unrelated to the voltage of the input signal, so that the output signal of the sample-and-hold circuit is linearly related to the input signal, and the precision of the integrated circuit is guaranteed.

In a preferred embodiment, the energy storage element 318 is a second capacitor, a first terminal of the second capacitor is a first terminal of the energy storage element 318, and a second terminal of the second capacitor is a second terminal of the energy storage element 318.

In this embodiment, the energy storage element 318 is a second capacitor, and the energy storage effect of the capacitor is good, so that the requirement of the sample-and-hold circuit in this application can be met, and the cost is low and saved.

In a preferred embodiment, the energy storage element 318 is a fourth PMOS, a gate of the fourth PMOS serves as a first terminal of the energy storage element 318, and a common terminal having a source and a drain connected and connected serves as a second terminal of the energy storage element 318.

In this embodiment, the energy storage element 318 is a fourth PMOS, and the MOS transistor can also realize the energy storage function, so that the energy storage effect is good, the requirement of the sample-and-hold circuit in this application can be met, and the cost is low and saved.

The invention also provides an analog-to-digital converter which comprises the sampling hold circuit.

For the related description of the analog-to-digital converter provided by the present invention, please refer to the above embodiments, which are not described herein.

It is to be noted that, in the present specification, relational terms such as first and second, and the like are used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Also, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising an … …" does not exclude the presence of other identical elements in a process, method, article, or apparatus that comprises the element.

The previous description of the disclosed embodiments is provided to enable any person skilled in the art to make or use the present invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other embodiments without departing from the spirit or scope of the invention. Thus, the present invention is not intended to be limited to the embodiments shown herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A sampling hold circuit is characterized by comprising a first NMOS, a first capacitor, a sampling linearization module, a hold module and a control module;

the output end of the holding module is connected with the grid electrode of the first NMOS, the input end of the sampling linearization module is used for inputting signals, the first output end of the sampling linearization module is connected with the grid electrode of the first NMOS, and the second output end of the sampling linearization module is connected with the source electrode of the first NMOS;

2. The sample-and-hold circuit of claim 1, wherein the sample linearization module comprises an operational amplifier and a voltage supply module;

3. The sample-and-hold circuit of claim 2, wherein the hold module comprises a second NMOS having a gate connected to the output of the first inverter, a source connected to ground, and a drain as the output of the hold module.

4. The sample-and-hold circuit of claim 3, wherein the control module comprises a first inverter, a second inverter, and an AND gate, and the voltage supply module comprises a third NMOS, a fourth NMOS, a fifth NMOS, a sixth NMOS, a first PMOS, a second PMOS, a third PMOS, and an energy storage element;

5. The sample-and-hold circuit of claim 3, wherein the energy storage element is a second capacitor, a first terminal of the second capacitor being a first terminal of the energy storage element, and a second terminal of the second capacitor being a second terminal of the energy storage element.

6. The sample-and-hold circuit of claim 3, wherein the energy storage element is a fourth PMOS having a gate as the first end of the energy storage element and a common end with a source and a drain connected and connected as the second end of the energy storage element.

7. An analog-to-digital converter comprising a sample-and-hold circuit as claimed in any one of claims 1 to 6.