CN110690820B - A last tube grid source voltage sampling circuit for Buck circuit - Google Patents
A last tube grid source voltage sampling circuit for Buck circuit Download PDFInfo
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- CN110690820B CN110690820B CN201910775954.2A CN201910775954A CN110690820B CN 110690820 B CN110690820 B CN 110690820B CN 201910775954 A CN201910775954 A CN 201910775954A CN 110690820 B CN110690820 B CN 110690820B
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M3/00—Conversion of dc power input into dc power output
- H02M3/02—Conversion of dc power input into dc power output without intermediate conversion into ac
- H02M3/04—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters
- H02M3/10—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
- H02M3/145—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal
- H02M3/155—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only
- H02M3/156—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators
- H02M3/158—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators including plural semiconductor devices as final control devices for a single load
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R19/00—Arrangements for measuring currents or voltages or for indicating presence or sign thereof
- G01R19/25—Arrangements for measuring currents or voltages or for indicating presence or sign thereof using digital measurement techniques
- G01R19/2503—Arrangements for measuring currents or voltages or for indicating presence or sign thereof using digital measurement techniques for measuring voltage only, e.g. digital volt meters (DVM's)
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M1/00—Analogue/digital conversion; Digital/analogue conversion
- H03M1/12—Analogue/digital converters
- H03M1/124—Sampling or signal conditioning arrangements specially adapted for A/D converters
- H03M1/1245—Details of sampling arrangements or methods
Abstract
The invention relates to an upper tube grid source voltage sampling circuit for a Buck circuit, which comprises a sampling unit and a positive feedback unit, wherein the sampling unit comprises an upper tube grid voltage TG port, a SW point voltage SW port, an output control voltage VA port and an output control voltage VB port, the positive feedback unit comprises a first input port, a second input port and an output voltage VOUT port, the output control voltage VA port is connected with the first input port, and the output control voltage VB port is connected with the second input port. When the Buck upper tube is conducted, the output control voltage VB port is at a high potential, the SW point voltage SW port is controlled to be at a low potential, and the output voltage VOUT port is at a low potential, so that the output voltage VOUT port is further pulled down to be at a low potential, and a sampling logic signal of the upper tube grid source voltage is output.
Description
Technical Field
The invention belongs to the technical field of electronic circuits, and particularly relates to an upper tube grid source voltage sampling circuit for a Buck circuit.
Background
Among four basic circuits of the DC-DC switching converter, the Buck converter has the characteristics that the output voltage is less than the input voltage and the direct current is not isolated, and is also called as a Buck converter, so that the Buck converter is widely applied to mobile portable equipment and has a huge application market. In the Buck circuit, no matter dead zone control or internal logic control, a logic signal for taking up actual grid source voltage is needed. However, since the gate voltage of the upper tube is a floating power supply rail, the sampling circuit cannot sample only the gate terminal voltage, otherwise, a large error exists in the sampling, and therefore, an upper tube gate source voltage sampling circuit for the Buck circuit is needed.
Disclosure of Invention
The invention aims to overcome the problems in the prior art and provides an upper grid source voltage sampling circuit for a Buck circuit, which realizes sampling of the upper grid source voltage and ensures sampling precision.
In order to achieve the purpose, the technical scheme adopted by the invention is as follows.
The utility model provides a go up grid source voltage sampling circuit for Buck circuit which characterized in that: including sampling unit and positive feedback unit, the sampling unit includes last gate voltage TG port, SW point voltage SW port, output control voltage VA port and output control voltage VB port, the positive feedback unit includes first input port, second input port and output voltage VOUT port, output control voltage VA port and first input port connection, output control voltage VB port and second input port connection.
The sampling unit further comprises a first NMOS tube, a second NMOS tube, a third NMOS tube, a first PMOS tube and a second PMOS tube.
The positive feedback unit further comprises a fourth NMOS tube, a fifth NMOS tube, a third PMOS tube and a fourth PMOS tube.
The source electrode of the first PMOS tube is connected with an upper tube grid voltage TG port, the grid electrode of the first PMOS tube is connected with a SW point voltage SW port, and the drain electrode of the first PMOS tube is connected with the drain electrode of the first NMOS tube;
the source electrode of the first NMOS tube is connected with the drain electrode of the second NMOS tube, the second PMOS tube is connected with the grid electrode of the third NMOS tube, the second NMOS tube and the third NMOS tube are connected and then connected with the output control voltage VB port, and the control voltage VB port is connected with the grid electrode of the fourth PMOS tube;
the grid electrode of the second NMOS tube is connected with a power supply voltage VDD, and the source electrode of the second NMOS tube is connected with a ground GND;
the source electrode of the second PMOS tube is connected with a power supply voltage VDD, the grid electrode of the third PMOS tube is respectively connected with the drain electrodes of the second PMOS tube and the third NMOS tube, and the source electrode of the third NMOS tube is connected with a ground GND;
the source electrodes of the third PMOS tube and the fourth PMOS tube are connected and connected with a power voltage VDD, the drain electrode of the third PMOS tube is connected with a control voltage VA port, the control voltage VA port is respectively connected with the drain electrode of the fourth NMOS tube and the grid electrode of the fifth NMOS tube, and the fourth NMOS tube is connected with the source electrode of the fifth NMOS tube and then connected with the ground GND;
and the drain electrode of the fourth PMOS tube is respectively connected with the grid electrode of the fourth NMOS tube and the drain electrode of the fifth NMOS tube, and the drain electrode of the fourth PMOS tube, the grid electrode of the fourth NMOS tube and the drain electrode of the fifth NMOS tube are connected and then connected with the output voltage VOUT port.
The invention has the advantages.
1. When the Buck upper tube is conducted, the first PMOS tube is conducted, the output control voltage VB port is at a high potential, the control SW point voltage SW port is at a low potential, the third PMOS tube is started, the drain end of the third PMOS tube is at the high potential, the fifth NMOS tube is started, the output voltage VOUT port is at the low potential, the fourth NMOS tube is turned off, the drain end potential of the third PMOS tube is further pulled high, the fifth NMOS tube is further conducted, the output voltage VOUT port is further pulled low to be at the low potential, and therefore sampling logic signals of upper tube grid source voltage are output.
Drawings
FIG. 1 is a logic diagram of a top-gate source voltage sampling circuit of the present invention.
FIG. 2 is a top gate source voltage sampling circuit diagram of the present invention.
FIG. 3 is a waveform diagram illustrating the operation transition state of the present invention.
The labels in the figure are: n1, a first NMOS transistor, N2, a second NMOS transistor, N3, a third NMOS transistor, N4, a fourth NMOS transistor, N5, a fifth NMOS transistor, P1, a first PMOS transistor, P2, a second PMOS transistor, P3, a third PMOS transistor, P4 and a fourth PMOS transistor.
Detailed Description
The invention is further described below with reference to the accompanying drawings.
Example 1
As shown in fig. 1 to 2, an upper tube gate source voltage sampling circuit for Buck circuit, includes sampling unit and positive feedback unit, the sampling unit includes upper tube gate voltage TG port, SW point voltage SW port, output control voltage VA port and output control voltage VB port, the positive feedback unit includes first input port, second input port and output voltage VOUT port, output control voltage VA port is connected with first input port, output control voltage VB port is connected with second input port.
The sampling unit further comprises a first NMOS transistor N1, a second NMOS transistor N2, a third NMOS transistor N3, a first PMOS transistor P1 and a second PMOS transistor P2.
The positive feedback unit further comprises a fourth NMOS transistor N4, a fifth NMOS transistor N5, a third PMOS transistor P3 and a fourth PMOS transistor P4.
The source electrode of the first PMOS tube P1 is connected with an upper tube gate voltage TG port, the gate electrode is connected with a SW point voltage SW port, and the drain electrode is connected with the drain electrode of a first NMOS tube N1, and the gate electrode of the first NMOS tube N1 is connected with a power supply voltage VDD;
the source electrode of the first NMOS tube N1 is connected with the drain electrode of a second NMOS tube N2, the second PMOS tube P2 is connected with the gate electrode of a third NMOS tube N3, the second PMOS tube P2 and the third NMOS tube N3 are connected and then connected with an output control voltage VB port, and the control voltage VB port is connected with the gate electrode of a fourth PMOS tube P4;
the grid electrode of the second NMOS tube N2 is connected with a power supply voltage VDD, and the source electrode of the second NMOS tube N2 is connected with a ground GND;
the source electrode of the second PMOS tube P2 is connected with a power supply voltage VDD, the grid electrode of the third PMOS tube P3 is respectively connected with the drain electrodes of the second PMOS tube P2 and the third NMOS tube N3, and the source electrode of the third NMOS tube N3 is connected with the ground GND;
the source electrodes of the third PMOS tube P3 and the fourth PMOS tube P4 are connected with a power supply voltage VDD, the drain electrode of the third PMOS tube P3 is connected with a control voltage VA port, the control voltage VA port is respectively connected with the drain electrode of the fourth NMOS tube N4 and the grid electrode of the fifth NMOS tube N5, and the fourth NMOS tube N4 is connected with the source electrode of the fifth NMOS tube N5 and then is connected with the ground GND;
the drain of the fourth PMOS transistor P4 is connected to the gate of the fourth NMOS transistor N4 and the drain of the fifth NMOS transistor N5, respectively, and the three are connected to the output voltage VOUT port.
When the Buck upper tube is conducted, the first PMOS tube is conducted P1, the output control voltage VB port is high potential, the control SW point voltage SW port is low potential, the third PMOS tube P3 is started, the drain electrode of the third PMOS tube P3 is high potential, the fifth NMOS tube N5 is started, the output voltage VOUT port is low potential, the fourth NMOS tube N4 is turned off, the drain electrode potential of the third PMOS tube P3 is further pulled high, the fifth NMOS tube N5 is further conducted, the output voltage VOUT port is further pulled low to be low potential, and therefore sampling logic signals of the upper tube gate source voltage are output.
As shown in fig. 3, when the Buck transistor is turned on, the first PMOS transistor P1 is turned on, the output control voltage VB port is high, the output control voltage VA port is low, the third PMOS transistor P3 is turned on, the drain of the third PMOS transistor P3 is high, the fifth NMOS transistor N5 is turned on, the output voltage VOUT port is low, the fourth NMOS transistor N4 is turned off, the drain of the third PMOS transistor P3 is further pulled high, the fifth NMOS transistor N5 is further turned on, the output voltage VOUT port is further pulled low, the sampled logic signal of the upper gate source voltage is low, when the Buck transistor is turned off, the first PMOS transistor P1 is turned off, the output control voltage VB port is low, the output control voltage VA port is high, the third PMOS transistor P3 is turned off, the third PMOS transistor P3 is low, the drain of the fifth NMOS transistor N5 is turned off, the output voltage VOUT port is high, the fourth NMOS transistor N4 is turned on, the drain potential of the third PMOS transistor P3 is further pulled low, so that the fifth NMOS transistor N5 is further turned off, and the output voltage VOUT port is further pulled high to a high potential, so that the sampled logic signal of the gate-source voltage is output as a high potential, thereby realizing accurate sampling of the gate-source voltage on the Buck circuit and outputting the logic signal VOUT.
The traditional upper tube grid voltage sampling circuit only adopts the upper tube grid end voltage, and the actual sampling of the on and off states of the tube is to sample the grid source voltage, so the sampling precision problem exists.
The invention samples the upper tube grid source voltage of the Buck circuit on the floating power supply rail to generate internal control voltages VA and VB, and the control voltages VA and VB output the voltage VOUT through the positive feedback unit.
The above-mentioned embodiments only express the specific embodiments of the present application, and the description thereof is more specific and detailed, but not construed as limiting the scope of the present application. It should be noted that, for those skilled in the art, without departing from the technical idea of the present application, several changes and modifications can be made, which are all within the protection scope of the present application.
Claims (3)
1. The utility model provides a go up grid source voltage sampling circuit for Buck circuit which characterized in that: the device comprises a sampling unit and a positive feedback unit;
the sampling unit comprises an upper tube grid voltage TG port, a SW point voltage SW port, an output control voltage VA port and an output control voltage VB port, and further comprises a first NMOS tube (N1), a second NMOS tube (N2), a third NMOS tube (N3), a first PMOS tube (P1) and a second PMOS tube (P2);
the source electrode of the first PMOS tube (P1) is connected with an upper tube grid voltage TG port, the grid electrode is connected with an SW point voltage SW port, and the drain electrode is connected with the drain electrode of the first NMOS tube (N1);
the grid electrode of the first NMOS tube (N1) is connected with a power supply voltage VDD, and the source electrode of the first NMOS tube (N1) is connected with the drain electrode of the second NMOS tube (N2);
the grid electrode of the second NMOS tube (N2) is connected with a power supply voltage VDD, and the source electrode of the second NMOS tube is connected with a ground GND;
the source electrode of the third NMOS tube (N3) is connected with the ground GND;
the second PMOS tube (P2) is connected with the grid electrode of the third NMOS tube (N3), and the second PMOS tube (P2) and the third NMOS tube are connected with the output control voltage VB port after being connected; the source electrode of the second PMOS pipe (P2) is connected with the power supply voltage VDD;
the positive feedback unit comprises a first input port, a second input port and an output voltage VOUT port, the output control voltage VA port is connected with the first input port, and the output control voltage VB port is connected with the second input port.
2. A top-gate source voltage sampling circuit for a Buck circuit as recited in claim 1, wherein: the positive feedback unit further comprises a fourth NMOS transistor (N4), a fifth NMOS transistor (N5), a third PMOS transistor (P3) and a fourth PMOS transistor (P4).
3. A top gate source voltage sampling circuit for a Buck circuit as recited in claim 2, wherein:
the grid electrode of the third PMOS tube (P3) is respectively connected with the drain electrodes of the second PMOS tube (P2) and the third NMOS tube (N3); the sources of the third PMOS tube (P3) and the fourth PMOS tube (P4) are connected and connected with a power supply voltage VDD; the drain electrode of the third PMOS tube (P3) is connected with a control voltage VA port; the control voltage VA port is respectively connected with the drain electrode of the fourth NMOS tube (N4) and the gate electrode of the fifth NMOS tube (N5); the fourth NMOS tube (N4) is connected with the source electrode of the fifth NMOS tube (N5) and then is connected with the ground GND;
the drain electrode of the fourth PMOS tube (P4) is respectively connected with the grid electrode of the fourth NMOS tube (N4) and the drain electrode of the fifth NMOS tube (N5), and the drain electrodes are connected and then connected with the output voltage VOUT port; and the control voltage VB port is connected with the grid electrode of the fourth PMOS tube (P4).
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201910775954.2A CN110690820B (en) | 2019-08-22 | 2019-08-22 | A last tube grid source voltage sampling circuit for Buck circuit |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201910775954.2A CN110690820B (en) | 2019-08-22 | 2019-08-22 | A last tube grid source voltage sampling circuit for Buck circuit |
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| Publication Number | Publication Date |
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| CN110690820A CN110690820A (en) | 2020-01-14 |
| CN110690820B true CN110690820B (en) | 2021-06-08 |
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| CN201910775954.2A Active CN110690820B (en) | 2019-08-22 | 2019-08-22 | A last tube grid source voltage sampling circuit for Buck circuit |
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| CN111257628B (en) * | 2020-03-05 | 2022-05-06 | 成都飞机工业（集团）有限责任公司 | Anti-interference method for converting alternating current signal into pulse signal |
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| JP4727232B2 (en) * | 2003-06-06 | 2011-07-20 | 株式会社半導体エネルギー研究所 | Semiconductor device |
| CN104536507A (en) * | 2014-12-05 | 2015-04-22 | 芯原微电子(上海)有限公司 | Fold back type current limiting circuit and linear constant voltage source with fold back type current limiting circuit |
| CN104967096A (en) * | 2015-07-29 | 2015-10-07 | 电子科技大学 | Over-temperature protection circuit used for high-side power switch |
| CN105958983A (en) * | 2016-04-25 | 2016-09-21 | 华中科技大学 | Voltage comparator suitable for blood oxygen saturation detection |
| CN107944099A (en) * | 2017-11-10 | 2018-04-20 | 东南大学 | A kind of high-speed, high precision comparator circuit design |
| CN109951178A (en) * | 2019-04-03 | 2019-06-28 | 电子科技大学 | A kind of system protection method of GaN gate drive circuit |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US9667194B2 (en) * | 2015-02-24 | 2017-05-30 | Omni Design Technologies Inc. | Differential switched capacitor circuits having voltage amplifiers, and associated methods |
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Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP4727232B2 (en) * | 2003-06-06 | 2011-07-20 | 株式会社半導体エネルギー研究所 | Semiconductor device |
| CN104536507A (en) * | 2014-12-05 | 2015-04-22 | 芯原微电子(上海)有限公司 | Fold back type current limiting circuit and linear constant voltage source with fold back type current limiting circuit |
| CN104967096A (en) * | 2015-07-29 | 2015-10-07 | 电子科技大学 | Over-temperature protection circuit used for high-side power switch |
| CN105958983A (en) * | 2016-04-25 | 2016-09-21 | 华中科技大学 | Voltage comparator suitable for blood oxygen saturation detection |
| CN107944099A (en) * | 2017-11-10 | 2018-04-20 | 东南大学 | A kind of high-speed, high precision comparator circuit design |
| CN109951178A (en) * | 2019-04-03 | 2019-06-28 | 电子科技大学 | A kind of system protection method of GaN gate drive circuit |
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