CN107370487B - Grid voltage bootstrap switch circuit based on NMOS pipe - Google Patents

Grid voltage bootstrap switch circuit based on NMOS pipe Download PDF

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CN107370487B
CN107370487B CN201710586131.6A CN201710586131A CN107370487B CN 107370487 B CN107370487 B CN 107370487B CN 201710586131 A CN201710586131 A CN 201710586131A CN 107370487 B CN107370487 B CN 107370487B
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nmos
switch
nmos transistor
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substrate
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CN107370487A (en
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徐代果
徐世六
陈光炳
刘涛
刘璐
石寒夫
邓民明
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CETC 24 Research Institute
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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M1/00—Analogue/digital conversion; Digital/analogue conversion
    • H03M1/12—Analogue/digital converters
    • H03M1/124—Sampling or signal conditioning arrangements specially adapted for A/D converters
    • H03M1/1245—Details of sampling arrangements or methods

Abstract

The invention provides a gate voltage bootstrap switch circuit based on an NMOS (N-channel metal oxide semiconductor) tube, which comprises an NMOS tube MN1 for sampling, a voltage bootstrap circuit BOOST, a sampling switch substrate coupling capacitor C1 and a sampling switch MN1 substrate discharge switch MN8, wherein a coupling capacitor C1 is added between the gate and the substrate of the sampling NMOS tube NM1, a discharge switch MN8 is added between the substrate of the sampling switch and the ground, when an input signal VIN changes, if a sampling and holding circuit is in a sampling state, the discharge switch NM8 is disconnected, through the bootstrap effect generated by a bootstrap circuit module BOOST, when the input signal VIN changes, if the sampling and holding circuit is in a holding state, the discharge switch NM8 is connected, the substrate voltage of the sampling switch NM1 is pulled down to the ground, and simultaneously, the gate voltage of the sampling switch NM1 is pulled down to the ground, so that the sampling switch NM1 is disconnected. Compared with the traditional structure, the sample-hold switch and the auxiliary circuit thereof provided by the invention have the advantage that the linearity is obviously improved.

Description

Grid voltage bootstrap switch circuit based on NMOS pipe
Technical Field
The invention belongs to the technical field of analog or digital-analog hybrid integrated circuits, and particularly relates to a high-linearity sample-and-hold switch and an auxiliary circuit thereof.
Background
In recent years, with the further improvement of performance indexes of analog-to-digital converters, especially with the continuous development of integrated circuit process technologies, research on high-precision analog-to-digital converters is more and more intensive, and the high-precision analog-to-digital converters put higher demands on sampling switches. In a traditional grid voltage bootstrap sampling switch structure, an NMOS tube is generally adopted as a sampling switch, through a grid voltage bootstrap technology, the difference of grid source voltages of the sampling NMOS tube can be kept as VDD theoretically, and the technology can enable the sampling switch to keep higher linearity. However, the conventional structure has a certain problem, when the sampling NMOS transistor is in a conducting state, the gate voltage of the sampling NMOS transistor is the input signal VIN + VDD, and if the input signal amplitude is small, the absolute value of the gate voltage of the sampling NMOS transistor is relatively small, so that a serious problem does not occur; when the amplitude of an input signal is large, the absolute value of the grid voltage of the sampling NMOS tube is correspondingly increased, the reliability of the device is caused by the excessively high grid voltage, and meanwhile, the undesirably leakage current is also possibly caused by the excessively high grid voltage, so that the grid voltage of the sampling NMOS tube is clamped to a fixed value, and the linearity of the sampling NMOS tube is seriously influenced. The traditional structure is difficult to meet the requirement of a high-linearity sampling switch under the condition of high-speed large-amplitude input signal application.
In order to describe the above problems in more detail, the working principle and advantages and disadvantages of the conventional gate voltage bootstrap sampling switch are analyzed. Structure [1]As shown in fig. 1, when an input signal VIN changes, a gate voltage bootstrap circuit module generates a bootstrap voltage, so that input and output voltages of the bootstrap voltage are kept at a constant value, and a constant gate-source voltage difference is obtained by a sampling NMOS transistor MN1, thereby improving linearity of a sampling NMOS transistor MN 1. A cross-sectional view of a conventional gate voltage bootstrapped sampling switch is shown in fig. 2, and it can be seen from fig. 2 that the substrate of the sampling NMOS transistor MN1 is directly grounded. The schematic diagram of the conventional sampling switch and its auxiliary circuit is shown in fig. 3, in which the source of MN1 is grounded, the gate is connected to the control signal CKN, the drain is connected to the source of MN2, and the drain is connected to the capacitor CPThe lower plate of MN3, the source of MN 4; MN2 and MP1 constitute an inverter structure, the input of which is connected with the control signal CK, the output of which is connected with the drain of MN3 and the grid of MP 3; the source of MP2 is connected with power VDD, the drain is connected with the upper plate of capacitor CN, the source of MP2 is connected with the source of MP3, the grid is connected with the drain of MP3, and the grid is connected with the drain of MN6, MN3, MN4 and MN 1; the gate of MN6 is connected with power vdd, and the source is connected with the drain of MN 7; the gate of MN7 is connected to control signal CKN, the source is connected to ground, the above devices and connection relationship constitute bootstrap voltage generating circuit BOOST, the output of which controls the gate C point of sampling switch MN1, the drain of MN5 is used as the output end of sampling signal, and is connected to sampling capacitor Cc. The operation principle is briefly described below, the signal CK and its inverse signal CKN are used as control signals, when CK is low level and CKN is high level, MN5/MN6/MN7/MP1/MP2 is turned on, MN1/MN2/MN3/MN4/MP3 is turned off, therefore, the voltage at point A is highThe voltage levels at the points B and C are low, and it should be noted that, at this time, the capacitor C isPThe voltage difference between the two ends is the voltage difference between the power voltage vdd and the ground; when the CK is high level and the CKN is low level, the working state of the MOS device is as follows, MN5/MN6/MN7/MP1/MP2 are disconnected, MN1/MN2/MN3/MN4/MP3 are connected, and at the moment, the capacitor C is connected by the connection of MN4 and MP3PThe upper and lower electrode plates of the sampling switch MN1 are directly connected to the gate and the source of the sampling switch MN1, if the charge sharing effect of the parasitic capacitance is neglected, theoretically, the voltage at the C point of the MN1 gate is VIN + vdd, then, when MN1 is turned on, the difference between the gate and source voltages thereof is maintained at vdd, and the on-resistance thereof can be expressed as:
Figure GDA0002415388320000021
according to the equation (1), due to the existence of the gate voltage bootstrap circuit of the NMOS transistor MN1, the on-resistance of the NMOS sampling switch does not change with the change of the input signal VIN, and is a fixed value, so that the sampling switch MN1 can provide better linearity. However, as can also be seen from the formula (1), there is a V in the denominatorthnIt represents the threshold voltage of the NMOS transistor sampling switch MN1, and as known from the knowledge of semiconductor devices, this threshold voltage can be expressed as:
Figure GDA0002415388320000022
wherein, -VmsFlat band voltage of metal-semiconductor contact, COXRepresenting the gate capacitance, Q, of the NMOS transistorOXRepresents the positive charge amount of the gate, NADenotes the substrate doping concentration, niDenotes the carrier concentration in thermal equilibrium, QBmaxRepresenting the space charge region charge concentration, with the remaining parameters being constant. The space charge region charge concentration can be expressed as:
Figure GDA0002415388320000023
wherein, VS+ V (y) represents the surface potential at that time, VBSRepresenting the voltage difference between the substrate and the source. As shown in the formula (3), when the NMOS transistor substrate is grounded, if other parameters are not changed, the space charge concentration Q is increasedBmaxIs kept unchanged, so that the threshold voltage V of the NMOS tubethnRemain unchanged. Therefore, according to the equation (1), the conventional sampling switch and its auxiliary circuit can provide a source of better linearity, and only the sampling switch can provide a stable gate-source voltage difference. Since the substrate of the NMOS transistor MN1 of the sampling switch is always grounded, the threshold voltage is large, and as can be seen from equation (1), the on-resistance of the conventional sampling switch and its auxiliary circuit is still limited, and it is difficult to meet the requirement of high linearity under the condition of high operating frequency or high input signal frequency.
Disclosure of Invention
Technical problem
The traditional sampling switch and the auxiliary circuit thereof are difficult to meet the requirement of high linearity under the condition of higher working frequency or higher input signal frequency.
Technical idea
Based on the above analysis, the present invention provides a high linearity sample-and-hold switch and its auxiliary circuit. If a substrate bias voltage V which changes along with the change of the amplitude of an input signal is added on the substrate of the sampling switch NMOS tube MN1BSThen, as can be seen from the formula (3), the space charge concentration QBmaxWill increase, thereby sampling the threshold voltage V of the NMOS transistor MN1 of the switchthnAnd will be reduced accordingly. As can be seen from equation (1), the on-resistance of the sampling NMOS switch MN1 decreases, which means that the larger the amplitude of the input signal is, the larger the threshold voltage V isthnThe more significant the reduction in on-resistance and thus the more significant the reduction in on-resistance. Compared with the traditional structure, the invention further improves the linearity of the sampling switch.
Technical scheme
A grid voltage bootstrap switch circuit based on an NMOS (N-channel metal oxide semiconductor) tube comprises an NMOS tube and a bootstrap circuit unit, wherein the grid electrode of the NMOS tube is connected with the output end of the bootstrap circuit unit, the source electrode of the NMOS tube and the input end of the bootstrap circuit unit are respectively connected with a node where an input signal VIN of the grid voltage bootstrap switch circuit is located, and the drain electrode of the NMOS tube is connected with a node where an output signal VOUT of the grid voltage bootstrap switch circuit is located; the gate voltage bootstrapped switch circuit further comprises: the upper pole plate of the substrate coupling capacitor is connected with the grid electrode of the NMOS tube, and the lower pole plate of the substrate coupling capacitor is connected with the substrate of the NMOS tube; one end of the discharge switch is connected with the lower polar plate of the substrate coupling capacitor, and the other end of the discharge switch is grounded; when the input signal VIN changes, if the sampling holding circuit is in a sampling state, the discharging switch is switched off; when the input signal VIN changes, the discharge switch is turned on if the sample-and-hold circuit is in the hold state.
Technical effects
1. In the invention, by introducing a sampling tube gate voltage bootstrap technology, when the sample hold circuit is in a sampling state, the discharge switch NM8 is turned off, and by the bootstrap effect generated by the bootstrap circuit module BOOST, the gate voltage of the sampling switch NM1 is increased, so that the gate-source voltage difference of the sampling switch NM1 is increased, the gate-source voltage difference is changed along with the amplitude change of the input signal, and the linearity of the sampling switch NM1 is improved.
2. In the invention, by introducing a sampling tube substrate voltage bootstrap technology, a bootstrap effect generated by a bootstrap circuit module BOOST is coupled to the substrate of the sampling switch NM1 through a coupling capacitor C1, so that the substrate voltage of the sampling switch NM1 is increased, the threshold voltage of the sampling switch NM1 is reduced due to the increase of the substrate voltage of the sampling switch NM1, the on-resistance of the sampling switch NM1 is reduced, and meanwhile, the substrate voltage of the sampling switch NM1 is changed along with the change of an input signal, so that the linearity of the sampling switch is further increased.
3. The maximum value of the substrate voltage of the switch MN8 in the sampling state is controlled by adjusting the capacitance value of the substrate coupling capacitor C1, and the forward conduction of a parasitic diode between the substrate and the source electrode of the sampling switch is prevented, so that the sampling switch keeps a better linearity.
4. Compared with the traditional structure, the sampling tube substrate voltage coupling circuit is introduced, namely a coupling capacitor and an NMOS switch tube are introduced, the circuit complexity is not obviously increased, but the linearity of the sampling hold circuit is greatly improved.
Drawings
FIG. 1 is a schematic diagram of a conventional gate voltage bootstrapped sampling switch;
FIG. 2 is a cross-sectional view of a conventional gate voltage bootstrapped sampling switch;
FIG. 3 is a schematic diagram of a conventional sampling switch and its auxiliary circuit;
FIG. 4 is a schematic diagram of a gate voltage bootstrapped sampling switch according to the present invention;
FIG. 5 is a cross-sectional view of a gate voltage bootstrapped sampling switch according to the present invention;
fig. 6 is a schematic structural diagram of a sampling switch and an auxiliary circuit thereof according to the present invention;
FIG. 7 is a timing diagram of the variation of the substrate voltage of the sampling NMOS transistor with the input signal according to the present invention;
FIG. 8 is a graph comparing the Spurious Free Dynamic Range (SFDR) with the frequency of the input signal for two configurations;
FIG. 9 is a graph comparing the Spurious Free Dynamic Range (SFDR) with the sampling frequency for two configurations.
Detailed Description
The following description of the embodiments of the present invention is provided for illustrative purposes, and other advantages and effects of the present invention will become apparent to those skilled in the art from the present disclosure.
The schematic diagram of the gate voltage bootstrap sampling switch provided by the invention is shown in fig. 4, and comprises an NMOS transistor MN1 for sampling, a voltage bootstrap circuit BOOST, a sampling switch substrate coupling capacitor C1, and a sampling switch MN1 substrate discharge switch MN 8. The invention adds a coupling capacitor C1 between the grid of the sampling NMOS transistor NM1 and the substrate, and adds a discharge switch MN8 between the substrate of the sampling switch and the ground. When the input signal VIN changes, if the sample-and-hold circuit is in the sampling state, the discharge switch NM8 is turned off, and through the bootstrap effect generated by the bootstrap circuit module BOOST, on one hand, the gate voltage of the sampling switch NM1 is increased, so that the gate-source voltage difference of the sampling switch NM1 is increased, the gate-source voltage difference changes along with the amplitude change of the input signal, and the linearity of the sampling switch NM1 is improved; on the other hand, the bootstrap effect generated by the bootstrap circuit module BOOST is coupled to the substrate of the sampling switch NM1 through the coupling capacitor C1, so that the substrate voltage of the sampling switch NM1 is increased, and due to the increase of the substrate voltage of the sampling switch NM1, the threshold voltage is reduced, so that the on-resistance of the sampling switch NM1 is reduced, and meanwhile, the substrate voltage of the sampling switch NM1 changes along with the change of the input signal, so that the linearity of the sampling switch is further increased. When the input signal VIN varies, if the sample-and-hold circuit is in the hold state, the discharge switch NM8 is turned on, the substrate voltage of the sampling switch NM1 is pulled down to the ground, and at the same time, the gate voltage of the sampling switch NM1 is also pulled down to the ground, so that the sampling switch NM1 is turned off. Compared with the traditional structure, the sample-hold switch and the auxiliary circuit thereof provided by the invention have the advantage that the linearity is obviously improved. Fig. 5 shows a cross-sectional view of a gate voltage bootstrapped sampling switch proposed by the present invention, and it can be seen from fig. 5 that the substrate potential of the sampling NMOS switch MN1 is led out through the P + diffusion region, and is connected to the bottom plate of the substrate potential coupling capacitor C1 and the drain of the sampling switch MN1 substrate discharge switch MN 8.
The schematic diagram of the sampling switch and its auxiliary circuit structure is shown in fig. 6. the sampling switch MN1 gate voltage bootstrap BOOST module comprises NMOS transistors MN2 to MN7, PMOS transistors PM1 to PM3 and a capacitor CPAnd forming a gate voltage bootstrap structure BOOST aiming at the sampling NMOS pipe MN 1. The source of MN5 is grounded, the gate is connected to control signal CKN, the drain is connected to the source of MN2, and simultaneously connected to the lower plate of capacitor CN, the source of MN3 and the drain of MN 4; MN2 and MP1 form an inverter structure, the input of the inverter structure is connected with a control signal CK, the output of the inverter structure is connected with the drain electrode of MN3, and the output of the inverter structure is simultaneously connected with the gate electrode of MP 3; the source of MP2 is connected to power vdd, and the drain of MP2 is connected to capacitor CPThe upper polar plate is connected with the source electrode of MP3, the grid electrode of MP2 is connected with the drain electrode of MP3 and is connected with the drain electrode of MN6, the grid electrodes of MN3, MN4 and MN 1; the gate of MN6 is connected with power vdd, and the source is connected with the drain of MN 7; the gate of MN7 is connected to control signal CKN, and its source is connected to ground. A substrate voltage bootstrap structure of a sampling switch MN1 comprises a substrate coupling capacitor C1 and an NMOS transistor MN8 serving as a discharge switch, wherein an upper polar plate of the C1 is connected with a grid electrode of the NMOS transistor MN1, and a lower polar plate of the C1 is connected with a sampling switchThe substrate of the switch MN1 is connected, the lower plate of the C1 is connected with the drain of the NMOS transistor MN8, the grid of the NMOS transistor MN8 is connected with the control signal CKN, and the source is grounded. When the input signal VIN changes, if the sample-and-hold circuit is in the sampling state, the discharge switch NM8 is turned off, and through the bootstrap effect generated by the bootstrap circuit module BOOST, on one hand, the gate voltage of the sampling switch NM1 is increased, so that the gate-source voltage difference of the sampling switch NM1 is increased, the gate-source voltage difference changes along with the amplitude change of the input signal, and the linearity of the sampling switch NM1 is improved; on the other hand, the bootstrap effect generated by the bootstrap circuit module BOOST is coupled to the substrate of the sampling switch NM1 through the coupling capacitor C1, so that the substrate voltage of the sampling switch NM1 is increased, and due to the increase of the substrate voltage of the sampling switch NM1, the threshold voltage is reduced, so that the on-resistance of the sampling switch NM1 is reduced, and meanwhile, the substrate voltage of the sampling switch NM1 changes along with the change of the input signal, so that the linearity of the sampling switch is further increased. When the input signal VIN varies, if the sample-and-hold circuit is in the hold state, the discharge switch NM8 is turned on, the substrate voltage of the sampling switch NM1 is pulled down to the ground, and at the same time, the gate voltage of the sampling switch NM1 is also pulled down to the ground, so that the sampling switch NM1 is turned off. Compared with the traditional structure, the sample-hold switch and the auxiliary circuit thereof provided by the invention have the advantage that the linearity is obviously improved. Fig. 7 shows a timing diagram of the variation of the substrate voltage of the sampling NMOS transistor with the input signal, and it can be seen from fig. 7 that the substrate D point voltage of the sampling NMOS transistor MN1 shown in fig. 6 varies with the amplitude variation of the input signal VIN, thereby achieving the purpose of substrate voltage bootstrapping.
It should be noted that the maximum value of the substrate voltage of the switch MN8 in the sampling state can be controlled by adjusting the capacitance value of the substrate coupling capacitor C1, so as to prevent the parasitic diode between the substrate and the source of the sampling switch from being turned on in the forward direction, and thus the sampling switch maintains a good linearity.
To further verify the above advantages of the present invention, the error correction comparator was carefully designed under 65nm cmos process. The sampling clock frequency is 100MHz, the power supply voltage is 1.2V, the common mode voltage is 0.6V, and the simulation result that the Spurious Free Dynamic Range (SFDR) of the sampling switch changes with the frequency change of the input signal is shown in fig. 8, and it can be known from fig. 8 that the SFDR is improved by at least 13.3% compared with the conventional structure. The input frequency is 10MHz, the power voltage is 1.2V, the common mode voltage is 0.6V, and the simulation result of the change of the non-stray dynamic range (SFDR) of the sampling switch along with the change of the sampling frequency is shown in fig. 9, and it can be known from fig. 9 that the SFDR is improved by at least 15% compared with the conventional structure. As can be seen from fig. 8 and 9, compared with the conventional structure, the effect of the present invention on improving linearity is more significant at high frequencies.
The foregoing embodiments are merely illustrative of the principles and utilities of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or change the above-mentioned embodiments without departing from the spirit and scope of the present invention. Accordingly, it is intended that all equivalent modifications or changes which can be made by those skilled in the art without departing from the spirit and technical spirit of the present invention be covered by the claims of the present invention.

Claims (5)

1. A grid voltage bootstrap switch circuit based on an NMOS (N-channel metal oxide semiconductor) tube comprises an NMOS tube MN1 and a bootstrap circuit unit, wherein the grid electrode of the NMOS tube MN1 is connected with the output end of the bootstrap circuit unit, the source electrode of the NMOS tube MN1 and the input end of the bootstrap circuit unit are respectively connected with a node where an input signal VIN of the grid voltage bootstrap switch circuit is located, and the drain electrode of the NMOS tube MN1 is connected with a node where an output signal VOUT of the grid voltage bootstrap switch circuit is located;
characterized in that, the grid voltage bootstrap switch circuit still includes:
a substrate coupling capacitor C1, an upper electrode plate of the substrate coupling capacitor C1 is connected with a gate of the NMOS transistor MN1, and a lower electrode plate of the substrate coupling capacitor C1 is connected with a substrate of the NMOS transistor MN 1;
one end of the discharge switch is connected with the lower pole plate of the substrate coupling capacitor C1, and the other end of the discharge switch is grounded;
when the input signal VIN changes, if the sampling holding circuit is in a sampling state, the discharging switch is switched off; when the input signal VIN changes, the discharge switch is turned on if the sample-and-hold circuit is in the hold state.
2. The gate voltage bootstrapped switch circuit based on the NMOS transistor of claim 1, wherein: the discharge switch is an electronic switch realized by an NMOS tube.
3. The gate voltage bootstrapped switch circuit based on the NMOS transistor of claim 2, wherein: the electronic switch realized by the NMOS tube comprises an NMOS tube MN8, an upper polar plate of a substrate coupling capacitor C1 is connected with a grid electrode of an NMOS tube MN1, a lower polar plate of the substrate coupling capacitor C1 is connected with a substrate of the NMOS tube MN1, a lower polar plate of the substrate coupling capacitor C1 is simultaneously connected with a drain electrode of the NMOS tube MN8, a grid electrode of the NMOS tube MN8 is connected with an external control signal CKN, and a source electrode of the NMOS tube MN8 is grounded.
4. The gate voltage bootstrapped switch circuit based on the NMOS transistor of any one of claims 1 to 3, wherein: the bootstrap circuit unit includes:
an NMOS transistor MN 2;
an NMOS transistor MN 3;
an NMOS transistor MN 4;
an NMOS transistor MN 5;
an NMOS transistor MN 6;
an NMOS transistor MN 7;
PMOS transistor MP 1;
PMOS transistor MP 2;
PMOS transistor MP 3;
capacitor CPComposition is carried out;
the source of the NMOS transistor MN5 is grounded, the gate of the NMOS transistor MN5 is connected to the external control signal CKN, the drain of the NMOS transistor MN5 is connected to the source of the NMOS transistor MN2 and to the capacitor CPThe lower polar plate of the NMOS tube MN3, the source electrode of the NMOS tube MN4 and the drain electrode of the NMOS tube MN 4;
the NMOS transistor MN2 and the PMOS transistor MP1 form an inverter structure, the input of the inverter structure is connected with an external control signal CK, the output of the inverter structure is connected with the drain electrode of the NMOS transistor MN3, and the output of the inverter structure is simultaneously connected with the grid electrode of the PMOS transistor MP 3;
the source electrode of the PMOS tube MP2 is connected with the power vdd, and the drain electrode of the PMOS tube MP2 is connected with the capacitor CPThe upper polar plate of the NMOS transistor MP2 is connected with the source electrode of a PMOS transistor MP3, the grid electrode of the PMOS transistor MP2 is connected with the drain electrode of a PMOS transistor MP3, and is connected with the drain electrode of an NMOS transistor MN6, the grid electrode of an NMOS transistor MN3, an NMOS transistor MN4 and a grid electrode of an NMOS transistor MN 1;
the grid electrode of the NMOS tube MN6 is connected with the power vdd, and the source electrode of the NMOS tube MN6 is connected with the drain electrode of the NMOS tube MN 7; the gate of the NMOS transistor MN7 is connected to the external control signal CKN, and the source thereof is grounded.
5. An analog-to-digital converter, characterized by: the gate voltage bootstrap switch circuit based on the NMOS transistor as claimed in any one of claims 1-4.
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CN108199703A (en) * 2017-12-29 2018-06-22 上海艾为电子技术股份有限公司 The analog switch of conduction impedance control circuit, control method and high linearity
CN108270444B (en) * 2018-02-08 2021-10-29 上海贝岭股份有限公司 Sampling network circuit and sampling chip
CN108599751B (en) * 2018-04-27 2021-10-08 中国电子科技集团公司第二十四研究所 Bootstrap circuit
CN108649953A (en) * 2018-05-04 2018-10-12 中国电子科技集团公司第二十四研究所 A kind of sampling switch and control method based on p-well floating technology
CN108696270B (en) * 2018-05-24 2022-02-01 上海艾为电子技术股份有限公司 Analog switch circuit
CN108806757A (en) * 2018-06-19 2018-11-13 广州领知信息技术有限公司 High-speed boosting type signal sampling transmitting switch
CN108777579B (en) * 2018-09-07 2023-08-11 广西师范大学 Grid voltage bootstrapping switch
CN111245413B (en) * 2020-01-20 2023-05-26 电子科技大学 High-speed high-linearity grid voltage bootstrap switch circuit
CN111900986B (en) * 2020-08-10 2022-08-16 中国电子科技集团公司第二十四研究所 Follow-up hold switch circuit
CN114421945A (en) * 2022-01-24 2022-04-29 福州大学 High-linearity bootstrap switch circuit for sensor and control method thereof
CN115378433B (en) * 2022-07-29 2023-10-03 北京时代民芯科技有限公司 1.25GHz broadband self-bias low-power-consumption sample hold circuit
CN115425958B (en) * 2022-11-04 2023-02-17 西安水木芯邦半导体设计有限公司 Gate-source voltage holding circuit for controlling high-voltage analog switch

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7286174B1 (en) * 2001-06-05 2007-10-23 Dalsa, Inc. Dual storage node pixel for CMOS sensor
JP2010187463A (en) * 2009-02-12 2010-08-26 Mitsumi Electric Co Ltd Charge pump circuit and device for switching power supply
CN201887738U (en) * 2010-10-09 2011-06-29 中国电子科技集团公司第五十八研究所 High-linearity-degree CMOS bootstrap sampling switch
CN102006041B (en) * 2010-12-24 2012-05-09 复旦大学 Usable-in-array bootstrapped switches realized by full-digital CMOS process
US8674863B2 (en) * 2011-06-07 2014-03-18 Microchip Technology Incorporated Distributed bootstrap switch

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