CN111162789B - Sampling hold circuit and electrical apparatus - Google Patents
Sampling hold circuit and electrical apparatus Download PDFInfo
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- CN111162789B CN111162789B CN202010058947.3A CN202010058947A CN111162789B CN 111162789 B CN111162789 B CN 111162789B CN 202010058947 A CN202010058947 A CN 202010058947A CN 111162789 B CN111162789 B CN 111162789B
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- H03M1/12—Analogue/digital converters
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Abstract
The invention discloses a sample hold circuit and an electric appliance, comprising: the first capacitor, the first field effect transistor and the second capacitor; one end of the first capacitor is respectively connected with the input end of the sample-and-hold circuit and the source electrode of the first field effect transistor, and the other end of the first capacitor is grounded; the drain electrodes of the first field effect transistors are coupled with one end of the second capacitor and the output end of the sampling hold circuit; the other end of the second capacitor is grounded. The sampling hold circuit provided by the invention can reduce the power-down rate of an output signal, reduce the on-resistance of a sampling switch, improve the linearity and reduce the overall power consumption.
Description
Technical Field
The invention relates to the field of integrated circuit design, in particular to a sampling hold circuit.
Background
The sampling hold circuit plays an important role in the fields of micro-mirror drive, biomedical treatment and the like. In a drive circuit with long signal holding time, the power-down rate of the sample-and-hold circuit determines the accuracy of the system, and a low power-down rate is beneficial to the multiplexing of other circuits of the system. Reducing the power-down rate of a sample-and-hold circuit generally requires a large sampling capacitor, resulting in a large chip area, so obtaining a lower power-down rate without increasing the chip area has important significance. A simple sample and hold circuit configuration is shown in fig. 1.
When the grid end is at high level, the circuit is in a sampling mode, and the input signal is stored in the capacitor C H A terminal; in the hold mode, the storage is held in the capacitor C H And as time goes longer, the smaller the leakage, the better. The gate-source voltage (V) is generally varied with the input signal GS ) The voltage will change along with the change, and the sampling switch conducting resistance will also change greatly, so that the linearity of the sampling hold circuit is deteriorated. Meanwhile, in order to improve the sampling speed, the smaller the on-resistance of the sampling switch is, the better the on-resistance is. The on-resistance of the traditional sampling switch changes along with the change of an input signal, the leakage of the sampling switch is serious, and a plurality of defects are revealed.
When the sample hold circuit is in the sampling mode, the sampling switch is turned off, and the charge on the sampling capacitor can pass through the samplingSwitch leakage, there are mainly three leakage paths: sub-threshold region current, reverse bias PN junction leakage current, accumulation region source-drain diffusion current. As shown in fig. 2. D DB2 Is a parasitic drain PN junction, D SB1 、D DB1 The source-drain and body-end parasitic diodes are respectively positioned in the accumulation region. The traditional mode for reducing the leakage current of the MOS transistor is the MOS transistor using a CMOS switch and a double-well process, but the measures can only reduce the leakage current of the MOS transistor, can not well compensate the sampling switch in a holding state, and periodically quantizes output capacitance voltage by using the ADC, so that the mode of counteracting the leakage current increases the complexity and the power consumption of the circuit.
Therefore, in view of the above-mentioned shortcomings, it is an urgent technical task for those skilled in the art to provide a sample-and-hold circuit that can reduce the power-off rate of the output signal, reduce the on-resistance of the sampling switch, improve the linearity, and reduce the overall power consumption.
Disclosure of Invention
In order to solve the above technical problem, the present invention discloses a sample-and-hold circuit, comprising: the first capacitor, the first field effect transistor and the second capacitor;
one end of the first capacitor is respectively connected with the input end of the sample-hold circuit and the source electrode of the first field effect transistor, and the other end of the first capacitor is grounded;
the drain electrodes of the first field effect transistors are coupled with one end of the second capacitor and the output end of the sampling hold circuit;
the other end of the second capacitor is grounded.
Further, still include: the circuit comprises a first switch, a first amplifier, a first resistor, a second switch, a first direct current source and a second direct current source;
one end of the first switch is coupled to the input end of the sample-and-hold circuit, and the other end of the first switch is coupled to one end of the first capacitor, the source of the first field effect transistor, and the positive input end of the first amplifier;
the negative electrode input ends of the first amplifiers are coupled with one end of the first resistor and the positive electrode of the first direct current source, and the output ends of the first amplifiers are coupled with the other end of the first resistor and one end of the second resistor;
the negative electrodes of the first direct current sources are both coupled with the negative power supply of the sample-and-hold circuit and the negative electrode of the second direct current source;
the other end of the second resistor is coupled with the grid electrode of the first field effect transistor, and one end of the second switch is coupled with a reference voltage;
the other end of the second switch is coupled with the anode of the second direct current source.
Further, still include: a third switch;
one end of the third switch is coupled with the other end of the second resistor, the grid electrode of the first field effect transistor and one end of the second switch, and the other end of the third switch is coupled with the reference voltage.
Further, still include: a fourth switch and a second amplifier;
one end of the fourth switch is coupled with the other end of the first switch, the positive input end of the first amplifier, one end of the first capacitor and the source electrode of the first field effect transistor; the other end of the fourth switch is coupled with the output end of the second amplifier and the negative input end of the second amplifier; and the positive input end of the second amplifier is coupled with one end of the second capacitor and the output end of the sample hold circuit.
Further, still include: and the source electrode, the drain electrode and the body end of the second field effect transistor are coupled with one end of the second capacitor and the output end of the sampling circuit.
Further, still include: a third field effect transistor;
the source electrode of the third field effect transistor is coupled with the source electrode of the first field effect transistor, and the body end of the third field effect transistor is biased at a positive power supply voltage V DD And the drain electrode of the third field effect transistor is coupled with one end of the second capacitor.
Further, the first switch, the second switch, the third switch and the fourth switch are all time-controlled switches.
Further, the third switch and the fourth switch are movably coupled.
Further, the capacitance value of the first capacitor is smaller than that of the second capacitor.
In another aspect, the present invention provides an electrical appliance, wherein the electrical appliance is provided with a sampling circuit, and the sampling circuit comprises any one of the above sample-and-hold circuits.
The implementation of the invention has the following beneficial effects:
the sampling hold circuit provided by the invention can reduce the power-down rate of an output signal, reduce the on-resistance of a sampling switch, improve the linearity and reduce the overall power consumption.
Drawings
In order to make those skilled in the art better understand the technical solutions in the present application, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are only a part of the embodiments of the present application, and not all the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.
FIG. 1 is a schematic diagram of a prior art sample and hold circuit;
FIG. 2 is a diagram illustrating a PMOS leakage current mechanism in the prior art;
FIG. 3 is a circuit diagram of a sample-and-hold circuit provided by the present invention;
FIG. 4 is a circuit diagram of another sample and hold circuit provided by the present invention;
FIG. 5 is a circuit diagram of yet another sample and hold circuit provided by the present invention;
FIG. 6 is a circuit diagram of yet another sample and hold circuit provided in the present invention;
FIG. 7 is a circuit diagram of yet another alternative select sample and hold circuit provided by the present invention;
FIG. 8 is a simulation diagram of the variation of the ON resistance of the sample-and-hold circuit with the input signal according to the present invention;
FIG. 9 is a schematic current flow diagram of another alternative select sample and hold circuit provided in accordance with the present invention;
FIG. 10 is a comparison graph of power-down rates with and without leakage compensation according to the present invention;
FIG. 11 is a schematic diagram of a simulation curve of a sample-and-hold circuit according to the present invention;
wherein the first switch-S 1 First capacitance-C 0 First field effect transistor-M 2 Second capacitance-C H First amplifier-A 1 A first resistance-R 2 A second resistance-R 1 A second switch-S 2 A first DC source I 1 A second DC source I 2 Third switch-S 3 Fourth switch-S 4 Second amplifier-A 0 Second field effect transistor M 3 Third field effect transistor M 1 。
Detailed Description
In order to make those skilled in the art better understand the technical solutions in the present application, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are only a part of the embodiments of the present application, and not all the embodiments. All other embodiments obtained by a person of ordinary skill in the art based on the embodiments in the present application without making creative efforts shall fall within the protection scope of the present application.
It will be understood that when an element is referred to as being "coupled" to another element, it can be directly coupled to the other element or intervening elements may also be present. The coupling may be a communication connection or a circuit connection.
Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein in the description of the present application is for the purpose of describing particular embodiments only and is not intended to be limiting of the application.
Fig. 3 is a circuit diagram of a sample-and-hold circuit provided by the present invention, and as shown in fig. 3, the present invention provides a sample-and-hold circuit, including: the first capacitor, the first field effect transistor and the second capacitor;
one end of the first capacitor is respectively connected with the input end of the sample-hold circuit and the source electrode of the first field effect transistor, and the other end of the first capacitor is grounded;
the drain electrodes of the first field effect transistors are coupled with one end of the second capacitor and the output end of the sampling hold circuit;
the other end of the second capacitor is grounded.
Specifically, the rated parameters of the first capacitor, the second capacitor and the first field effect transistor are not specifically limited in the embodiments of the present specification, and may be set according to actual needs, and the rated parameters of the first capacitor and the second capacitor may be equal or unequal. Preferably, the capacitance value of the first capacitor is smaller than the capacitance value of the second capacitor. Wherein, the first field effect transistor can be an insulated gate field effect transistor.
The sampling hold circuit provided by the invention can reduce the power-off rate of an output signal, reduce the on-resistance of the sampling switch, improve the linearity and reduce the overall power consumption through the arrangement of the first capacitor, the second capacitor and the first field effect transistor.
On the basis of the above embodiments, in an embodiment of the present specification, as shown in fig. 4, fig. 4 is a circuit diagram of another sample-and-hold circuit provided by the present invention; further comprising: the circuit comprises a first switch, a first amplifier, a first resistor, a second switch, a first direct current source and a second direct current source;
one end of the first switch is coupled to the input end of the sample-and-hold circuit, and the other end of the first switch is coupled to one end of the first capacitor, the source of the first field effect transistor, and the positive input end of the first amplifier;
the negative electrode input ends of the first amplifiers are coupled with one end of the first resistor and the positive electrode of the first direct current source, and the output ends of the first amplifiers are coupled with the other end of the first resistor and one end of the second resistor;
the negative electrodes of the first direct current sources are both coupled with the negative power supply of the sample-and-hold circuit and the negative electrode of the second direct current source;
the other end of the second resistor is coupled with the grid electrode of the first field effect transistor, and one end of the second switch is coupled with a reference voltage;
the other end of the second switch is coupled with the anode of the second direct current source.
Specifically, rated operating parameters of the first switch, the first amplifier, the first resistor, the second switch, the first dc source, and the second dc source are not specifically limited in the embodiments of the present specification, and may be set according to actual needs.
Adding a first amplifier A 1 A second resistor R 1 A first resistor R 2 And a first current source I 1 A second current source I 2 To form a constant first field effect transistor M 2 Gate source voltage V GS So that it does not vary with input signal, V ref Used in the holding stage at this time, so that M 2 In the deep accumulation region, M is reduced 2 The sub-threshold region of (3) is leaky.
On the basis of the above embodiment, in an embodiment of the present specification, the method further includes: a third switch;
one end of the third switch is coupled with the other end of the second resistor, the grid electrode of the first field effect transistor and one end of the second switch, and the other end of the third switch is coupled with the reference voltage.
On the basis of the above embodiments, in an embodiment of this specification, as shown in fig. 5, fig. 5 is a circuit diagram of another sample-and-hold circuit provided by the present invention, further including: a fourth switch and a second amplifier;
one end of the fourth switch is coupled with the other end of the first switch, the positive input end of the first amplifier, one end of the first capacitor and the source electrode of the first field effect transistor; the other end of the fourth switch is coupled with the output end of the second amplifier and the negative electrode input end of the second amplifier; and the positive input end of the second amplifier is coupled with one end of the second capacitor and the output end of the sample hold circuit.
Specifically, the fourth switch and the third switch may be the same switch, fig. 7 is a circuit diagram of yet another sample-and-hold circuit provided by the present invention, as shown in fig. 7, and the rated parameters of the fourth switch and the second amplifier are not specifically limited in the embodiment of the present specification.
A second amplifier A is added 0 Connected in unity gain form using a second amplifier A 0 The offset voltage at both ends of the first field effect transistor M 2 Compensating a second capacitor (i.e., a sampling capacitor) C for its source and drain terminal voltages H The leakage current of (1).
On the basis of the above embodiments, in an embodiment of the present specification, the method further includes: and the source electrode, the drain electrode and the body end of the second field effect transistor are all coupled with one end of the second capacitor and the output end of the sampling circuit.
Specifically, the second field effect transistors may be the same as or different from the first field effect transistors, and the rated parameters of the second field effect transistors are not specifically limited in the embodiments of the present specification.
On the basis of the above embodiments, in an embodiment of this specification, as shown in fig. 6, fig. 6 is a circuit diagram of another sample-and-hold circuit provided by the present invention, and further includes: a third field effect transistor;
the source electrode of the third field effect transistor is coupled with the source electrode of the first field effect transistor, and the body end of the third field effect transistor is biased at a positive power supply voltage V DD And the drain electrode of the third field effect transistor is coupled with one end of the second capacitor.
Specifically, the third field effect transistors may be the same as or different from the first field effect transistors, and the rated parameters of the third field effect transistors are not specifically limited in the embodiments of the present specification.
In particular, the third field effect transistor M 1 Is connected with body end at V DD Formula source end and first field effect transistor M 2 Is connected with the source terminal and the drain terminal is also connected with the first field effect tube M 2 The drain ends are connected. Using a third field effect transistor M 1 Compensating for C by reverse biased PN junction body leakage current H The leakage of electricity.
On the basis of the above embodiments, in an embodiment of this specification, the first switch, the second switch, the third switch, and the fourth switch are all time-controlled switches.
Specifically, the first switch, the second switch, the third switch and the fourth switch are all delay switches, the specific delay time is not specifically limited in the embodiment of the present specification, and may be set according to actual needs,
on the basis of the above embodiments, in an embodiment of the present specification, the third switch and the fourth switch are movably coupled.
In particular, the third switch S 3 And a fourth switch S 4 Simultaneously open and close. I.e. the third switch S 3 Controlling the input of a reference voltage, a fourth switch S 4 Controlling the second amplifier A 0 Whether the output end is connected with the first field effect transistor M 2 Are coupled.
On the basis of the above embodiments, in an embodiment of the present specification, a capacitance value of the first capacitor is smaller than a capacitance value of the second capacitor.
Exemplary when CLK 1 、CLK 2 At a high level, CLK 3 At a low level, the first switch S 1 And a second switch S 2 Closed, third switch S 3 And a fourth switch S 4 Breaking the circuit and entering a sampling mode when CLK is applied 1 、CLK 2 At a low level, CLK 3 First switch S at high level 1 And a second switch S 2 Open, third switch S 3 And a fourth switch S 4 Closed, third field effect transistor M 1 And a first field effect transistor M 2 Shut down and the circuit enters hold mode. When the clock signal CLK 1 And CLK 2 At high level, the first switch S 1 And a second switch S 2 Closure, utilization ofFirst amplifier A 1 Virtual short characteristic makes input voltage V in Current source I same as point Q 1 A current source I 2 Respectively flow through the second resistors R 1 A first resistor R 2 And enabling the sampling switch to generate a constant grid source voltage value, wherein the constant grid source voltage value is represented by the following formula:
V in -V g ＝I 1 R 2 -I 2 R 1
due to R 1 、R 2 And I 1 、I 2 Is constant, so the gate source voltage value does not change with the input signal, and the on-resistance R on,eq The simulation result along with the change of the input signal is shown in fig. 8, the control is changed between 1.5 and 2.5K, and the nonlinear distortion of a sampling switch (namely a first field effect transistor) caused by the change of the grid source voltage is improved.
FIG. 9 is a schematic diagram of a current flow direction of another sample-and-hold circuit according to the present invention, wherein when the circuit is in a hold mode, the reference voltage V in FIG. 6 is properly adjusted ref Value of so that the first field effect transistor M 2 In the deep accumulation region, the subthreshold current is reduced. At this time, although the current between the source and the drain is reduced, if the first field effect transistor M 2 There is a voltage difference between the source and drain, and a small amount of current I SD Therefore, the second amplifier A is used when the third switch S3 and the fourth switch S4 are closed 0 Offset voltage of the compensating capacitor C H The leakage of electricity. The body and the drain of the first field effect transistor M2 are connected together, and a third field effect transistor M1 is arranged on the body and the drain, and the body end of the third field effect transistor M1 is biased at a high potential V DD Using the leakage current I of the reverse biased PN junction of the M1 body of the third field effect tube BD Again compensate for C H And charge is leaked upwards.
Fig. 10 is a comparison graph of power-down rates with and without leakage compensation provided by the present invention, where the power-down rate in ordinate is a logarithmic coordinate system, and the simulation time is set to 100ms. As can be seen from fig. 10, the power down rate decreases by nearly 300 times after the leakage compensation is added. The overall power consumption was at 1.106mW. The design effectively reduces the power failure rate of the sample-and-hold circuit and the on-resistance of the sampling switch, improves the linearity and reduces the power consumption of the total sample-and-hold circuit. Fig. 11 is a schematic diagram of a simulation curve of a sample-and-hold circuit provided by the present invention, and as shown in fig. 11, the simulation curve of the whole sample-and-hold circuit is within 180 μ s.
The sampling hold circuit provided by the invention adopts an operational first amplifier A 1 A first resistor R 2 A second resistor R 1 A first current source I 1 A second current source I 2 The constant sampling switch grid source voltage is generated, so that the on-resistance of the sampling switch is not changed along with the change of an input signal, and the linearity of the sampling switch is improved.
The invention utilizes a second amplifier A 0 So that the first field effect transistor M 2 If the voltage of the first field effect transistor M changes 2 When the voltage at the source end is higher than that at the drain end, a compensation current is generated, so that the first field effect transistor M is compensated 2 The leakage current of (2).
The invention also relates to a first field effect transistor M 2 The source end and the body end of the second FET are connected together, and the body drain end is connected with a third field effect transistor M 1 A third field effect transistor M 1 Is biased at a high potential V DD Using a third field effect transistor M 1 Body-drain reverse bias PN junction leakage current I BD Again compensate for C H Upper leakage charge.
In the holding stage of the sample-and-hold circuit, the reference voltage V is reasonably adjusted ref The sub-threshold current can be reduced by biasing the first field effect transistor (i.e., the sampling switch transistor) in the deep accumulation region.
The sample-and-hold circuit provided by the invention can be applied to circuits with low speed, low power consumption and low power failure rate, and has a wide application range.
In another aspect, the present invention provides an electrical appliance provided with a sampling circuit comprising any one of the sample-and-hold circuits described above.
The electric appliance provided by the embodiment comprises the sampling and holding circuit, so that the effects and the like of the electric appliance are the same as those of the sampling and holding circuit, and are not described again.
It should be noted that, in the description of the present application, the terms "first", "second", and the like are used for descriptive purposes only and to distinguish similar objects, and there is no order between the two, and no indication or implication of relative importance should be understood. In addition, in the description of the present application, "a plurality" means two or more unless otherwise specified.
It is to be understood that the above description is intended to be illustrative, and not restrictive. Many embodiments and many applications other than the examples provided will be apparent to those of skill in the art upon reading the above description. The scope of the present teachings should, therefore, be determined not with reference to the above description, but should instead be determined with reference to the pending claims along with the full scope of equivalents to which such claims are entitled. The disclosures of all articles and references, including patent applications and publications, are hereby incorporated by reference for all purposes. The omission in the foregoing claims of any aspect of subject matter that is disclosed herein is not intended to forego the subject matter and should not be construed as an admission that the applicant does not consider such subject matter to be part of the disclosed subject matter.
Claims (10)
1. A sample and hold circuit, comprising: the first capacitor, the first field effect transistor and the second capacitor;
one end of the first capacitor is respectively connected with the input end of the sample-and-hold circuit and the source electrode of the first field effect transistor, and the other end of the first capacitor is grounded;
the drain electrodes of the first field effect transistors are coupled with one end of the second capacitor and the output end of the sampling hold circuit;
the other end of the second capacitor is grounded.
2. The sample-and-hold circuit of claim 1, further comprising: the circuit comprises a first switch, a first amplifier, a first resistor, a second switch, a first direct current source and a second direct current source;
one end of the first switch is coupled to the input end of the sample-and-hold circuit, and the other end of the first switch is coupled to one end of the first capacitor, the source of the first field effect transistor, and the positive input end of the first amplifier;
the negative electrode input ends of the first amplifiers are coupled with one end of the first resistor and the positive electrode of the first direct current source, and the output ends of the first amplifiers are coupled with the other end of the first resistor and one end of the second resistor;
the negative electrodes of the first direct current sources are coupled with the negative power supply of the sample-and-hold circuit and the negative electrode of the second direct current source;
the other end of the second resistor is coupled with the grid electrode of the first field effect transistor, and one end of the second switch is coupled with a reference voltage;
the other end of the second switch is coupled with the anode of the second direct current source.
3. The sample-and-hold circuit of claim 2, further comprising: a third switch;
one end of the third switch is coupled with the other end of the second resistor, the grid electrode of the first field effect transistor and one end of the second switch, and the other end of the third switch is coupled with the reference voltage.
4. The sample-and-hold circuit of claim 3, further comprising: a fourth switch and a second amplifier;
one end of the fourth switch is coupled with the other end of the first switch, the positive input end of the first amplifier, one end of the first capacitor and the source electrode of the first field effect transistor; the other end of the fourth switch is coupled with the output end of the second amplifier and the negative input end of the second amplifier; and the positive input ends of the second amplifiers are coupled with one end of the second capacitor and the output end of the sample hold circuit.
5. The sample-and-hold circuit of claim 4, further comprising: and the source electrode, the drain electrode and the body end of the second field effect transistor are coupled with one end of the second capacitor and the output end of the sampling circuit.
6. The sample-and-hold circuit of claim 5, further comprising: a third field effect transistor;
the source electrode of the third field effect transistor is coupled with the source electrode of the first field effect transistor, and the body end of the third field effect transistor is biased at a positive power supply voltage V DD And the drain electrode of the third field effect transistor is coupled with one end of the second capacitor.
7. The sample-and-hold circuit of claim 6, wherein the first switch, the second switch, the third switch, and the fourth switch are all clocked switches.
8. The sample-and-hold circuit of claim 7, wherein the third switch and the fourth switch are movably coupled.
9. The sample-and-hold circuit of claim 8, wherein the capacitance value of the first capacitor is less than the capacitance value of the second capacitor.
10. An electrical appliance, characterized in that the electrical appliance is provided with a sampling circuit comprising a sample-and-hold circuit according to any of claims 1-9.
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Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101986570A (en) * | 2010-11-02 | 2011-03-16 | 西安电子科技大学 | Analog-to-digital converter (ADC) and sample-and-hold circuit thereof |
| CN106027010A (en) * | 2016-05-10 | 2016-10-12 | 天津大学 | Low-current-leakage analog switch applied to low-speed sample-and-hold circuit |
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| CN103762986A (en) * | 2014-01-16 | 2014-04-30 | 四川和芯微电子股份有限公司 | Sampling hold switch circuit |
| US20190238125A1 (en) * | 2018-01-29 | 2019-08-01 | MACOM Technology Solutions Holding, Inc. | Sampling circuitry with temperature insensitive bandwidth |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101986570A (en) * | 2010-11-02 | 2011-03-16 | 西安电子科技大学 | Analog-to-digital converter (ADC) and sample-and-hold circuit thereof |
| CN106027010A (en) * | 2016-05-10 | 2016-10-12 | 天津大学 | Low-current-leakage analog switch applied to low-speed sample-and-hold circuit |
Non-Patent Citations (1)
| Title |
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| 低电压低功耗CMOS采样保持电路;郑晓燕等;《电子器件》(第02期);全文 * |
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