CN106027010A - Low-current-leakage analog switch applied to low-speed sample-and-hold circuit - Google Patents
Low-current-leakage analog switch applied to low-speed sample-and-hold circuit Download PDFInfo
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- CN106027010A CN106027010A CN201610309534.1A CN201610309534A CN106027010A CN 106027010 A CN106027010 A CN 106027010A CN 201610309534 A CN201610309534 A CN 201610309534A CN 106027010 A CN106027010 A CN 106027010A
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- nmos tube
- operational amplifier
- drain electrode
- transmission gate
- analog switch
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
- H03K17/51—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used
- H03K17/56—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices
- H03K17/687—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices the devices being field-effect transistors
- H03K17/6871—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices the devices being field-effect transistors the output circuit comprising more than one controlled field-effect transistor
Abstract
The invention relates to the design field of an analog integrated circuit. In order to enable an S/H (Sample-and-hold) circuit to realize S/H functions better, improve the sample precision of the S/H circuit, reduce the charge leakage of the analog switch and further expand the application range of the S/H circuit, the invention provides an analog switch design which is applied to a low-speed S/H circuit and can realize relatively low charge leakage. The technical scheme provided by the analog switch is that the low-current-leakage analog switch applied to the low-speed S/H circuit is composed of transmission gates TG1, TG2 and TG3, and an operational amplifier. The transmission gates TG1 and TG2 are connected in series. The output end of the transmission gate TG2 is connected with the in-phase input end of the operational amplifier. The output end of the operational amplifier is connected with the input end of the transmission gate TG2 through the transmission gates TG3. The inverted-phase input end and the output end of the operational amplifier are connected. The analog switch is mainly applied to the design and production occasions of the analog integrated circuit.
Description
Technical field
The present invention relates to analogue layout field, particularly to a kind of Low dark curient being capable of low speed sampling hold circuit
Analog switch.
Background technology
Sampling keeps (Sample-and-hold, S/H) circuit to be an important functional device for analog signal processing.One typical case
S/H circuit comprise a MOSFET used as analog switch and a sampling capacitance, as shown in Figure 1.Analog switch
Be not preferably, owing to this switch has several leakage paths, cause the voltage kept in sampling capacitance to rise or under
Fall.In the analog switch of an off state, leakage current includes PN junction reverse biased current, sub-threshold current leakage and grid
Leakage current.Size and the Relative Contribution of leakage current are strongly depend on manufacture process.At low-down sample rate (about 1～1kHz),
Such as temperature sensor and the biosensor of super low-power consumption, the effect of leakage of switch is the most significant.The clock cycle of this length
The voltage error more serious than kT/c thermal noise can be caused, and when operating temperature and being the highest, this phenomenon will be more serious.
In view of the range of application of low speed S/H circuit, present invention research emphatically reduces leakage current under deep submicron process.
It is to use a bigger sampling capacitance that tradition solves the method for this problem, but bigger electric capacity needs front stage circuits higher
Driving, this will cause more source current demand.The biggest sampling capacitance also can be serious increase silicon area.Pass through
Measure the size of leakage current, be the most once suggested by the method injecting cancellation current.But, these methods need complicated
Circuit, the effectiveness of cancellation current is limited by equipment matching degree simultaneously.Substrate protective technology can make switch away from electric leakage node,
But this technology can be only applied in three trap CMOS technology or BiCMOS technique.
Summary of the invention
For overcoming the deficiencies in the prior art, it is contemplated that S/H circuit can preferably realize sampling and keep function, improve
Its levels of precision of sampling, reduces analog switch charge leakage, and then the range of application of expansion S/H circuit, proposes one and be applied to
Low speed sampling hold circuit can realize the analog switch design of relatively low charge leakage.The technical solution used in the present invention is, application
In the Low dark curient analog switch of low speed sampling hold circuit, it is made up of transmission gate TG1, TG2, TG3 and operational amplifier, passes
Defeated door TG1, TG2 concatenate, transmission gate TG2 outfan concatenation operation amplifier in-phase input end, operational amplifier output terminal warp
Transmission gate TG3 connects transmission gate TG2 input, and operational amplifier inverting input is connected with outfan.
NMOS tube N1 and PMOS P1 form transmission gate TG1, and NMOS tube N2 forms transmission gate with PMOS P2
TG2, NMOS tube N3 forms transmission gate TG3 with PMOS P3；The drain electrode of NMOS tube N1 is connected with input Vin,
Substrate is connected on ground wire, and grid is connected on clock clk+；The source electrode of PMOS P1 connects with the drain electrode of NMOS tube N1
Connecing, substrate is connected on power vd D, and grid is connected on clock clk-, and drain electrode is connected with the source electrode of NMOS tube N1, and
If this end points is electromotive force is Vx；The drain electrode of NMOS tube N2 is connected with the source electrode of N1, and substrate is connected on ground wire, and grid is even
Receive on clock clk+；The source electrode of PMOS P2 is connected with the drain electrode of NMOS tube N2, and substrate is connected on power vd D,
Grid is connected on clock clk-, and drain electrode is connected with the source electrode of NMOS tube N2, and this end also serves as the output of on-off circuit simultaneously
End；The drain electrode of NMOS tube N3 is connected with the source electrode of N1, and substrate is connected on ground wire, and grid is connected on clock clk+；
The source electrode of PMOS P3 is connected with the drain electrode of NMOS tube N3, and substrate is connected on power vd D, and grid is connected to clock
On clk-, drain electrode is connected with the source electrode of NMOS tube N3；The positive input terminal of operational amplifier is connected with outfan, operation amplifier
The negative input end of device is connected with the outfan of operational amplifier, and the outfan of operational amplifier is connected with the source electrode of N3.
Outfan connects sampling capacitance Cs, and the sampling capacitance Cs other end is connected with ground wire, forms sampling hold circuit.
The feature of the present invention and providing the benefit that:
The leakage electricity that the Low dark curient analog switch being applied to low speed sampling hold circuit proposed effectively reduces under off state
Stream.At 27 DEG C, the leakage current order of magnitude 108 orders of magnitude little compared with traditional switch of switch are proposed；Even if when operation temperature liter
High to 150 DEG C, owing to the pull-down current of PN joint can not be completely counterbalanced by each other, the leakage current of the switch proposed still is opened than tradition
Close is low 104 times.This S/H circuit switched is applied can preferably to realize sampling and keep function, it is possible to it to be greatly improved and adopts
Sample levels of precision, and then expand the range of application of S/H circuit.
Accompanying drawing illustrates:
Fig. 1 is traditional analog switch sampling hold circuit.In figure, a PN junction pull-down current, b sub-threshold-conducting electric current, c
Grid leakage current.
Fig. 2 is the circuit diagram of the low speed sampling hold circuit using Low dark curient analog switch.
Fig. 3 is that the present invention compares with traditional analog switch leakage current at different operating temperatures.
Detailed description of the invention
In the present invention, shielded inspiring of concept by triaxle cable, by the way of voltage drop is clamped to zero, and then proposed
Low leakage analog switch.
The proposed by the invention Low dark curient analog switch structure being applied to low speed sampling hold circuit as shown in Fig. 2 solid box,
It is mainly made up of NMOS tube N1～N3, PMOS P1～P3 and operational amplifier (abbreviation amplifier).In this switch respectively
The annexation of individual assembly is as follows: the drain electrode of NMOS tube N1 is connected with input Vin, and substrate is connected on ground wire, grid
It is connected on clock clk+；The source electrode of PMOS P1 is connected with the drain electrode of NMOS tube N1, and substrate is connected to power vd D
On, grid is connected on clock clk-, and drain electrode is connected with the source electrode of NMOS tube N1, and to set this end points as electromotive force be Vx；NMOS
The drain electrode of pipe N2 is connected with the source electrode of N1, and substrate is connected on ground wire, and grid is connected on clock clk+；PMOS P2
Source electrode be connected with the drain electrode of NMOS tube N2, substrate is connected on power vd D, and grid is connected on clock clk-, drain electrode
Being connected with the source electrode of NMOS tube N2, this end also serves as the outfan of on-off circuit simultaneously；The drain electrode of NMOS tube N3 and N1
Source electrode be connected, substrate is connected on ground wire, and grid is connected on clock clk+；The source electrode of PMOS P3 and NMOS tube
The drain electrode of N3 connects, and substrate is connected on power vd D, and grid is connected on clock clk-, drain electrode and NMOS tube N3
Source electrode connects；The positive input terminal of amplifier is connected with the outfan of on-off circuit, and the negative input end of amplifier is connected with the outfan of amplifier,
The outfan of amplifier is connected with the source electrode of N3.Wherein NMOS tube N1 and PMOS P1 form transmission gate TG1, wherein
NMOS tube N2 and PMOS P2 form transmission gate TG2, and wherein NMOS tube N3 forms transmission gate with PMOS P3
TG3.Proposed the Low dark curient performance of switch for convenience of detection, connected sampling capacitance Cs at output switching terminal, adopted with switch composition
Sample holding circuit, as shown in Figure 2.Sampling capacitance Cs one end is connected with the outfan of on-off circuit, and the other end is connected with ground wire.
As it is shown in figure 1, three kinds of current contribution below traditional analog switch leakage current, it is respectively as follows: subthreshold conduction electric current, PN
Knot pull-down current, grid leakage current.Wherein grid leakage current is under the conditions of 0.18 micrometre CMOS process, and its order of magnitude can be neglected
Slightly disregard.Therefore this patent focuses on reduction subthreshold conduction electric current and PN junction pull-down current.
Reduce the operation principle of subthreshold conduction electric current: traditional analog switch has electric potential difference due to metal-oxide-semiconductor source and drain two ends,
Cause having between source and drain carrier moving, cause change in electrical charge in sampling capacitance, sampling accuracy to decline.As in figure 2 it is shown, work as
Switch is in opening (clk+=1, clk-=0), switchs as two traditional series-connected transmission doors are operated.At switch
In off state (clk+=0, clk-=1), in transmission gate TG2, a Unity-gain buffer is passed through at the source and drain two ends of metal-oxide-semiconductor
Device is connected.Therefore, Vx voltage bias identical with Vout, the transmission gate TG2 of NMOS tube N2 and PMOS P2 composition
Voltage drop be clamped to zero, the sub-threshold leakage of TG2 is reduced to insignificant level.TG1 is isolated by Vx with analog switch
Open.Meanwhile, the Leakage Current contributed by subthreshold current in switch is temperature-resistant.
Reduce PN and connect the operation principle of pull-down current: as shown in Fig. 2 dotted line frame, from the output node of TG2 and VDD and
Ground wire two back-biased PN junctions of Equivalent conjunction respectively, when output node is charged by a PN junction reverse biased current,
Output node is discharged by another PN junction reverse biased current.Therefore, the two PN junction reverse biased current can be one
Determine to cancel each other in degree, but this counteracting operation is thermally sensitive.So when the temperature increases, two pull-down currents are mutual
Neutralization effect declines, and the leakage current now increased mainly is provided by the pull-down current failing to offset.
For making the object, technical solutions and advantages of the present invention become apparent from, provide embodiment of the present invention below in conjunction with example
Specifically describe.In this example, NMOS tube N1～N3, PMOS P1～P3 all use grid width to be 1um, a length of 180nm of grid
Metal-oxide-semiconductor；The capacitance of sampling capacitance Cs is 1pF；Op-amp gain bandwidth product is 12MHz, and DC current gain is
139dB, electric current is 450uA, and dynamic range is 70mV to 3.3V.The analog switch proposed is at 0.18 micron of 1.8V of standard
Emulate under CMOS technology.When switch is off state, the setting of Vin and Vout is respectively 1.8V and 0V, so
Afterwards the leakage current of switch is simulated.Fig. 3 shows proposed switch and switchs in different operation temperature from tradition TG
Leakage current under the conditions of degree.At 27 DEG C, switch leakage current in the off case is 10-19A, at 150 DEG C, it is let out
Leakage current still can reach 10-13A。
Claims (3)
1. it is applied to a Low dark curient analog switch for low speed sampling hold circuit, it is characterized in that, by transmission gate TG1, TG2, TG3
And operational amplifier composition, transmission gate TG1, TG2 concatenation, transmission gate TG2 outfan concatenation operation amplifier homophase is defeated
Entering end, operational amplifier output terminal connects transmission gate TG2 input, operational amplifier inverting input through transmission gate TG3
It is connected with outfan.
It is applied to the Low dark curient analog switch of low speed sampling hold circuit the most as claimed in claim 1, it is characterized in that, NMOS tube
N1 and PMOS P1 form transmission gate TG1, and NMOS tube N2 forms transmission gate TG2, NMOS with PMOS P2
Pipe N3 forms transmission gate TG3 with PMOS P3；The drain electrode of NMOS tube N1 is connected with input Vin, and substrate is even
Receiving on ground wire, grid is connected on clock clk+；The source electrode of PMOS P1 is connected with the drain electrode of NMOS tube N1,
Substrate is connected on power vd D, and grid is connected on clock clk-, and drain electrode is connected with the source electrode of NMOS tube N1, and
If this end points is electromotive force is Vx；The drain electrode of NMOS tube N2 is connected with the source electrode of N1, and substrate is connected on ground wire, grid
It is connected on clock clk+；The source electrode of PMOS P2 is connected with the drain electrode of NMOS tube N2, and substrate is connected to power vd D
On, grid is connected on clock clk-, and drain electrode is connected with the source electrode of NMOS tube N2, and this end also serves as on-off circuit simultaneously
Outfan；The drain electrode of NMOS tube N3 is connected with the source electrode of N1, and substrate is connected on ground wire, and grid is connected to clock
On clk+；The source electrode of PMOS P3 is connected with the drain electrode of NMOS tube N3, and substrate is connected on power vd D, grid
Being connected on clock clk-, drain electrode is connected with the source electrode of NMOS tube N3；The positive input terminal of operational amplifier and outfan phase
Even, the negative input end of operational amplifier is connected with the outfan of operational amplifier, the outfan of operational amplifier and the source of N3
The most connected.
Being applied to the Low dark curient analog switch of low speed sampling hold circuit the most as claimed in claim 1, it is characterized in that, outfan connects
Sampling capacitance Cs, the sampling capacitance Cs other end is connected with ground wire, forms sampling hold circuit.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201610309534.1A CN106027010A (en) | 2016-05-10 | 2016-05-10 | Low-current-leakage analog switch applied to low-speed sample-and-hold circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201610309534.1A CN106027010A (en) | 2016-05-10 | 2016-05-10 | Low-current-leakage analog switch applied to low-speed sample-and-hold circuit |
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| CN106027010A true CN106027010A (en) | 2016-10-12 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201610309534.1A Pending CN106027010A (en) | 2016-05-10 | 2016-05-10 | Low-current-leakage analog switch applied to low-speed sample-and-hold circuit |
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Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106656132A (en) * | 2016-12-31 | 2017-05-10 | 唯捷创芯(天津)电子技术股份有限公司 | Extremely low current leakage analog switch, chip and communication terminal |
| CN111162789A (en) * | 2020-01-19 | 2020-05-15 | 中国科学院上海微系统与信息技术研究所 | Sampling hold circuit and electrical apparatus |
| CN113098510A (en) * | 2019-12-23 | 2021-07-09 | 华润微集成电路(无锡)有限公司 | Sampling hold circuit structure for eliminating offset function |
| CN116054796A (en) * | 2023-01-05 | 2023-05-02 | 核芯互联科技(青岛)有限公司 | Anti-leakage switch |
| CN113098510B (en) * | 2019-12-23 | 2024-04-26 | 华润微集成电路(无锡)有限公司 | Sample hold circuit structure for eliminating offset function |
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2016
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Patent Citations (4)
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Non-Patent Citations (1)
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| JIN JYH SU ET AL.: "A Low-Leakage Body-Guarded Analog Switch in 0.35-μm BiCMOS and Its Applications in Low-Speed Switched-Capacitor Circuits", 《IEEE TRANSACTIONS ON CIRCUITS AND SYSTEM II:EXPRESS BRIEFS》 * |
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106656132A (en) * | 2016-12-31 | 2017-05-10 | 唯捷创芯(天津)电子技术股份有限公司 | Extremely low current leakage analog switch, chip and communication terminal |
| CN106656132B (en) * | 2016-12-31 | 2023-08-04 | 唯捷创芯(天津)电子技术股份有限公司 | Extremely low electric leakage analog switch, chip and communication terminal |
| CN113098510A (en) * | 2019-12-23 | 2021-07-09 | 华润微集成电路(无锡)有限公司 | Sampling hold circuit structure for eliminating offset function |
| CN113098510B (en) * | 2019-12-23 | 2024-04-26 | 华润微集成电路(无锡)有限公司 | Sample hold circuit structure for eliminating offset function |
| CN111162789A (en) * | 2020-01-19 | 2020-05-15 | 中国科学院上海微系统与信息技术研究所 | Sampling hold circuit and electrical apparatus |
| CN111162789B (en) * | 2020-01-19 | 2023-03-31 | 中国科学院上海微系统与信息技术研究所 | Sampling hold circuit and electrical apparatus |
| CN116054796A (en) * | 2023-01-05 | 2023-05-02 | 核芯互联科技(青岛)有限公司 | Anti-leakage switch |
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Application publication date: 20161012 |