CN110149111B - Bootstrap switch circuit and control method thereof - Google Patents

Bootstrap switch circuit and control method thereof Download PDF

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Publication number
CN110149111B
CN110149111B CN201910311082.4A CN201910311082A CN110149111B CN 110149111 B CN110149111 B CN 110149111B CN 201910311082 A CN201910311082 A CN 201910311082A CN 110149111 B CN110149111 B CN 110149111B
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tube
capacitor
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pmos
nmos
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Zhuhai Eeasy Electronic Tech Co ltd
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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
    • H03K17/51—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used
    • H03K17/56—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices
    • H03K17/687—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices the devices being field-effect transistors
    • H03K17/6871—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices the devices being field-effect transistors the output circuit comprising more than one controlled field-effect transistor
    • H03K17/6872—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices the devices being field-effect transistors the output circuit comprising more than one controlled field-effect transistor using complementary field-effect transistors
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K2217/00—Indexing scheme related to electronic switching or gating, i.e. not by contact-making or -breaking covered by H03K17/00
    • H03K2217/0081—Power supply means, e.g. to the switch driver
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02B—CLIMATE CHANGE MITIGATION TECHNOLOGIES RELATED TO BUILDINGS, e.g. HOUSING, HOUSE APPLIANCES OR RELATED END-USER APPLICATIONS
    • Y02B70/00—Technologies for an efficient end-user side electric power management and consumption
    • Y02B70/10—Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes

Abstract

The invention discloses a bootstrap switching circuit, which comprises a first control module, a second control module and a conduction switching tube MP9, wherein the conduction switching tube MP9 adopts a PMOS tube, the first control module is connected with the second control module and is used for controlling the second control module, the second control module is connected with a grid electrode of the conduction switching tube MP9 and is used for controlling the conduction and the disconnection of the conduction switching tube MP9, a source electrode of the conduction switching tube MP9 is connected with an input signal Vin, and a drain electrode of the conduction switching tube MP9 is connected with an output signal Vout. The PMOS is adopted as the on-switch tube, so that nonlinear distortion caused by a body effect can be completely eliminated, and the total harmonic distortion can reach-110 db; the control method can ensure that the withstand voltage of all MOS tubes meets the requirements of corresponding process, the voltage difference of the gate-source voltage VGS, the gate-drain voltage VGD and the source-drain voltage VSD of all MOS tubes is in the range of-VDD to VDD, and the parasitic diodes of all MOS tubes are kept in the reverse bias state, so that the situation of larger electric leakage does not exist, the safety and the reliability of the circuit are ensured, and the service life is longer.

Description

Bootstrap switch circuit and control method thereof
Technical Field
The invention relates to the technical field of integrated circuits, in particular to a bootstrap switch circuit and a control method thereof.
Background
As consumer electronics demand lower power consumption becomes more stringent, reducing the supply voltage is currently the most straightforward way. However, lower supply voltages, particularly ultra-low supply voltages, present a significant challenge for the design of analog circuits. Digital-to-analog conversion is used as an essential module for modern communication and sensor systems, and signal output swing has been limited in lower power systems. However, more seriously, under the low-voltage condition, the nonlinear factor brought by the common MOS switch tube is more influenced, so that the signal-to-noise-and-distortion ratio (SNDR) performance of the digital-to-analog converter is further reduced. In high performance digital-to-analog converters, bootstrap switches are therefore commonly employed to reduce the non-linearities of the path switching resistance, thereby improving or maintaining the SNDR performance of the converter.
As shown in fig. 1, fig. 1 is a conventional bootstrap switch circuit. When clk=0, the NMOS transistor MN1 is turned on, the NMOS transistor MN2 is turned off, the PMOS transistor MP3 is turned on, the NMOS transistor MN5 is turned on, the NMOS transistor MN6 is turned on, and the NMOS transistor MN7 is turned off. The gate potential of the NMOS transistor MN8 is discharged to the ground through the NMOS transistors MN5 and MN6, so that the NMOS transistor MN8 is in an off state. The grid potential of the PMOS tube MP2 is pulled to the power supply through the PMOS tube MP3, and the PMOS tube MP2 is turned off. The gate potential of the PMOS tube MP1 is pulled to the ground, and the PMOS tube MP1 is conducted. The positive potential of the capacitor C1 is precharged to VDD, and the negative potential is precharged to 0. When clk=vdd, the NMOS transistor MN1 is turned off, and the NMOS transistor MN2 is turned on to turn on the PMOS transistor MP2, and at the same time, the NMOS transistor MN6 is turned off, and the NMOS transistor MN7 is turned on to turn on the NMOS transistor MN 4. The negative electrode of the capacitor C1 is charged by the signal Vin through the NMOS transistor MN 4. Because the charge on the capacitor C1 has no bleed-off path, the positive voltage of the capacitor C1 will be bootstrapped to vdd+vin according to the charge conservation principle, and the voltage drives the on-switch MN8 through the PMOS transistor MP2, so that the gate-source voltage vgs= (vdd+vin) -vin=vdd of the on-switch MN8 is made to be conductive, and the gate-source voltage VGS of the on-switch MN8 is independent of the input signal. In the gate-source voltage conduction stage of the on-switch MN8, the expression of the on-resistance is as follows without considering the channel length modulation effect and the body effect:
Figure GDA0002102674310000011
considering the body effect:
Figure GDA0002102674310000012
wherein μ is electron mobility, C ox Is the capacitance of the gate oxide layer, W/L is the width-to-length ratio of the MOS tube, V th Is a threshold voltage, V th0 Is a critical threshold, V SB Is the voltage difference between the source of the turn-on switch and the substrate.
Equation (1) shows that the bootstrap circuit can stabilize the gate-source voltage of the switching tube to VDD without variation with the input signal. On one hand, the problem of weak driving capability under low power supply voltage is solved, and the nonlinear problem of on-resistance is also improved. However, in consideration of the body effect, as shown in equation (2), the threshold voltage Vth varies with the variation of the input signal Vin, resulting in nonlinear distortion of Ron magnitude dependent on Vin. The problem of nonlinear distortion caused by the body effect cannot be eliminated by the conventional bootstrap switch. And with the continuous development of the high-order process, the power supply voltage V DD Will be continuously reduced, V between the source and the substrate SB The more severe the effect of the nonlinear distortion is.
Disclosure of Invention
Aiming at the defects of the prior art, one of the purposes of the invention is to provide a bootstrap switching circuit which is used for solving the problem of nonlinearity caused by the body effect of an NMOS switching tube under the condition of low power supply voltage.
The invention comprises the following steps:
the bootstrap switching circuit comprises a first control module, a second control module and a conduction switching tube MP9, wherein the conduction switching tube MP9 adopts a PMOS tube, the first control module is connected with the second control module and used for controlling the second control module, the second control module is connected with a grid electrode of the conduction switching tube MP9 and used for controlling the conduction and the disconnection of the conduction switching tube MP9, a source electrode of the conduction switching tube MP9 is connected with an input signal Vin, and a drain electrode of the conduction switching tube MP9 is connected with an output signal Vout.
Preferably, the first control module includes first to fifth NMOS transistors, first to third PMOS transistors, and a first capacitor C1;
the grid electrode of the second NMOS tube MN2 is connected with the grid electrode of the third PMOS tube MP3 and is used for receiving a clock signal clk, the drain electrode of the second NMOS tube MN2 and the drain electrode of the third PMOS tube MP3 are respectively connected with the grid electrode of the second PMOS tube MP2 and the drain electrode of the third NMOS tube MN3 after being connected, the source electrode of the second NMOS tube MN2 is respectively connected with the negative electrode of the first capacitor C1, the drain electrode of the fourth NMOS tube MN4, the source electrode of the third NMOS tube MN3 and the source electrode of the fifth NMOS tube MN5, and the source electrode of the third PMOS tube MP3 is connected with the power supply VDD;
the grid electrode of the first NMOS tube MN1 is connected with a power supply VDD, the drain electrode of the first NMOS tube MN1 is used for receiving a clock delay signal clkbb, and the source electrode of the first NMOS tube MN1 is respectively connected with the grid electrode of the first PMOS tube MP1, the drain electrode of the second PMOS tube MP2, the grid electrode of the third NMOS tube MN3 and the grid electrode of the fifth NMOS tube MN5 and is used as a first output end of the first control module;
the drain electrode of the first PMOS tube MP1 is connected with a power supply VDD, the source electrode of the first PMOS tube MP1 is respectively connected with the source electrode of the second PMOS tube MP2 and the positive electrode of the first capacitor C1, the substrate of the first PMOS tube MP1 and the substrate of the second PMOS tube MP2 are respectively connected with the positive electrode of the first capacitor C1, and the positive electrode of the first capacitor C1 is used as the second output end of the first control module;
the gate of the fourth NMOS transistor MN4 is configured to receive the clock inversion signal clkb, the source of the fourth NMOS transistor MN4 is grounded, and the drain of the fifth NMOS transistor MN5 is connected to the input signal Vin.
Preferably, the second control module includes sixth to eighth NMOS transistors, fourth to eighth PMOS transistors, tenth PMOS transistor, second capacitor C2, and third capacitor C3;
the grid electrode of the sixth NMOS tube MN6 and the grid electrode of the seventh PMOS tube MP7 are respectively connected with a power supply VDD, the drain electrode of the sixth NMOS tube MN6 is used for receiving a clock inversion signal clkb, the source electrode of the sixth NMOS tube MN6 and the drain electrode of the seventh PMOS tube MP7 are respectively connected with the grid electrode of the sixth PMOS tube MP6, the drain electrode of the sixth PMOS tube MP6 is connected with the power supply VDD, the source electrode of the sixth PMOS tube MP6, the source electrode of the seventh PMOS tube MP7 and the source electrode of the eighth PMOS tube MP8 are respectively connected with the positive electrode of the third capacitor C3, the negative electrode of the third capacitor C3 is connected with the first input end of the second control module, the grid electrode of the eighth PMOS tube MP8 is connected with the power supply VDD, the drain electrode of the eighth PMOS tube MP8 is respectively connected with the negative electrode of the second capacitor C2 and the source electrode of the seventh NMOS tube MP7, and the substrate of the sixth PMOS tube MP6, the seventh PMOS tube MP7 and the eighth PMOS tube MP8 are respectively connected with the positive electrode of the third capacitor C3;
the positive electrode of the second capacitor C2 is respectively connected with the drain electrode of the fifth PMOS tube MP5 and the grid electrode of the on-switch tube MP9, the grid electrode of the fifth PMOS tube MP5 is grounded, the source electrode of the fifth PMOS tube MP5 is connected with the drain electrode of the fourth PMOS tube MP4, the grid electrode of the fourth PMOS tube MP4 is used for receiving the clock delay signal clkbb, and the source electrode of the fourth PMOS tube MP4 is connected with the power supply VDD;
the source electrode of the eighth NMOS tube MN8 is respectively connected with the drain electrode of the seventh NMOS tube MN7, the drain electrode of the tenth PMOS tube MP10 and the substrate of the on-switch tube MP9, the grid electrode of the eighth NMOS tube MN8 and the grid electrode of the seventh NMOS tube MN7 are respectively connected with the first output end and the second output end of the first control module, the drain electrode of the eighth NMOS tube MN8 is respectively connected with the source electrode of the on-switch tube MP9 and the input signal Vin, the grid electrode of the tenth PMOS tube MP10 is used for receiving the clock delay signal clkbb, and the source electrode of the tenth PMOS tube MP10 is connected with the power supply VDD.
Preferably, the second control module further includes a first inverter INV1 and a second inverter INV2 connected in sequence, an input end of the first inverter INV1 is configured to receive the clock signal clk, an output end of the first inverter INV1 is configured to output the clock inversion signal clkb, and an output end of the second inverter INV2 is configured to output the clock delay signal clkbb.
Preferably, the substrates of all NMOS transistors are grounded.
Preferably, all MOS tubes meet the standard CMOS process requirements.
The second objective of the present invention is to provide a control method of a bootstrap switching circuit, which is used for solving the problem of nonlinearity caused by the body effect of an NMOS switching tube under the condition of low power supply voltage.
The control method of the bootstrap switch circuit includes that when a clock signal clk=0, a first PMOS tube MP1, a third PMOS tube MP3, a fourth PMOS tube MP4, a fifth PMOS tube MP5, a seventh PMOS tube MP7, an eighth PMOS tube MP8, a tenth PMOS tube MP10, a first NMOS tube MN1 and a fourth NMOS tube MN4 are all conducted, a first capacitor C1 and a second capacitor C2 are in a precharge stage, a third capacitor C3 is in a bootstrap stage, and a conducting switch tube MP9 is in an off state;
when the clock signal clk=vdd, the second PMOS transistor MP2, the sixth PMOS transistor MP6, the second NMOS transistor MN2, the third NMOS transistor MN3, the fifth NMOS transistor MN5, the sixth NMOS transistor MN6, the seventh NMOS transistor MN7, and the eighth NMOS transistor MN8 are all turned on, the first capacitor C1 and the second capacitor C2 are in the bootstrap stage, the third capacitor C3 is in the precharge stage, and the turn-on switch transistor MP9 is in the on state.
Preferably, when the clock signal clk=0, the positive potential of the first capacitor C1 is charged to VDD, the negative potential of the first capacitor C1 is charged to 0, the negative potential of the third capacitor C3 is charged from 0 to VDD, the positive potential of the third capacitor C3 is bootstrapped from VDD to 2VDD, the negative potential of the second capacitor C2 is charged to 2VDD, the positive potential of the second capacitor C2 is charged to VDD, the substrate potential of the pass switch MP9 is VDD, and the substrate barrier of the pass switch MP9 is in a reverse bias state.
Preferably, when the clock signal clk=vdd, the negative potential of the first capacitor C1 is charged from 0 to Vin, the positive potential of the capacitor is bootstrapped to vin+vdd, the negative potential of the second capacitor C2 is discharged from 2VDD to Vin, the positive potential of the second capacitor C2 is bootstrapped to Vin-VDD, the negative potential of the third capacitor C3 is discharged from VDD to 0, the positive potential of the third capacitor C3 is discharged from 2VDD to VDD, and the source line voltage VSB of the on-switch MP9 is constant at 0.
The beneficial effects of the invention are as follows: the PMOS is adopted as the on-switch tube, so that nonlinear distortion caused by a body effect can be completely eliminated, and the total harmonic distortion can reach-110 db; the control method adopted by the invention can ensure that the withstand voltage of all MOS tubes meets the requirements of corresponding process, the voltage differences of the gate-source voltage VGS, the gate-drain voltage VGD and the source-drain voltage VSD of all the MOS tubes are all in the range of-VDD to VDD, and the parasitic diodes of all the MOS tubes are kept in the reverse bias state, so that the situation of larger electric leakage does not exist, the safety and reliability of the circuit are ensured, and the service life is longer.
Drawings
FIG. 1 is a diagram of a prior art bootstrap switch circuit;
FIG. 2 is a schematic diagram of a bootstrap switch circuit in accordance with an embodiment of the present invention;
fig. 3 is a schematic diagram of a bootstrap switch circuit when clock signal clk=0 according to an embodiment of the present invention;
fig. 4 is a schematic diagram of a bootstrap switch circuit when clock signal clk=vdd according to an embodiment of the present invention.
Detailed Description
The foregoing description is only an overview of the present invention, and is intended to be implemented in accordance with the teachings of the present invention, as well as the preferred embodiments thereof, together with the following detailed description of the invention, given by way of illustration only, together with the accompanying drawings.
Referring to fig. 2, the bootstrap switching circuit disclosed in this embodiment includes a first control module 1, a second control module 2 and a turn-on switching tube MP9, where the turn-on switching tube MP9 adopts a PMOS tube, so that nonlinear distortion caused by a body effect can be completely eliminated, and total harmonic distortion can reach-110 db. The first control module 1 is connected with the second control module 2 and is used for controlling the second control module 2, the second control module 2 is connected with the grid electrode of the conduction switch tube MP9 and is used for controlling the conduction and the disconnection of the conduction switch tube MP9, the source electrode of the conduction switch tube MP9 is connected with an input signal Vin, and the drain electrode of the conduction switch tube MP9 is connected with an output signal Vout.
The first control module 1 comprises first to fifth NMOS tubes, first to third PMOS tubes and a first capacitor C1;
the grid electrode of the second NMOS tube MN2 is connected with the grid electrode of the third PMOS tube MP3 and is used for receiving a clock signal clk, the drain electrode of the second NMOS tube MN2 and the drain electrode of the third PMOS tube MP3 are respectively connected with the grid electrode of the second PMOS tube MP2 and the drain electrode of the third NMOS tube MN3 after being connected, the source electrode of the second NMOS tube MN2 is respectively connected with the negative electrode of the first capacitor C1, the drain electrode of the fourth NMOS tube MN4, the source electrode of the third NMOS tube MN3 and the source electrode of the fifth NMOS tube MN5, and the source electrode of the third PMOS tube MP3 is connected with the power supply VDD;
the grid electrode of the first NMOS tube MN1 is connected with a power supply VDD, the drain electrode of the first NMOS tube MN1 is used for receiving a clock delay signal clkbb, and the source electrode of the first NMOS tube MN1 is respectively connected with the grid electrode of the first PMOS tube MP1, the drain electrode of the second PMOS tube MP2, the grid electrode of the third NMOS tube MN3 and the grid electrode of the fifth NMOS tube MN5 and is used as a first output end of the first control module 1;
the drain electrode of the first PMOS tube MP1 is connected with a power supply VDD, the source electrode of the first PMOS tube MP1 is respectively connected with the source electrode of the second PMOS tube MP2 and the positive electrode of the first capacitor C1, the substrate of the first PMOS tube MP1 and the substrate of the second PMOS tube MP2 are respectively connected with the positive electrode of the first capacitor C1, and the positive electrode of the first capacitor C1 is used as the second output end of the first control module 1;
the gate of the fourth NMOS transistor MN4 is configured to receive the clock inversion signal clkb, the source of the fourth NMOS transistor MN4 is grounded, and the drain of the fifth NMOS transistor MN5 is connected to the input signal Vin.
The second control module 2 comprises sixth to eighth NMOS (N-channel metal oxide semiconductor) tubes, fourth to eighth PMOS tubes, tenth PMOS tube, a second capacitor C2 and a third capacitor C3;
the grid electrode of the sixth NMOS tube MN6 and the grid electrode of the seventh PMOS tube MP7 are respectively connected with a power supply VDD, the drain electrode of the sixth NMOS tube MN6 is used for receiving a clock inversion signal clkb, the source electrode of the sixth NMOS tube MN6 and the drain electrode of the seventh PMOS tube MP7 are respectively connected with the grid electrode of the sixth PMOS tube MP6, the drain electrode of the sixth PMOS tube MP6 is connected with the power supply VDD, the source electrode of the sixth PMOS tube MP6, the source electrode of the seventh PMOS tube MP7 and the source electrode of the eighth PMOS tube MP8 are respectively connected with the positive electrode of the third capacitor C3, the negative electrode of the third capacitor C3 is connected with the first input end of the second control module 2, the grid electrode of the eighth PMOS tube MP8 is connected with the power supply VDD, the drain electrode of the eighth PMOS tube MP8 is respectively connected with the negative electrode of the second capacitor C2 and the source electrode of the seventh NMOS tube MP7, and the substrate of the seventh PMOS tube MP7 and the eighth PMOS tube MP8 are respectively connected with the positive electrode of the third capacitor C3;
the positive electrode of the second capacitor C2 is respectively connected with the drain electrode of the fifth PMOS tube MP5 and the grid electrode of the on-switch tube MP9, the grid electrode of the fifth PMOS tube MP5 is grounded, the source electrode of the fifth PMOS tube MP5 is connected with the drain electrode of the fourth PMOS tube MP4, the grid electrode of the fourth PMOS tube MP4 is used for receiving a clock delay signal clkbb, and the source electrode of the fourth PMOS tube MP4 is connected with a power supply VDD;
the source electrode of the eighth NMOS tube MN8 is respectively connected with the drain electrode of the seventh NMOS tube MN7, the drain electrode of the tenth PMOS tube MP10 and the substrate of the conduction switch tube MP9, the grid electrode of the eighth NMOS tube MN8 and the grid electrode of the seventh NMOS tube MN7 are respectively connected with the first output end and the second output end of the first control module 1, the drain electrode of the eighth NMOS tube MN8 is respectively connected with the source electrode of the conduction tube MP9 and the input signal Vin, the grid electrode of the tenth PMOS tube MP10 is used for receiving the clock delay signal clkbb, and the source electrode of the tenth PMOS tube MP10 is connected with the power supply VDD.
The second control module 2 further comprises a first inverter INV1 and a second inverter INV2 which are sequentially connected, wherein the input end of the first inverter INV1 is used for receiving the clock signal clk, the output end of the first inverter INV1 is used for outputting the clock inversion signal clkb, and the output end of the second inverter INV2 is used for outputting the clock delay signal clkbb, and the first inverter INV1 and the second inverter INV2 share one clock signal input end, so that circuit wiring is facilitated, and the degree of a circuit is reduced.
The substrates of all the NMOS transistors in the embodiment are grounded, and all the MOS transistors meet the standard CMOS process requirements, but are not limited to the standard CMOS process requirements, and are also suitable for other special processes, such as Deep Nwell (Deep Nwell) process, double-well process, etc., and the circuit of the embodiment is suitable for low-voltage and ultra-low-voltage application scenarios, and can make the on-resistance of the switch smaller and the linearity higher.
The working principle of this embodiment is as follows:
referring to fig. 3, when the clock signal clk=0, the first PMOS transistor MP1 and the fourth PMOS transistor MN4 are both turned on, the potential of the positive electrode of the first capacitor C1 is charged to VDD, the potential of the negative electrode of the first capacitor C1 is charged to 0, and the positive-negative voltage difference of the first capacitor C1 is VDD. The third PMOS tube MP3 is conducted so that the grid potential of the second PMOS tube MP2 is VDD, and the second PMOS tube MP2 is turned off. The first NMOS transistor MN1 is turned on to cause the gate potentials of the third NMOS transistor MN3, the fifth NMOS transistor MN5, and the eighth NMOS transistor MN8 to be 0, so that the third NMOS transistor MN3, the fifth NMOS transistor MN5, and the eighth NMOS transistor MN8 are turned off. The negative electrode potential of the third capacitor C3 is charged from 0 to VDD, the positive electrode potential of the third capacitor 3 is bootstrapped from VDD to 2VDD, and the positive-negative voltage difference of the third capacitor C3 is VDD. Because of the bootstrap of the third capacitor C3, the sixth NMOS transistor MN6 is turned off and the seventh PMOS transistor MP7 is turned on, so that the gate potential of the sixth PMOS transistor MP6 is 2VDD, and the sixth PMOS transistor MP6 is turned off. As the substrates of the sixth PMOS tube MP6, the seventh PMOS tube MP7 and the eighth PMOS tube MP8 are connected to the positive electrode of the third capacitor C3, the parasitic diodes of the sixth PMOS tube MP6, the seventh PMOS tube MP7 and the eighth PMOS tube MP8 are in the reverse bias state. The bootstrap of the third capacitor C3 enables the eighth PMOS tube MP8 to be conducted, so that the negative potential of the second capacitor C2 is charged to 2VDD, the fourth PMOS tube MP4 and the fifth PMOS tube MP5 are conducted to charge the positive potential of the second capacitor C2 to VDD, and the positive-negative voltage difference of the second capacitor C2 is-VDD. At this time, the gate-source potential vgs= -VDD of the seventh NMOS transistor MN7, the seventh NMOS transistor MN7 is in the off state. The gate-source potential vgs= -VDD of the eighth NMOS transistor MN8, the eighth NMOS transistor MN8 being in the off state. The gate-source potential vgs=vdd-Vin of the on-switch tube MP9, because the input signal Vin is an analog signal with swing less than VDD, the on-switch tube MP9 is turned off, the input signal Vin cannot be transmitted to Vout, and meanwhile, the substrate potential of the on-switch tube MP9 is VDD, so that the substrate potential barrier of the on-switch tube MP9 is guaranteed to be in a reverse bias state.
As described above, when clk=0, the on-switch tube MP9 is turned off, the first capacitor C1 and the second capacitor C2 are in the precharge phase, the third capacitor C3 is in the bootstrap phase, and the withstand voltages of all MOS tubes meet |vgs|vdd, |vgd|vdd, and |vds|vdd, where VGS is the gate-source voltage of the MOS tube, VGD is the gate-drain voltage of the MOS tube, and VDS is the drain-source voltage of the MOS tube.
Referring to fig. 4, when the clock signal clk=vdd, the sixth PMOS transistor MP6 is turned on, the positive potential of the third capacitor C3 is charged to VDD, and the negative potential is discharged to 0, so that the seventh PMOS transistor MP7 and the eighth PMOS transistor MP8 are turned off. Because clk=vdd, the third PMOS transistor MP3 and the fourth PMOS transistor MN4 are turned off, and the fifth NMOS transistor MN5 is turned on weakly at the beginning, so that the negative potential of the first capacitor C1 increases, and at the same time, the positive potential of the first capacitor C1 increases from VDD. The weak conduction of the second NMOS transistor MN2 enables the second PMOS transistor MP2 to be turned on, so that the gate voltage of the fifth NMOS transistor MN5 becomes larger, the negative electrode of the first capacitor C1 is charged more, and the gate voltage of the fifth NMOS transistor MN5 is increased until the voltage reaches vin+vdd, so that the input signal Vin can charge the negative electrode potential of the first capacitor C1 to Vin without threshold loss. During this period, the eighth NMOS transistor MN8 and the seventh NMOS transistor MN7 are turned on in order, and the input signal Vin similarly charges the negative electrode potential of the second capacitor C2 to Vin without a threshold loss. At this time, the fourth PMOS transistor MP4 and the fifth PMOS transistor MP5 are in an off state, and the positive electrode of the second capacitor C2 has no bleed-off path, so that the positive electrode potential of the second capacitor C2 can be bootstrapped to Vin-VDD, and the positive-negative voltage difference of the second capacitor C2 remains unchanged. At this time, the gate-source voltage vgs= (Vin-VDD) -vin= -VDD of the ninth PMOS transistor MP9, thereby realizing the conduction of the conduction switch MP9, and the gate-source voltage VGS of the conduction switch MP9 does not change with the change of Vin. Meanwhile, the substrate of the on-switch tube MP9 is connected with the input signal Vin through the eighth NMOS tube MN8 without threshold loss, so that the source lining voltage VSB=0 of the on-switch tube MP9 completely eliminates nonlinear distortion caused by the body effect, and the resistance of the on-switch tube MP9 has higher linearity.
As described above, when clk=vdd, the on-switch MP9 is turned on, both the first capacitor C1 and the second capacitor C2 are in the bootstrap phase, and the third capacitor C3 is in the precharge phase. The withstand voltage of all the MOS tubes meets the requirements of |VGS| not more than VDD, |VGD| not more than VDD and|VDS| not more than VDD, wherein VGS is the gate-source voltage of the MOS tube, VGD is the gate-drain voltage of the MOS tube, and VDS is the drain-source voltage of the MOS tube.
The embodiment also discloses a control method of the bootstrap switch circuit, wherein the implementation circuit is the circuit, when the clock signal clk=0, the first PMOS transistor MP1, the third PMOS transistor MP3, the fourth PMOS transistor MP4, the fifth PMOS transistor MP5, the seventh PMOS transistor MP7, the eighth PMOS transistor MP8, the tenth PMOS transistor MP10, the first NMOS transistor MN1 and the fourth NMOS transistor MN4 are all conducted, the first capacitor C1 and the second capacitor C2 are in the precharge phase, the third capacitor C3 is in the bootstrap phase, and the conduction switch transistor MP9 is in the off state;
when the clock signal clk=vdd, the second PMOS transistor MP2, the sixth PMOS transistor MP6, the second NMOS transistor MN2, the third NMOS transistor MN3, the fifth NMOS transistor MN5, the sixth NMOS transistor MN6, the seventh NMOS transistor MN7, and the eighth NMOS transistor MN8 are all turned on, the first capacitor C1 and the second capacitor C2 are in the bootstrap stage, the third capacitor C3 is in the precharge stage, and the turn-on switch transistor MP9 is in the on state.
Specifically, when the clock signal clk=0, the positive potential of the first capacitor C1 is charged to VDD, the negative potential of the first capacitor C1 is charged to 0, the negative potential of the third capacitor C3 is charged from 0 to VDD, the positive potential of the third capacitor C3 is bootstrapped from VDD to 2VDD, the negative potential of the second capacitor C2 is charged to 2VDD, the positive potential of the second capacitor C2 is charged to VDD, the substrate potential of the pass switch MP9 is VDD, and the substrate barrier of the pass switch MP9 is in a reverse bias state.
Specifically, when the clock signal clk=vdd, the negative potential of the first capacitor C1 is charged from 0 to Vin, the positive potential of the capacitor is bootstrapped to vin+vdd, the negative potential of the second capacitor C2 is discharged from 2VDD to Vin, the positive potential of the second capacitor C2 is bootstrapped to Vin-VDD, the negative potential of the third capacitor C3 is discharged from VDD to 0, the positive potential of the third capacitor C3 is discharged from 2VDD to VDD, and the source line voltage VSB of the on-switch MP9 is constant at 0.
The control method adopted by the embodiment can ensure that the withstand voltage of all MOS tubes meets the corresponding process requirements, the voltage differences of the gate-source voltage VGS, the gate-drain voltage VGD and the source-drain voltage VDS of all the MOS tubes are all in the range of-VDD to VDD, parasitic diodes of all the MOS tubes are kept in a reverse bias state, no larger leakage condition exists, the safety and reliability of the circuit are ensured, and the service life is longer.
The present invention is not limited to the above embodiments, but is merely preferred embodiments of the present invention, and the present invention should be construed as being limited to the above embodiments as long as the technical effects of the present invention are achieved by the same means. Various modifications and variations are possible in the technical solution and/or in the embodiments within the scope of the invention.

Claims (6)

1. A bootstrap switching circuit, characterized by: the control circuit comprises a first control module (1), a second control module (2) and a conduction switch tube MP9, wherein the conduction switch tube MP9 adopts a PMOS tube, the first control module (1) is connected with the second control module (2) and is used for controlling the second control module (2), the second control module (2) is connected with a grid electrode of the conduction switch tube MP9 and is used for controlling the conduction and the disconnection of the conduction switch tube MP9, a source electrode of the conduction switch tube MP9 is connected with an input signal Vin, and a drain electrode of the conduction switch tube MP9 is connected with an output signal Vout;
the first control module (1) comprises first to fifth NMOS (N-channel metal oxide semiconductor) tubes, first to third PMOS (P-channel metal oxide semiconductor) tubes and a first capacitor C1; the grid electrode of the second NMOS tube MN2 is connected with the grid electrode of the third PMOS tube MP3 and is used for receiving a clock signal clk, the drain electrode of the second NMOS tube MN2 and the drain electrode of the third PMOS tube MP3 are respectively connected with the grid electrode of the second PMOS tube MP2 and the drain electrode of the third NMOS tube MN3 after being connected, the source electrode of the second NMOS tube MN2 is respectively connected with the negative electrode of the first capacitor C1, the drain electrode of the fourth NMOS tube MN4, the source electrode of the third NMOS tube MN3 and the source electrode of the fifth NMOS tube MN5, and the source electrode of the third PMOS tube MP3 is connected with the power supply VDD; the grid electrode of the first NMOS tube MN1 is connected with a power supply VDD, the drain electrode of the first NMOS tube MN1 is used for receiving a clock delay signal clkbb, and the source electrode of the first NMOS tube MN1 is respectively connected with the grid electrode of the first PMOS tube MP1, the drain electrode of the second PMOS tube MP2, the grid electrode of the third NMOS tube MN3 and the grid electrode of the fifth NMOS tube MN5 and is used as a first output end of the first control module (1); the drain electrode of the first PMOS tube MP1 is connected with a power supply VDD, the source electrode of the first PMOS tube MP1 is respectively connected with the source electrode of the second PMOS tube MP2 and the positive electrode of the first capacitor C1, the substrate of the first PMOS tube MP1 and the substrate of the second PMOS tube MP2 are respectively connected with the positive electrode of the first capacitor C1, and the positive electrode of the first capacitor C1 is used as the second output end of the first control module (1); the grid electrode of the fourth NMOS tube MN4 is used for receiving a clock inversion signal clkb, the source electrode of the fourth NMOS tube MN4 is grounded, and the drain electrode of the fifth NMOS tube MN5 is connected with an input signal Vin;
the second control module (2) comprises sixth to eighth NMOS (N-channel metal oxide semiconductor) tubes, fourth to eighth PMOS tubes, tenth PMOS tubes, a second capacitor C2 and a third capacitor C3; the grid electrode of the sixth NMOS tube MN6 and the grid electrode of the seventh PMOS tube MP7 are respectively connected with a power supply VDD, the drain electrode of the sixth NMOS tube MN6 is used for receiving a clock inversion signal clkb, the source electrode of the sixth NMOS tube MN6 and the drain electrode of the seventh PMOS tube MP7 are respectively connected with the grid electrode of the sixth PMOS tube MP6, the drain electrode of the sixth PMOS tube MP6 is connected with the power supply VDD, the source electrode of the sixth PMOS tube MP6, the source electrode of the seventh PMOS tube MP7 and the source electrode of the eighth PMOS tube MP8 are respectively connected with the positive electrode of the third capacitor C3, the negative electrode of the third capacitor C3 is connected with the first input end of the second control module (2), the grid electrode of the eighth PMOS tube MP8 is connected with the power supply VDD, the drain electrode of the eighth PMOS tube MP8 is respectively connected with the negative electrode of the second capacitor C2 and the source electrode of the seventh NMOS tube MP7, and the substrates of the sixth PMOS tube MP6, the seventh PMOS tube MP7 and the eighth PMOS tube MP8 are respectively connected with the positive electrode of the third capacitor C3; the positive electrode of the second capacitor C2 is respectively connected with the drain electrode of the fifth PMOS tube MP5 and the grid electrode of the on-switch tube MP9, the grid electrode of the fifth PMOS tube MP5 is grounded, the source electrode of the fifth PMOS tube MP5 is connected with the drain electrode of the fourth PMOS tube MP4, the grid electrode of the fourth PMOS tube MP4 is used for receiving the clock delay signal clkbb, and the source electrode of the fourth PMOS tube MP4 is connected with the power supply VDD; the source electrode of the eighth NMOS tube MN8 is respectively connected with the drain electrode of the seventh NMOS tube MN7, the drain electrode of the tenth PMOS tube MP10 and the substrate of the conduction switch tube MP9, the grid electrode of the eighth NMOS tube MN8 and the grid electrode of the seventh NMOS tube MN7 are respectively connected with the first output end and the second output end of the first control module (1), the drain electrode of the eighth NMOS tube MN8 is respectively connected with the source electrode of the conduction switch tube MP9 and the input signal Vin, the grid electrode of the tenth PMOS tube MP10 is used for receiving a clock delay signal clkbb, and the source electrode of the tenth PMOS tube MP10 is connected with a power supply VDD;
the second control module (2) further comprises a first inverter INV1 and a second inverter INV2 which are sequentially connected, wherein the input end of the first inverter INV1 is used for receiving the clock signal clk, the output end of the first inverter INV1 is used for outputting the clock inversion signal clkb, and the output end of the second inverter INV2 is used for outputting the clock delay signal clkbb.
2. The bootstrapped switch circuit of claim 1, wherein: all substrates of the NMOS transistors are grounded.
3. The bootstrapped switch circuit of claim 1, wherein: all MOS tubes meet the requirements of standard CMOS technology.
4. A method of controlling a bootstrap switching circuit as defined in any one of claims 1-3, characterized in that: when the clock signal clk=0, the first PMOS transistor MP1, the third PMOS transistor MP3, the fourth PMOS transistor MP4, the fifth PMOS transistor MP5, the seventh PMOS transistor MP7, the eighth PMOS transistor MP8, the tenth PMOS transistor MP10, the first NMOS transistor MN1 and the fourth NMOS transistor MN4 are all turned on, the first capacitor C1 and the second capacitor C2 are in the precharge phase, the third capacitor C3 is in the bootstrap phase, and the on-switch transistor MP9 is in the off state;
when the clock signal clk=vdd, the second PMOS transistor MP2, the sixth PMOS transistor MP6, the second NMOS transistor MN2, the third NMOS transistor MN3, the fifth NMOS transistor MN5, the sixth NMOS transistor MN6, the seventh NMOS transistor MN7, and the eighth NMOS transistor MN8 are all turned on, the first capacitor C1 and the second capacitor C2 are in the bootstrap stage, the third capacitor C3 is in the precharge stage, and the turn-on switch transistor MP9 is in the on state.
5. The method for controlling a bootstrap switching circuit as defined in claim 4, characterized in that: when the clock signal clk=0, the positive potential of the first capacitor C1 is charged to VDD, the negative potential of the first capacitor C1 is charged to 0, the negative potential of the third capacitor C3 is charged from 0 to VDD, the positive potential of the third capacitor C3 is bootstrapped from VDD to 2VDD, the negative potential of the second capacitor C2 is charged to 2VDD, the positive potential of the second capacitor C2 is charged to VDD, the substrate potential of the turn-on switch MP9 is VDD, and the substrate barrier of the turn-on switch MP9 is in a reverse bias state.
6. The method for controlling a bootstrap switching circuit as defined in claim 5, characterized in that: when the clock signal clk=vdd, the negative potential of the first capacitor C1 is charged from 0 to Vin, the positive potential of the capacitor is bootstrapped to vin+vdd, the negative potential of the second capacitor C2 is discharged from 2VDD to Vin, the positive potential of the second capacitor C2 is bootstrapped to Vin-VDD, the negative potential of the third capacitor C3 is discharged from VDD to 0, the positive potential of the third capacitor C3 is discharged from 2VDD to VDD, and the source liner voltage VSB of the turn-on switching tube MP9 is constant at 0.
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