CN108155899A - A kind of boot-strapped switch circuit - Google Patents
A kind of boot-strapped switch circuit Download PDFInfo
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- CN108155899A CN108155899A CN201711417126.9A CN201711417126A CN108155899A CN 108155899 A CN108155899 A CN 108155899A CN 201711417126 A CN201711417126 A CN 201711417126A CN 108155899 A CN108155899 A CN 108155899A
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- grid
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- pmos
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
- H03K17/51—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used
- H03K17/56—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices
- H03K17/687—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices the devices being field-effect transistors
Abstract
A kind of boot-strapped switch circuit, belongs to field of analog integrated circuit.Charge pump circuit is used to make its amount of charge stored constant for the 5th capacitance and the 6th capacitor charging, grid voltage, which promotes circuit and grid voltage, reduces circuit for changing the grid end voltage of NMOS switch pipe and PMOS switch pipe to realize its gate source voltage as steady state value, and switching circuit is used to control the charging of charge pump circuit and grid voltage promotes circuit and grid voltage and reduces the opening and closing of circuit.Input signal is connected to output by the present invention simultaneously using NMOS switch pipe and PMOS switch pipe, reduces the conducting resistance of switch；By using NMOS switch pipe and the mode of PMOS switch pipe parallel connection so that NMOS switch pipe and PMOS switch pipe the channel charge injection effect caused by clock changes offset each other, and clock feed-through effect also offsets each other, so as to improve the linearity of switch；It charges by using diode pair capacitance, making circuit, there is no overvoltage devices, improve the reliability of circuit.
Description
Technical field
The invention belongs to analogue layout fields, and in particular to a kind of boot-strapped switch circuit.
Background technology
With the continuous improvement that the continuous development and people of modern communications technology require communication speed, in communication system
The frequency of analog signal is continuously improved in system, and the requirement for converting analog signals into digital signal is continuously improved, also will modulus
Number converter will have the higher linearity when being sampled to analog signal, this just needs to use Bootstrap circuit.
Traditional boot-strapped switch circuit structure is as shown in Figure 1, by main switch MsIt is formed with Bootstrap circuit,
Middle Bootstrap circuit includes capacitance C7~C8With MOS transistor M1~M11.Its operation principle is：
(1) phase is turned off：When CLK is low level, and CLKB is high level, M3Conducting, C7Bottom crown is connected to ground, C8Upper pole
Plate voltage is 2 times of supply voltage VDD, makes M2Conducting, makes C7In store C7The electricity of × VDD；M6Shutdown, M5By M4Grid connect
Supply voltage VDD is connected to, makes M4Shutdown；CLKB is high level, makes M11Shutdown, M10Conducting, by M9Source electrode is connected to the ground, and makes M9It leads
It is logical, by main switch MsGrid be connected to the ground, then M7~M9And MsShutdown.
(2) phase is connected：When CLK is converted to high level, and CLKB is low level, M3Shutdown, M1Conducting, makes C8Store C8×
The electricity of VDD；CLKB is low level, makes M10Shutdown, M11Conducting, by M9Source electrode is connected to supply voltage VDD, makes M9Shutdown；CLK
High level is converted to, makes M5Shutdown, M6Conducting, by M4Grid drag down, then M4Conducting, and then make M8Conducting, input signal are passed through
M8It is connected to C7Bottom crown, due to capacitance C7The charge of upper storage does not have discharge loop in clock CLK transfer processes, is stored in electricity
Hold C7On charge remain unchanged, then capacitance C7The voltage of top crown will synchronize rising, until its value is equal to Vin+ VDD, at this time
Main switch MsGrid end voltage VD=Vin+ VDD, then main switch MsGate source voltage VGSFor：
VGS=VD-Vin=Vin+VDD-Vin=VDD
The conducting resistance of main switch is：
Wherein, μ is carrier mobility, CoxFor main switch unit area gate capacitance,For main switch MsWidth it is long
Than VGSFor main switch MsGate source voltage, VthFor main switch MsOn state threshold voltage.
Utilize Bootstrap circuit so that gate source voltage is equal to supply voltage VDD when main switch is connected, so as to keep leading
The resistance that is powered is invariable, you can realizes output signal VoutTo input signal VinRealize the tracking of high linearity.
But in traditional Bootstrap circuit, M2In shutdown mutually in overvoltage condition, the reliability of circuit can be caused to ask
Topic reduces the service life of circuit；Generally in order to realize the quick sampling to high speed signal, it is desirable that the conducting resistance of main switch is very
Low, this results in its size very big so that the channel charge injection effect and clock feed-through effect of main switch become serious, cause
The linearity of main switch sampling is lower.
Invention content
It supports against the above deficiency, the present invention provides a kind of boot-strapped switch circuit, main switch is opened for CMOS
Guan Guan can effectively improve its linearity, improve the reliability of chip, while reduce conducting resistance.
Technical scheme is as follows：
A kind of boot-strapped switch circuit, including NMOS main switches MnWith PMOS main switches MpAnd it is opened with NMOS master
Close pipe MnFirst charge pump circuit of connection, grid voltage promote circuit and first switch circuit, with PMOS main switches MpThe of connection
Two charge pump circuits, grid voltage reduce circuit and second switch circuit,
NMOS main switches MnSource electrode connection PMOS main switches MpSource electrode and be used as the boot-strapped switch circuit
Input terminal, drain electrode connection PMOS main switches MpDrain electrode and as the output terminal of the boot-strapped switch circuit；
First charge pump circuit includes the first NMOS tube MN1, the second NMOS tube MN2, the first capacitance C1, the second capacitance
C2 and the first diode D1,
The grid of first NMOS tube MN1 connects the source electrode of the second NMOS tube MN2 and the anode of the first diode D1 and passes through
Inverting clock signal CLKB is connected after second capacitance C2, source electrode connects the grid of the second NMOS tube MN2 and passes through the first capacitance
Clock signal clk is connected after C1, the drain electrode of the second NMOS tube MN2 of drain electrode connection simultaneously connects supply voltage；First diode D1
Output terminal of the cathode as first charge pump circuit；
Second charge pump circuit includes the first PMOS tube MP1, the second PMOS tube MP2, third capacitance C3, the 4th capacitance
C4 and the second diode D2,
The grid of first PMOS tube MP1 connects the source electrode of the second PMOS tube MP2 and connects reverse phase after passing through third capacitance C3
Clock signal clk B, source electrode connect the grid of the second PMOS tube MP2 and the cathode of the second diode D2 and pass through the 4th capacitance
Clock signal clk, the drain electrode of the second PMOS tube MP2 of drain electrode connection and ground connection are connected after C4；The anode of second diode D2 is made
Output terminal for second charge pump circuit；
The grid voltage promotes circuit and includes third NMOS tube MN3, the 4th NMOSMN4, the 5th PMOS tube MP5 and the 6th capacitance
C6,
The grid of 4th NMOS tube MN4 connects the NMOS main switches MnGrid, third NMOS tube MN3 grid and
The drain electrode of 5th PMOS tube MP5, source electrode connect the input terminal of the boot-strapped switch circuit, the 3rd NMOS of drain electrode connection
The source electrode of pipe MN3 simultaneously passes through the defeated of the source electrode of the 5th PMOS tube MP5 of connection and first charge pump circuit after the 6th capacitance C6
Outlet；The grid of 5th PMOS tube MP5 connects the first switch circuit；
The grid voltage reduces circuit and includes third PMOS tube MP3, the 4th PMOS tube MP4, the electricity of the 5th NMOS tube MN5 and the 5th
Hold C5,
The grid of 4th PMOS tube MP4 connects the PMOS main switches MpGrid, third PMOS tube MP3 grid and
The drain electrode of 5th NMOS tube MN5, source electrode connect the input terminal of the boot-strapped switch circuit, the 3rd PMOS of drain electrode connection
The source electrode of pipe MP3 and the grid voltage promote the drain electrode of third NMOS tube MN3 in circuit and connect the 5th after passing through the 5th capacitance C5
The output terminal of the source electrode of NMOS tube MN5 and second charge pump circuit；The grid connection described second of 5th NMOS tube MN5 is opened
Powered-down road；The drain electrode of third PMOS tube MP3 connects the source electrode that the grid voltage promotes third NMOS tube MN3 in circuit；
The first switch circuit generates timing control signal control according to clock signal clk and inverting clock signal CLKB
The grid voltage promotes circuit；
The second switch circuit generates timing control signal control according to clock signal clk and inverting clock signal CLKB
The grid voltage reduces circuit.
Specifically, the first switch circuit include the 6th NMOS tube MN6, the 7th NMOS tube MN7, the 8th NMOS tube MN8,
9th NMOS tube MN9, the tenth NMOS tube MN10, the 11st PMOS tube MP11 and the 12nd PMOS tube MP12,
The grid connection inverting clock signal CLKB of 6th NMOS tube MN6, source electrode ground connection, the 7th NMOS of drain electrode connection
The source electrode of pipe MN7 and the 8th NMOS tube MN8 and the grid voltage promote the drain electrode of the 4th NMOS tube MN4 in circuit；
The grid of 11st PMOS tube MP11 connects the grid and clock signal clk of the 7th NMOS tube MN7, and source electrode connects electricity
Source voltage, the drain electrode of drain electrode connection the 7th NMOS tube MN7 and the 8th NMOS tube MN8 and the grid voltage are promoted the 5th in circuit
The grid of PMOS tube MP5；
The grid connection supply voltage of 9th NMOS tube MN9, the grid and the grid of the 8th NMOS tube MN8 of drain electrode connection
Pressure promotes the drain electrode of the 5th PMOS tube MP5 in circuit, and source electrode connects the tenth NMOS tube MN10 pipes and the 12nd PMOS tube MP12
Drain electrode；
The source electrode connection supply voltage of 12nd PMOS tube MP12, grid connect the grid of the tenth NMOS tube MN10 and company
The source electrode ground connection of reversed clock signal CLKB, the tenth NMOS tube MN10；
The second switch circuit includes the 6th PMOS tube MP6, the 7th PMOS tube MP7, the 8th PMOS tube MP8, the 9th
PMOS tube MP9, the tenth PMOS tube MP10, the 11st NMOS tube MN11 and the 12nd NMOS tube MN12,
The grid connection clock signal clk of 6th PMOS tube MP6, source electrode ground connection, the 7th PMOS tube MP7 of drain electrode connection
The drain electrode of the 4th PMOS tube MP4 in circuit is reduced with the source electrode of the 8th PMOS tube MP8 and the grid voltage；
The grid connection grid of the 7th PMOS tube MP7 and inverting clock signal CLKB of 11st NMOS tube MN11, source
Pole is grounded, and the drain electrode of drain electrode connection the 7th PMOS tube MP7 and the 8th PMOS tube MP8 and the grid voltage are reduced the 5th in circuit
The grid of NMOS tube MN5；
The grounded-grid of 9th PMOS tube MP9, the grid of the 8th PMOS tube MP8 of drain electrode connection and the grid voltage reduce electricity
The drain electrode of five NMOS tube MN5 of Lu Zhong, source electrode connect the tenth PMOS tube MP10 pipes and the drain electrode of the 12nd NMOS tube MN12；
The source electrode ground connection of 12nd NMOS tube MN12, grid connect the grid of the tenth PMOS tube MP10 and connect clock letter
Number CLK, the source electrode of the tenth PMOS tube MP10 connect supply voltage.
Beneficial effects of the present invention are：
1st, the present invention realizes Bootstrap, makes NMOS main switches MnWith PMOS main switches MpGrid source in conducting
Voltage is fixed value, and NMOS main switches MnWith PMOS main switches MpInput signal is connected to output simultaneously, is reduced
The conducting resistance of switch.
2nd, the present invention is by using NMOS main switches MnWith PMOS main switches MpMode in parallel so that NMOS master opens
Close pipe MnWith PMOS main switches MpChannel charge injection effect offsets each other caused by clock changes, clock feed-through effect
Also it offsets each other, so as to improve the linearity of switch.
3rd, the present invention charges by using diode pair capacitance, and making circuit, there is no overvoltage devices, improve circuit
Reliability.
Description of the drawings
Fig. 1 is the structure diagram of boot-strapped switch circuit in the prior art.
Fig. 2 is a kind of a kind of way of realization of boot-strapped switch circuit provided by the invention.
Specific embodiment
In the following with reference to the drawings and specific embodiments, technical scheme of the present invention is described in detail.
As shown in Fig. 2, a kind of boot-strapped switch circuit provided by the invention includes NMOS main switches MnWith PMOS master
Switching tube MpAnd with NMOS main switches MnFirst charge pump circuit of connection, grid voltage promote circuit and first switch circuit,
With PMOS main switches MpSecond charge pump circuit of connection, grid voltage reduce circuit and second switch circuit, NMOS main switches Mn
Source electrode connection PMOS main switches MpSource electrode and as the boot-strapped switch circuit input terminal connect input signal
Vin, drain electrode connection PMOS main switches MpDrain electrode and as the boot-strapped switch circuit output terminal connection output letter
Number Vout, input signal VinPromoting circuit and grid voltage by grid voltage reduces circuit and is connected to NMOS main switches MnIt is opened with PMOS master
Close pipe MpGrid；NMOS main switches MnGrid be node A, PMOS main switch MpGrid be node B.
Connect NMOS main switches MnThe first charge pump circuit include the first NMOS tube MN1, the second NMOS tube MN2, the
The grid of one capacitance C1, the second capacitance C2 and the first diode D1, the first NMOS tube MN1 connect the source electrode of the second NMOS tube MN2
Inverting clock signal CLKB is connected with the anode of the first diode D1 and after passing through the second capacitance C2, source electrode connects the 2nd NMOS
The grid of pipe MN2 simultaneously passes through clock signal clk is connected after the first capacitance C1, and the drain electrode of the second NMOS tube MN2 of drain electrode connection is simultaneously
Connect supply voltage；Output terminal of the cathode of first diode D1 as first charge pump circuit.
Grid voltage promoted circuit connect the first charge pump circuit output terminal, including third NMOS tube MN3, the 4th NMOSMN4,
The grid of 5th PMOS tube MP5 and the 6th capacitance C6, the 4th NMOS tube MN4 connect the NMOS main switches MnGrid,
The drain electrode of the grid and the 5th PMOS tube MP5 of three NMOS tube MN3, source electrode connect the input of the boot-strapped switch circuit
End, the source electrode of drain electrode connection third NMOS tube MN3 simultaneously pass through the source electrode of the 5th PMOS tube MP5 of connection and institute after the 6th capacitance C6
State the output terminal of the first charge pump circuit；The grid of 5th PMOS tube MP5 connects the first switch circuit.
First charge pump circuit is turned it on by raising the supply voltage VDD of the grid voltage to positive 2 times of metal-oxide-semiconductor, is used
It charges in promoting the 6th capacitance C6 in circuit for grid voltage so that the constant quantity of electric charge of the 6th capacitance C6 storages is its capacitance and 2
Times supply voltage VDD subtracts the product of diode drop；Grid voltage promotes circuit for changing NMOS main switches MnGrid end electricity
Pressure, by improving NMOS main switches MnGrid end voltage using realize its gate source voltage as with input signal VinUnrelated is constant
Value, the function of being promoted so as to fulfill grid voltage simultaneously eliminate input signal VinTo NMOS main switches MnThe influence of conducting resistance；First
Switching circuit is for controlling the charging of the first charge pump circuit and grid voltage to promote the opening and closing of circuit, and the in the present embodiment
One switching circuit includes the 6th NMOS tube MN6, the 7th NMOS tube MN7, the 8th NMOS tube MN8, the 9th NMOS tube MN9, the tenth
NMOS tube MN10, the 11st PMOS tube MP11 and the 12nd PMOS tube MP12, the grid connection inversion clock of the 6th NMOS tube MN6
Signal CLKB, source electrode ground connection, source electrode and the grid voltage of drain electrode connection the 7th NMOS tube MN7 and the 8th NMOS tube MN8
Promote the drain electrode of the 4th NMOS tube MN4 in circuit；The grid of 11st PMOS tube MP11 connect the 7th NMOS tube MN7 grid and
Clock signal clk, source electrode connect supply voltage, the drain electrode of drain electrode connection the 7th NMOS tube MN7 and the 8th NMOS tube MN8 and
The grid voltage promotes the grid of the 5th PMOS tube MP5 in circuit；The grid connection supply voltage of 9th NMOS tube MN9, drain electrode
It connects the grid of the 8th NMOS tube MN8 and the grid voltage promotes the drain electrode of the 5th PMOS tube MP5 in circuit, source electrode connection the tenth
NMOS tube MN10 is managed and the drain electrode of the 12nd PMOS tube MP12；The source electrode connection supply voltage of 12nd PMOS tube MP12, grid
Pole connects the grid of the tenth NMOS tube MN10 and connects inverting clock signal CLKB, the source electrode ground connection of the tenth NMOS tube MN10.
The second charge pump circuit for connecting PMOS main switches includes the first PMOS tube MP1, the second PMOS tube MP2, third
Capacitance C3, the 4th capacitance C4 and the second diode D2, the grid of the first PMOS tube MP1 connect the source electrode of the second PMOS tube MP2 simultaneously
By connecting inverting clock signal CLKB after third capacitance C3, source electrode connects grid and the two or two pole of the second PMOS tube MP2
The cathode of pipe D2 simultaneously passes through clock signal clk is connected after the 4th capacitance C4, and the drain electrode of the second PMOS tube MP2 of drain electrode connection simultaneously connects
Ground；Output terminal of the anode of second diode D2 as second charge pump circuit.
Grid voltage reduces the output terminal that circuit connects the second charge pump circuit, including third PMOS tube MP3, the 4th PMOS tube
MP4, the 5th NMOS tube MN5 and the 5th capacitance C5, the grid of the 4th PMOS tube MP4 connect the PMOS main switches MpGrid
The drain electrode of pole, the grid of third PMOS tube MP3 and the 5th NMOS tube MN5, source electrode connect the boot-strapped switch circuit
Input terminal, the source electrode of drain electrode connection third PMOS tube MP3 and the grid voltage promote the drain electrode of third NMOS tube MN3 in circuit simultaneously
By connecting the source electrode of the 5th NMOS tube MN5 and the output terminal of second charge pump circuit after the 5th capacitance C5；5th NMOS
The grid of pipe MN5 connects the second switch circuit；The drain electrode of third PMOS tube MP3 connects the grid voltage and promotes third in circuit
The source electrode of NMOS tube MN3.
Second charge pump circuit is turned it on by reducing the grid voltage of metal-oxide-semiconductor to negative supply voltage VDD, for for
The 5th capacitance C5 chargings that grid voltage is reduced in circuit make its amount of charge stored be fixed as its capacitance with 2 times of supply voltage VDD to subtract
The product of diode drop is gone, grid voltage reduces grid end voltage of the circuit for changing PMOS main switches, by reducing PMOS master
Switching tube MpGrid end voltage using realize its gate source voltage as with input voltage VinUnrelated steady state value reduces so as to fulfill grid voltage
Function and eliminate input signal VinTo PMOS main switches MpThe influence of conducting resistance；Second switch circuit is for control second
The charging of charge pump circuit and grid voltage reduce the opening and closing of circuit；Second switch circuit in the present embodiment includes the 6th
PMOS tube MP6, the 7th PMOS tube MP7, the 8th PMOS tube MP8, the 9th PMOS tube MP9, the tenth PMOS tube MP10, the 11st NMOS
The grid connection clock signal clk of pipe MN11 and the 12nd NMOS tube MN12, the 6th PMOS tube MP6, source electrode ground connection, drain electrode
The source electrode and second grid voltage for connecting the 7th PMOS tube MP7 and the 8th PMOS tube MP8 promote the 4th PMOS tube MP4 in circuit
Drain electrode；The grid connection grid of the 7th PMOS tube MP7 and inverting clock signal CLKB of 11st NMOS tube MN11, source electrode
Ground connection, the drain electrode of drain electrode connection the 7th PMOS tube MP7 and the 8th PMOS tube MP8 and second grid voltage are promoted the 5th in circuit
The grid of NMOS tube MN5；The grounded-grid of 9th PMOS tube MP9, the grid and described the of the 8th PMOS tube MP8 of drain electrode connection
Two grid voltages promote the drain electrode of the 5th NMOS tube MN5 in circuit, and source electrode connects the tenth PMOS tube MP10 pipes and the 12nd NMOS tube
The drain electrode of MN12；The source electrode ground connection of 12nd NMOS tube MN12, when grid connects the grid of the tenth PMOS tube MP10 and connection
Clock signal CLK, the source electrode of the tenth PMOS tube MP10 connect supply voltage.
The operation principle of the present embodiment is：In boot-strapped switch circuit shown in Fig. 2, NMOS main switches M is connectedn's
First charge pump circuit promotes the 6th capacitance C6 in circuit for grid voltage and charges, and the quantity of electric charge that it is stored after charging is C × (2VDD-
VF), wherein VFPressure drop during for diode current flow, then when the bottom crown of the 6th capacitance C6 meets input signal VinWhen, top crown
Voltage is raised to VC6=2VDD-VF+Vin, the 5th PMOS tube MP5 is by NMOS main switches MnGrid and the 6th capacitance C6 upper pole
Plate connects, and causes NMOS main switches MnGate source voltage VGSn=VC6-Vin=2VDD-VF+Vin-Vin=2VDD-VF, it is and input
Signal VinUnrelated and constant 2VDD-VF, NMOS main switches M at this timenConducting, output signal VoutTo input signal VinCarry out with
Track so as to fulfill grid voltage enhanced feature and eliminates input signal to NMOS main switches MnThe influence of conducting resistance.
Connect PMOS main switches MpThe second charge pump circuit for grid voltage reduce circuit in the 5th capacitance C5 charging, fill
The quantity of electric charge that it is stored after electricity is C × (2VDD-VF), wherein VFPressure drop during for diode current flow, then it is upper as the 5th capacitance C5
When pole plate connects input, bottom crown voltage drop is down to VC5=Vin-(2VDD-VF), the 5th NMOS tube MN5 is by PMOS main switches Mp
Grid and the 5th capacitance C5 bottom crown connection, cause PMOS main switches MpGate source voltage VGSp=Vin-VC=Vin-
(2VDD-VF+Vin)=- (2VDD-VF), it is and input signal VinUnrelated and constant-(2VDD-VF), PMOS main switches M at this timep
Conducting, output signal VoutTo input signal VinInto line trace, so as to fulfill grid voltage enhanced feature and input signal pair is eliminated
PMOS main switches MpThe influence of conducting resistance.
The present invention can make NMOS main switches M simultaneouslynWith PMOS main switches MpRaceway groove electricity caused by changing due to clock
Lotus injection effect and clock feed-through effect also offset each other, so as to improve the linearity of switch.
To sum up, a kind of boot-strapped switch circuit provided by the invention, makes NMOS main switches MnWith PMOS main switches Mp
Gate source voltage in conducting is fixed value, and NMOS main switches MnWith PMOS main switches MpSimultaneously by input signal Vin
Output is connected to, reduces the conducting resistance of switch；By using NMOS main switches MnWith PMOS main switches MpSide in parallel
Formula so that NMOS main switches MnWith PMOS main switches MpChannel charge injection effect mutually offsets caused by clock changes
Disappear, clock feed-through effect also offsets each other, so as to improve the linearity of switch；It is filled by using diode pair capacitance
Electricity, making circuit, there is no overvoltage devices, improve the reliability of circuit.
Those of ordinary skill in the art can make various do not depart from originally according to these technical inspirations disclosed by the invention
The other various specific deformations and combination of essence are invented, these deformations and combination are still within the scope of the present invention.
Claims (2)
1. a kind of boot-strapped switch circuit, which is characterized in that including NMOS main switches (Mn) and PMOS main switches (Mp),
And with NMOS main switches (Mn) the first charge pump circuit of connection, grid voltage promote circuit and first switch circuit, with PMOS
Main switch (Mp) the second charge pump circuit of connection, grid voltage reduce circuit and second switch circuit,
NMOS main switches (Mn) source electrode connection PMOS main switches (Mp) source electrode and be used as the boot-strapped switch circuit
Input terminal, drain electrode connection PMOS main switches (Mp) drain electrode and as the output terminal of the boot-strapped switch circuit；
First charge pump circuit includes the first NMOS tube (MN1), the second NMOS tube (MN2), the first capacitance (C1), the second electricity
Hold (C2) and the first diode (D1),
The grid of first NMOS tube (MN1) connects the source electrode of the second NMOS tube (MN2) and the anode of the first diode (D1) and leads to
It crosses the second capacitance (C2) and connects inverting clock signal (CLKB) afterwards, source electrode connects the grid of the second NMOS tube (MN2) and passes through
First capacitance (C1) connects clock signal (CLK) afterwards, and the drain electrode of drain electrode the second NMOS tube of connection (MN2) simultaneously connects power supply electricity
Pressure；Output terminal of the cathode of first diode (D1) as first charge pump circuit；
Second charge pump circuit includes the first PMOS tube (MP1), the second PMOS tube (MP2), third capacitance (C3), the 4th electricity
Hold (C4) and the second diode (D2),
The grid of first PMOS tube (MP1) connects the source electrode of the second PMOS tube (MP2) and passes through third capacitance (C3) and connects afterwards instead
Clock signal (CLKB), source electrode connect the grid of the second PMOS tube (MP2) and the cathode of the second diode (D2) and pass through
4th capacitance (C4) connects clock signal (CLK), the drain electrode of drain electrode the second PMOS tube of connection (MP2) and ground connection afterwards；Two or two
Output terminal of the anode of pole pipe (D2) as second charge pump circuit；
The grid voltage promotes circuit and includes third NMOS tube (MN3), the 4th NMOS (MN4), the 5th PMOS tube (MP5) and the 6th electricity
Hold (C6),
The grid of 4th NMOS tube (MN4) connects the NMOS main switches (Mn) grid, third NMOS tube (MN3) grid
With the drain electrode of the 5th PMOS tube (MP5), source electrode connects the input terminal of the boot-strapped switch circuit, drain electrode connection third
The source electrode of NMOS tube (MN3) simultaneously passes through the 6th capacitance (C6) and connects the source electrode of the 5th PMOS tube (MP5) and first charge afterwards
The output terminal of pump circuit；The grid of 5th PMOS tube (MP5) connects the first switch circuit；
The grid voltage reduces circuit and includes third PMOS tube (MP3), the 4th PMOS tube (MP4), the 5th NMOS tube (MN5) and the 5th
Capacitance (C5),
The grid of 4th PMOS tube (MP4) connects the PMOS main switches (Mp) grid, third PMOS tube (MP3) grid
With the drain electrode of the 5th NMOS tube (MN5), source electrode connects the input terminal of the boot-strapped switch circuit, drain electrode connection third
The source electrode of PMOS tube (MP3) and the grid voltage promote the drain electrode of third NMOS tube (MN3) in circuit and pass through the 5th capacitance (C5)
The output terminal of the source electrode of the 5th NMOS tube (MN5) of connection and second charge pump circuit afterwards；The grid of 5th NMOS tube (MN5)
Connect the second switch circuit；The drain electrode of third PMOS tube (MP3) connects the grid voltage and promotes third NMOS tube in circuit
(MN3) source electrode；
The first switch circuit generates timing control signal control according to clock signal (CLK) and inverting clock signal (CLKB)
The grid voltage promotes circuit；
The second switch circuit generates timing control signal control according to clock signal (CLK) and inverting clock signal (CLKB)
The grid voltage reduces circuit.
2. boot-strapped switch circuit according to claim 1, which is characterized in that the first switch circuit includes the 6th
NMOS tube (MN6), the 7th NMOS tube (MN7), the 8th NMOS tube (MN8), the 9th NMOS tube (MN9), the tenth NMOS tube (MN10),
11st PMOS tube (MP11) and the 12nd PMOS tube (MP12),
The grid connection inverting clock signal (CLKB) of 6th NMOS tube (MN6), source electrode ground connection, the 7th NMOS of drain electrode connection
It manages the source electrode of (MN7) and the 8th NMOS tube (MN8) and the grid voltage promotes the drain electrode of the 4th NMOS tube (MN4) in circuit；
The grid connection grid of the 7th NMOS tube (MN7) and clock signal (CLK), source electrode of 11st PMOS tube (MP11) connect
Supply voltage, the drain electrode of drain electrode the 7th NMOS tube (MN7) of connection and the 8th NMOS tube (MN8) and the grid voltage promote circuit
In the 5th PMOS tube (MP5) grid；
The grid connection supply voltage of 9th NMOS tube (MN9), the grid and the grid of drain electrode the 8th NMOS tube (MN8) of connection
Pressure promotes the drain electrode of the 5th PMOS tube (MP5) in circuit, and source electrode connects the tenth NMOS tube (MN10) pipe and the 12nd PMOS tube
(MP12) drain electrode；
The source electrode connection supply voltage of 12nd PMOS tube (MP12), grid connect the grid of the tenth NMOS tube (MN10) and company
Reversed clock signal (CLKB), the source electrode ground connection of the tenth NMOS tube (MN10)；
The second switch circuit includes the 6th PMOS tube (MP6), the 7th PMOS tube (MP7), the 8th PMOS tube (MP8), the 9th
PMOS tube (MP9), the tenth PMOS tube (MP10), the 11st NMOS tube (MN11) and the 12nd NMOS tube (MN12),
The grid connection clock signal (CLK) of 6th PMOS tube (MP6), source electrode ground connection, drain electrode the 7th PMOS tube of connection
(MP7) and the source electrode of the 8th PMOS tube (MP8) and the grid voltage reduce the drain electrode of the 4th PMOS tube (MP4) in circuit；
The grid connection grid of the 7th PMOS tube (MP7) and inverting clock signal (CLKB) of 11st NMOS tube (MN11),
Source electrode is grounded, and the drain electrode of drain electrode the 7th PMOS tube (MP7) of connection and the 8th PMOS tube (MP8) and the grid voltage are reduced in circuit
The grid of 5th NMOS tube (MN5)；
The grounded-grid of 9th PMOS tube (MP9), the grid of drain electrode the 8th PMOS tube (MP8) of connection and the grid voltage reduce electricity
The drain electrode of five NMOS tubes of Lu Zhong (MN5), source electrode connect the tenth PMOS tube (MP10) pipe and the 12nd NMOS tube (MN12)
Drain electrode；
The source electrode ground connection of 12nd NMOS tube (MN12), grid connect the grid of the tenth PMOS tube (MP10) and connect clock letter
Number (CLK), the source electrode of the tenth PMOS tube (MP10) connect supply voltage.
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| CN108155899B CN108155899B (en) | 2020-07-31 |
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| CN110149111A (en) * | 2019-04-18 | 2019-08-20 | 珠海亿智电子科技有限公司 | A kind of bootstrap switch circuit and its control method |
| CN111106819A (en) * | 2019-12-31 | 2020-05-05 | 思瑞浦微电子科技（苏州）股份有限公司 | Grid voltage bootstrap switch circuit |
| CN112671382A (en) * | 2020-12-16 | 2021-04-16 | 东南大学 | Grid voltage bootstrap switch circuit |
| CN112787644A (en) * | 2019-11-11 | 2021-05-11 | 圣邦微电子（北京）股份有限公司 | Bootstrap circuit with power-on reset function |
| CN113315371A (en) * | 2021-04-13 | 2021-08-27 | 西安拓尔微电子有限责任公司 | Self-adaptive charge pump control circuit and control method for four-switch-tube buck-boost converter |
| CN113517883A (en) * | 2021-07-09 | 2021-10-19 | 广东工业大学 | Bootstrap switch for reducing channel charge injection effect |
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| CN110149111A (en) * | 2019-04-18 | 2019-08-20 | 珠海亿智电子科技有限公司 | A kind of bootstrap switch circuit and its control method |
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| CN112787644A (en) * | 2019-11-11 | 2021-05-11 | 圣邦微电子（北京）股份有限公司 | Bootstrap circuit with power-on reset function |
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| CN111106819B (en) * | 2019-12-31 | 2023-04-18 | 思瑞浦微电子科技（苏州）股份有限公司 | Grid voltage bootstrap switch circuit |
| CN112671382A (en) * | 2020-12-16 | 2021-04-16 | 东南大学 | Grid voltage bootstrap switch circuit |
| CN112671382B (en) * | 2020-12-16 | 2023-08-08 | 东南大学 | Grid voltage bootstrapping switch circuit |
| CN113315371A (en) * | 2021-04-13 | 2021-08-27 | 西安拓尔微电子有限责任公司 | Self-adaptive charge pump control circuit and control method for four-switch-tube buck-boost converter |
| CN113517883A (en) * | 2021-07-09 | 2021-10-19 | 广东工业大学 | Bootstrap switch for reducing channel charge injection effect |
| CN113517883B (en) * | 2021-07-09 | 2023-05-26 | 广东工业大学 | Bootstrap switch for reducing channel charge injection effect |
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