CN112787644A

CN112787644A - Bootstrap circuit with power-on reset function

Info

Publication number: CN112787644A
Application number: CN201911093845.9A
Authority: CN
Inventors: 张伟
Original assignee: SG Micro Beijing Co Ltd
Current assignee: SG Micro Beijing Co Ltd
Priority date: 2019-11-11
Filing date: 2019-11-11
Publication date: 2021-05-11
Anticipated expiration: 2039-11-11
Also published as: CN112787644B

Abstract

A bootstrap circuit with a power-on reset function is characterized in that a main bootstrap circuit and an additional power-on reset discharge circuit are combined, an output signal end of the main bootstrap circuit is connected with the additional power-on reset discharge circuit, and stored charges on a capacitor of the output signal end are released in a short pulse switching mode when a chip is powered on again, so that the output signal is prevented from being abnormal due to power-on restoration.

Description

Bootstrap circuit with power-on reset function

Technical Field

The invention relates to a bootstrap circuit technology, in particular to a bootstrap circuit with a power-on reset function, which is characterized in that through the combination of a main bootstrap circuit and an additional power-on reset discharge circuit, and through the connection of an output signal end of the main bootstrap circuit and the additional power-on reset discharge circuit, when a chip is powered on again, a short pulse switch mode is used for releasing stored charges on a capacitor of the output signal end, so that the output signal abnormality caused by the power-on restoration is avoided.

Background

Existing bootstrap circuits are used to boost the existing voltage to a double or fixed voltage. In the event of power loss or shutdown (chip off, which is usually not normally off), charge is temporarily stored on the capacitor due to the absence of a discharge path. If the power is turned on instantly after the power failure or the chip is turned on after shutdown, and the power supply voltage is lower than the previous power supply voltage in the two processes after the power is turned on, the voltage output by the circuit is incorrect, even the circuit cannot be restored to a normal state, and the subsequent circuit is in an error. Fig. 1 is a timing diagram of an abnormality occurring in a conventional bootstrap circuit. The bootstrap circuit of fig. 1 has no discharge circuit, as shown by the circuit on the left side of the dotted line in fig. 2. A first signal output end out1 of the high-voltage power supply is connected with a first signal input end in1 through a first capacitor C1, a second signal output end out2 of the high-voltage power supply is connected with a second signal input end in2 through a second capacitor C2, the first signal output end out1 is respectively connected with the drain of a first NMOS transistor M1 and the gate of a second NMOS transistor M2, the second signal output end out2 is respectively connected with the gate of the first NMOS transistor M1 and the drain of the second NMOS transistor M2, and the source of the first NMOS transistor M1 and the source of the second NMOS transistor M2 are both connected with a power supply voltage end VDD. As shown in FIG. 1, in1 and in2 are both [0, VDD1] square wave signals, but are inverted. In the interval from t1 to t2, the circuit works normally, and both out1 and out2 are square wave signals of [ VDD1, 2VDD1], but the two signals are also in phase opposition. At time t2, the chip shutdown. In the interval from t2 to t3, the voltages of out1 and out2 are almost constant. At time t3, the power supply voltage drops from VDD1 to VDD 2. At the same time, the shutdown signal returns to high, the level is also VDD2, and the chip should operate normally, but since out1 and out2 do not have a discharge path during shutdown, and store charges, after time t3, out1 and out2 cannot normally output square wave signals of [ VDD2, 2VDD2 ]. The inventor believes that if the stored charge on the capacitor of the output signal end is released in a short pulse switching mode when the chip is powered on again through the combination of the main bootstrap circuit and the additional power-on reset discharge circuit and the connection of the output signal end of the main bootstrap circuit and the additional power-on reset discharge circuit, the output signal caused by power-on restoration can be prevented from being abnormal. In view of the above, the present inventors have completed the present invention.

Disclosure of Invention

Aiming at the defects or shortcomings in the prior art, the invention provides the bootstrap circuit with the power-on reset function, the combination of the main bootstrap circuit and the additional power-on reset discharge circuit is adopted, the output signal end of the main bootstrap circuit is connected with the additional power-on reset discharge circuit, and the stored charge on the capacitor of the output signal end is released in a short pulse switch mode when the chip is powered on again, so that the output signal is prevented from being abnormal due to the power-on restoration.

The technical scheme of the invention is as follows:

a bootstrap circuit with a power-on reset function is characterized by comprising a main bootstrap circuit, wherein an output signal end of the main bootstrap circuit is connected with an additional power-on reset discharging circuit, and the additional power-on reset discharging circuit releases stored charges on a capacitor of the output signal end in a short pulse switching mode when a chip is powered on again.

The main body bootstrap circuit comprises a first output signal end and a second output signal end, the additional power-on reset discharge circuit comprises a fifth NMOS tube and a sixth NMOS tube, the source electrode of the fifth NMOS tube and the source electrode of the sixth NMOS tube are both grounded, the grid electrode of the fifth NMOS tube and the grid electrode of the sixth NMOS tube are both connected with a discharge channel pulse signal control end, the drain electrode of the fifth NMOS tube is connected with the first output signal end, and the drain electrode of the sixth NMOS tube is connected with the second output signal end.

The main body bootstrap circuit comprises a first output signal end and a second output signal end, the additional power-on reset discharge circuit comprises a third NMOS tube, a fourth NMOS tube, a fifth NMOS tube and a sixth NMOS tube, a grid electrode of the third NMOS tube and a grid electrode of the fourth NMOS tube are connected with a power supply voltage end, a drain electrode of the third NMOS tube is connected with the first output signal end, a drain electrode of the fourth NMOS tube is connected with the second output signal end, a source electrode of the third NMOS tube is connected with a drain electrode of the fifth NMOS tube, a source electrode of the fourth NMOS tube is connected with a drain electrode of the sixth NMOS tube, a source electrode of the fifth NMOS tube and a source electrode of the sixth NMOS tube are both grounded, and a grid electrode of the fifth NMOS tube and a grid electrode of the sixth NMOS tube are both connected with a discharge path pulse signal control end.

The main part bootstrapping circuit includes first output signal end and second output signal end, first signal output part connects first signal input part through first electric capacity, second signal output part passes through second electric capacity and connects second signal input part, the drain electrode of first NMOS pipe and the grid of second NMOS pipe are connected respectively to first signal output part subdividing, the grid of first NMOS pipe and the drain electrode of second NMOS pipe are connected respectively to second signal output part subdividing, the source electrode of first NMOS pipe with the source electrode of second NMOS pipe all connects the mains voltage end.

The invention has the following technical effects: the invention relates to a bootstrap circuit with a power-on reset function, which adds a power-on reset discharge circuit at an output signal end of a main bootstrap circuit. The control signal of the power-on reset discharge circuit can be a power-on reset signal of a power supply, or can be generated by a chip shutdown signal and a power-on reset signal logic, and a short pulse is generated when the chip is powered on. Before other circuits work normally, the pulse signal is used for resetting, and meanwhile, the effect of releasing the stored charges on the capacitor at the output signal end in a short pulse switching mode is achieved, so that the output signal is prevented from being abnormal due to power-on recovery, and the correctness of the output signal is ensured. After normal operation, the pulse is low, and the normal operation of the circuit is not influenced.

Drawings

Fig. 1 is a timing diagram of an abnormality occurring in a conventional bootstrap circuit. In the interval t1 to t2 of the time axis in fig. 1, the circuit normally operates. At time t2, the chip shutdown (chip off, i.e., from VDD1 down to 0 potential). In the interval from t2 to t3, the voltages of out1 and out2 are almost unchanged (out1 is kept at 2VDD1, and out2 is kept at VDD 1). At time t3, the power supply voltage is reduced from VDD1 to VDD2, and the shutdown signal returns to high (i.e., rises from 0 and remains at VDD2, and VDD2 is smaller than VDD1), the chip should operate normally, but since out1 and out2 have no discharge path during shutdown, and store charges, after time t3, out1 and out2 cannot normally output square wave signals of VDD 2-2 VDD2 (VDD 2 of out2 remains below VDD1, and 2VDD2 does not appear).

Fig. 2 is a schematic diagram of a bootstrap circuit with power-on reset function according to the present invention. The left side of the middle vertical dashed line in fig. 2 is the body bootstrap circuit and the right side is the additional power-on reset discharge circuit. The body bootstrap circuit comprises two NMOS transistors M1 and M2, and the additional power-on reset discharge circuit comprises four NMOS transistors M3, M4, M5 and M6.

FIG. 3 is a timing diagram of the nodes of FIG. 2. Fig. 3 includes a power voltage terminal VDD, a first input signal terminal in1, a second input signal terminal in2, a first output signal terminal out1, a second output signal terminal out2, a shutdown signal waveform, a discharge path short pulse reset, a normal operation time period of a circuit from t1 to t2, a shutdown (shutdown) time period of a chip from t2 to t3, a time period after the power voltage is reduced from VDD1 to VDD2 at t3, and a shutdown signal is restored to high.

The reference numbers are listed below: VDD-supply voltage or supply voltage terminal; shutdown-control signals for part or all of the functions of the shutdown chip; in1 — first input signal terminal or first input signal; in2 — second input signal terminal or second input signal; out 1-first output signal terminal or first output signal; out 2-second output signal terminal or second output signal; reset-discharge path pulse signal control terminal or short pulse signal; t 1-t 3-first to third time; C1-C2-first to second capacitors; M1-M6-the first to sixth NMOS transistors.

Detailed Description

The invention is described below with reference to the accompanying drawings (fig. 2-3).

Fig. 2 is a schematic diagram of a bootstrap circuit with power-on reset function according to the present invention. FIG. 3 is a timing diagram of the nodes of FIG. 2. Referring to fig. 2 and 3, a bootstrap circuit with power-on reset function includes a main bootstrap circuit (e.g., a left circuit of a middle vertical dashed line in fig. 2), an output signal terminal of which is connected to an additional power-on reset discharge circuit (e.g., a right circuit of a middle vertical dashed line in fig. 2), which discharges stored charges on capacitances (e.g., a first capacitor C1 and a second capacitor C2) of the output signal terminal in a short pulse switching manner when a chip resumes power-on. The main body bootstrap circuit comprises a first output signal end out1 and a second output signal end out2, the additional power-on reset discharge circuit comprises a fifth NMOS tube M5 and a sixth NMOS tube M6, the source electrode of the fifth NMOS tube M5 and the source electrode of the sixth NMOS tube M6 are both grounded, the grid electrode of the fifth NMOS tube M5 and the grid electrode of the sixth NMOS tube M6 are both connected with a discharge path pulse signal control end reset, the drain electrode of the fifth NMOS tube M5 is connected with the first output signal end out1, and the drain electrode of the sixth NMOS tube M6 is connected with the second output signal end out 2.

The body bootstrap circuit comprises a first output signal end out1 and a second output signal end out2, the additional power-on reset discharge circuit comprises a third NMOS tube M3, a fourth NMOS tube M4, a fifth NMOS tube M5 and a sixth NMOS tube M6, the gates of the third NMOS tube M3 and the fourth NMOS tube M4 are both connected with a power supply voltage end VDD, the drain of the third NMOS tube M3 is connected with the first output signal end out1, the drain of the fourth NMOS tube M4 is connected with the second output signal end out2, the source of the third NMOS tube M3 is connected with the drain of the fifth NMOS tube M5, the source of the fourth NMOS tube M4 is connected with the drain of the sixth NMOS tube M6, the source of the fifth NMOS tube M5 and the source of the sixth NMOS tube M6 are both grounded, and the gate of the fifth NMOS tube M5 and the sixth NMOS tube M6 are both connected with a pulse control signal discharge end reset control circuit. The body bootstrap circuit comprises a first output signal terminal out1 and a second output signal terminal out2, the first signal output terminal out1 is connected to the first signal input terminal in1 through a first capacitor C1, the second signal output terminal out2 is connected to the second signal input terminal in2 through a second capacitor C2, the first signal output terminal in1 is respectively connected to the drain of the first NMOS transistor M1 and the gate of the second NMOS transistor M2, the second signal output terminal out2 is respectively connected to the gate of the first NMOS transistor M1 and the drain of the second NMOS transistor M2, and the source of the first NMOS transistor M1 and the source of the second NMOS transistor M2 are both connected to the power supply voltage terminal VDD.

As shown in the left part of the dotted line of FIG. 2, the traditional bootstrap circuit inputs an opposite square wave signal from 0 to VDD1 at the in1 and in2 ends, and outputs an opposite square wave signal from VDD1 to 2VDD1 at the out1 and out2 ends. When the power supply is suddenly turned off or the chip is shutdown, the charges of out1 and out2 will be stored in the capacitors C1 and C2 because there is no discharge path. If the power is turned on again or the chip is turned on again after shutdown, and the power-on voltage is lower than before, the charges stored in the capacitors C1 and C2 will cause errors in out1 and out 2. The invention provides a power-on reset discharge circuit added to a traditional bootstrap circuit. The power-on reset discharge circuit is shown in the right part of the dotted line of FIG. 2 and is composed of M3-M6. The circuit sequence with power-on reset discharge is shown in fig. 3, and in normal operation, the reset signal is low, and M5 and M6 are turned off. At time shutdown goes low at t2, and out1 and out2 still store charge. At time t3, the shutdown signal goes back high, which produces a short pulse reset. Before other circuits work normally, the reset voltage is high, and M5 and M6 are conducted, so that a discharge path is formed, and charges of C1 and C2 are discharged. Then reset goes back low, M5, M6 turn off, and the circuit works normally. If M5 and M6 can withstand high pressures, M3 and M4 can be deleted.

It is pointed out here that the above description is helpful for the person skilled in the art to understand the invention, but does not limit the scope of protection of the invention. Any such equivalents, modifications and/or omissions as may be made without departing from the spirit and scope of the invention may be resorted to.

Claims

1. A bootstrap circuit with a power-on reset function is characterized by comprising a main bootstrap circuit, wherein an output signal end of the main bootstrap circuit is connected with an additional power-on reset discharging circuit, and the additional power-on reset discharging circuit releases stored charges on a capacitor of the output signal end in a short pulse switching mode when a chip is powered on again.

2. The bootstrap circuit with power-on reset function as claimed in claim 1, wherein the main bootstrap circuit includes a first output signal terminal and a second output signal terminal, the additional power-on reset discharge circuit includes a fifth NMOS transistor and a sixth NMOS transistor, a source of the fifth NMOS transistor and a source of the sixth NMOS transistor are both grounded, a gate of the fifth NMOS transistor and a gate of the sixth NMOS transistor are both connected to a discharge path pulse signal control terminal, a drain of the fifth NMOS transistor is connected to the first output signal terminal, and a drain of the sixth NMOS transistor is connected to the second output signal terminal.

3. The bootstrap circuit with power-on reset function as claimed in claim 1, wherein the main bootstrap circuit includes a first output signal terminal and a second output signal terminal, the additional power-on reset discharge circuit includes a third NMOS transistor, a fourth NMOS transistor, a fifth NMOS transistor and a sixth NMOS transistor, gates of the third NMOS transistor and the fourth NMOS transistor are both connected to a power supply voltage terminal, a drain of the third NMOS transistor is connected to the first output signal terminal, a drain of the fourth NMOS transistor is connected to the second output signal terminal, a source of the third NMOS transistor is connected to a drain of the fifth NMOS transistor, a source of the fourth NMOS transistor is connected to a drain of the sixth NMOS transistor, a source of the fifth NMOS transistor and a source of the sixth NMOS transistor are both grounded, and a gate of the fifth NMOS transistor and a gate of the sixth NMOS transistor are both connected to a discharge path pulse signal control terminal.

4. The bootstrap circuit with power-on reset function as claimed in claim 1, wherein the main body bootstrap circuit includes a first output signal terminal and a second output signal terminal, the first signal output terminal is connected to the first signal input terminal through a first capacitor, the second signal output terminal is connected to the second signal input terminal through a second capacitor, the first signal output terminal is connected to the drain of the first NMOS transistor and the gate of the second NMOS transistor respectively, the second signal output terminal is connected to the gate of the first NMOS transistor and the drain of the second NMOS transistor respectively, and the source of the first NMOS transistor and the source of the second NMOS transistor are both connected to the power supply voltage terminal.