CN102185596A - Bootstrapping sampling switch applied to high-speed and high-linearity analog-to-digital converter - Google Patents
Bootstrapping sampling switch applied to high-speed and high-linearity analog-to-digital converter Download PDFInfo
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- CN102185596A CN102185596A CN 201110108268 CN201110108268A CN102185596A CN 102185596 A CN102185596 A CN 102185596A CN 201110108268 CN201110108268 CN 201110108268 CN 201110108268 A CN201110108268 A CN 201110108268A CN 102185596 A CN102185596 A CN 102185596A
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- electric capacity
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C27/00—Electric analogue stores, e.g. for storing instantaneous values
- G11C27/02—Sample-and-hold arrangements
- G11C27/024—Sample-and-hold arrangements using a capacitive memory element
Abstract
The invention provides a bootstrapping sampling switch applied to a high-speed and high-linearity analog-to-digital converter. The bootstrapping sampling switch comprises a clock booster, a grid-source voltage follower, a conduction switch and a charging and discharging enhanced circuit, wherein several times of power voltage are generated by the clock booster and used for charging a capacitor; the grid-source voltage follower connects the capacitor between the grid and the source when the conduction switch is off, so that a relevantly constant grid-source voltage difference under different voltage input is ensured; the charging and discharging enhanced circuit is added in a charging or discharging loop during switching of the switch so as to shorten the off and on time, reduce a parasitic capacitance of the grid of the conduction switch and reduce the loss of the storage charge of the capacitor; the use of a high-voltage metal oxide semiconductor (MOS) tube is not needed; meanwhile, high-linearity sampling is realized (the sampling rate is more than 1 KMHz under 65-nano complementary metal-oxide-semiconductor (CMOS) technology and a stray-free dynamic range more than 95 decibels can be obtained). A complicated logic control circuit is absent in the structure, so the area of a chip cannot be increased; moreover, a requirement of the clock buffer is not needed to be enhanced.
Description
Technical field
The invention relates to a kind of important module that is applied to sampling hold circuit, be specifically related to adopt bootstrapping (bootstrapped) and discharge and recharge that path technology is applicable at a high speed, the analog switch of high linearity analog to digital converter more.
Technical background
In modern composite signal integrated circuits, analog to digital converter is indispensable part, and its conversion accuracy and speed play decisive role to the performance of whole system.The analog switch that uses in sampling hold circuit has then determined the dynamic range and the sample rate of analog to digital converter.
Fig. 1 has provided a simple sampling hold circuit of being made up of cmos switch and electric capacity.Traditional cmos switch is because conducting resistance is big and be difficult to along with the shortcoming of input signal size variation in the analog to digital converter of high linearity (green curve as shown in Figure 2).The size that increases metal-oxide-semiconductor can reduce these non-ideal factors, but can propose higher requirement to clock buffer, needs bigger power consumption accordingly.In this external low voltage designs, when supply voltage during less than NMOS pipe and PMOS pipe threshold voltage sum, the king-sized one section zone of conducting resistance can appear in the traditional cmos switch.
In order to solve the problem that the traditional cmos switch runs into, as shown in Figure 3, (a kind of bootstrap type switch sees reference document A.M.Abo and P.R.Gray, " A 1.5-V 10-bit 14.3-MS/s CMOS PipelineAnalog-to-Digital Converter; " IEEE J.Solid-State Circuits, vol.34, pp.599-606, May 1999.) by clock boosting device (clock booster), produce relative constantly and at the grid of the metal-oxide-semiconductor that plays on-off action and input, can obtain less and not with the conducting resistance of input signal size variation near the pressure reduction of supply voltage.Widely used bottom crown Sampling techniques (turn-off time) as far as possible short switch that needs the turn-off time in analog to digital converter, in the time of this while, thereby also the opening time (turn-on time) is had higher requirement for further raising sample rate continuous compression sampling in circuit design.Just there is long shortcoming of turn-off time and opening time in this bootstrap type switch, and owing to guaranteeing that the high pressure NMOS pipe (as M11 among Fig. 3 and M12) that reliability is used has further limited the speed that switch switches.
Summary of the invention
The objective of the invention is to, by a kind of bootstrap type sampling switch that is applied to high-speed high linearity analog to digital converter is provided, on the way basis of generally adopting at present, shorten the demand of switch switching time, the present invention is under the prerequisite that does not increase design complexities and chip area, use to discharge and recharge path technology raising switch switch speed more, and no longer need to use the high pressure NMOS pipe.
The present invention adopts following technological means to realize:
A kind of bootstrap type sampling switch that is applied to high-speed high linearity analog to digital converter of the present invention comprises: clock boosting device, gate source voltage follower, actuating switch and discharge and recharge intensifier circuit, and the clock boosting device produces the supply voltage of twice, and electric capacity is charged; The gate source voltage follower is connected electric capacity between its grid source electrode when actuating switch is closed, remains on different voltages inputs and descends constant relatively gate source voltage poor; Discharge and recharge the charge or discharge loop of intensifier circuit when being increased in switch and switching, wherein:
Aforementioned clock boosting device comprises an inverter I1, two NMOS pipe M1 and M2, two capacitor C 1 and C2, and wherein: the inversion clock signal is connected to the bottom crown of aforementioned electric capacity C1, is connected to the bottom crown of aforementioned electric capacity C2 through inverter I1; The drain electrode of M1 and M2 is connected to power supply, and its grid is connected to source electrode each other, and connects the top crown of C1 and C2 respectively.
Aforementioned grid voltage follower comprises five NMOS pipe M3, M4, M6, M8 and M9, two PMOS pipe M5 and M7, a capacitor C 3, wherein: the grid of M3 is connected with the grid of M2 in the aforementioned clock boosting device, drain electrode connects power supply, source electrode connects the top crown of capacitor C 3, the grid of NMOS pipe M4 is by the inversion clock signal controlling, source electrode is connected to ground, and drain electrode connects the bottom crown of capacitor C 3; The source electrode of PMOS pipe M7 and drain electrode are connected the top crown of capacitor C 3 and the grid that aforementioned NMOS manages M9 respectively, and the drain electrode of M9 and source electrode are connected the bottom crown and the input of capacitor C 3 respectively; The grid of NMOS pipe M6 is by the control of positive clock signal, and drain electrode connects the grid of PMOS pipe M7, and source electrode connects the bottom crown of capacitor C 3; The grid of M8 links to each other with the grid of M9, and drain electrode connects the grid of PMOS pipe M7, and source electrode connects the bottom crown of aforementioned electric capacity C3; The grid of PMOS pipe M5 is by the control of positive clock signal, and source electrode connects power supply, and drain electrode connects the grid of PMOS pipe M7.
Actuating switch comprises a NMOS pipe M10, and its source electrode and drain electrode are connected respectively to input and output, and grid links to each other with the grid of NMOS pipe M9 in the aforementioned grid voltage follower.
Discharge and recharge intensifier circuit and comprise two NMOS pipe M13 and M14, wherein: the grid of M13 is by the control of positive clock signal, and drain electrode connects power supply, and source electrode connects the drain electrode of PMOS pipe M7; The grid of M14 is by the inversion clock signal controlling, and drain electrode connects the grid of NMOS pipe M9, and source electrode connects the drain electrode of M9.
The present invention compared with prior art has following remarkable advantages and beneficial effect:
The present invention is applied to the bootstrap type sampling switch of high-speed high linearity analog to digital converter, compares with the metal-oxide-semiconductor of the identical size of traditional approach, under the prerequisite that realizes high linearity, has improved the speed that switch switches, and has shortened the switching time simultaneously.Realized being applicable to the bootstrap type sampling switch of high-speed high linearity analog to digital converter, have simple in structure, area is little, low in energy consumption and characteristics that the switch switch speed is fast.
Description of drawings
Fig. 1 is for adopting the sampling hold circuit figure of traditional cmos switch;
Fig. 2 is NMOS pipe, PMOS pipe and cmos switch conducting resistance simulation result schematic diagram under different input voltages;
The bootstrap type switching circuit figure that Fig. 3 proposes for Abo;
The high-speed high linearity bootstrap type switching circuit figure that Fig. 4 proposes for the present invention;
Fig. 5 is the simulation result schematic diagram of traditional approach and the present invention's gate-source voltage of actuating switch (M10) when switch switches;
Fig. 6 is the spectrogram of bootstrap type switch sampling of the present invention.
Symbol description:
41 for discharging and recharging intensifier circuit;
Specific implementation method
Bootstrap type sampling switch in the embodiment of the invention as shown in Figure 4.Comprise: clock boosting device, gate source voltage follower, actuating switch and discharge and recharge intensifier circuit.
1. clock signal control bootstrap type sampling switch switches to unlatching (turn-on) by turn-offing (turn-off):
Two NMOS pipe M6 and M13 open simultaneously, so just can manage M7 at PMOS and three NMOS be managed the gate charges of M8, M9 and M10 before opening.Because this part charging charge directly comes from power supply rather than capacitor C 3, the NMOS that so just can have more electric charge to be added in as actuating switch manages between the grid source electrode of M10, and corresponding is higher gate source voltage and littler conducting resistance therewith.In addition, higher gate source voltage also can be accelerated the opening speed of two NMOS pipe M8 and M9, and accelerates the opening speed of PMOS pipe M7 indirectly.Behind PMOS pipe M7 complete opening, because gate source voltage is less than threshold voltage, NMOS pipe M13 turn-offs, and also no longer influences the grid voltage of actuating switch M10.By the charging path that marks with solid line among comparison diagram 3 and Fig. 4, the present invention shortens the opening time of switch by the mode that increases an additional passageway.
2. clock signal control bootstrap type sampling switch switches to shutoff (turn-off) by opening (turn-on):
After NMOS pipe M14 opened, with grid and the source electrode short circuit of actuating switch M10, this also was that a metal-oxide-semiconductor is turn-offed the most direct method.NMOS pipe M4 can finally move the grid source electrode of actuating switch M10 to ground.Since the gate source voltage of actuating switch M10 before being pulled to ground just short circuit together, therefore with respect to traditional method of respectively its grid and source electrode being moved to ground shown in Figure 3 stopcock faster.And, reduced the parasitic capacitance on the actuating switch M10 grid owing to no longer need the necessary high-voltage MOS pipe (as M11 among Fig. 3 and M12) that uses in the conventional method, further accelerated turn-off speed.By the discharge path of with dashed lines mark among comparison diagram 3 and Fig. 4, the present invention is by optimizing the turn-off time that original path shortens switch.
When input signal is big, be used for the NMOS pipe M14 of short circuit actuating switch M10 grid source electrode may not directly open, but along with NMOS pipe M4 reduces the source voltage that NMOS manages M14, the discharge path of actuating switch M10 source-drain electrode also will be opened.Even like this, the velocity of discharge also will be faster than traditional approach as shown in Figure 3.The size of increase NMOS pipe M4 can effectively promote the turn-off speed under this extreme case, and the parasitic capacitance of therefore bringing can take the electric charge that stores on the capacitor C 3 hardly.Because the voltage between NMOS pipe M14 source-drain electrode is always less than supply voltage, so do not need to use high-voltage MOS pipe to guarantee the reliability of circuit.
According to the simulation result of Fig. 5 and Fig. 6 as can be seen, embodiments of the invention use and the metal-oxide-semiconductor of the identical size of traditional approach, under the prerequisite that realizes high linearity, have improved the speed of switch switching, have shortened the switching time simultaneously.
It should be noted that at last: above embodiment only in order to the explanation the present invention and and unrestricted technical scheme described in the invention; Therefore, although this specification has been described in detail the present invention with reference to each above-mentioned embodiment,, those of ordinary skill in the art should be appreciated that still and can make amendment or be equal to replacement the present invention; And all do not break away from the technical scheme and the improvement thereof of the spirit and scope of invention, and it all should be encompassed in the middle of the claim scope of the present invention.
Claims (2)
1. bootstrap type sampling switch that is applied to high-speed high linearity analog to digital converter, comprise: clock boosting device, gate source voltage follower, actuating switch and discharge and recharge intensifier circuit, it is characterized in that: the clock boosting device produces the supply voltage of several times, and electric capacity is charged; The gate source voltage follower is connected electric capacity between its grid source electrode when actuating switch is closed, remains on different voltages inputs and descends constant relatively gate source voltage poor; Discharge and recharge the charge or discharge loop of intensifier circuit when being increased in switch and switching, wherein:
Described clock boosting device comprise an inverter (I1), two NMOS pipe (M1) and (M2), two electric capacity (C1) and (C2); The inversion clock signal is connected to the bottom crown of electric capacity (C1), is connected to the bottom crown of electric capacity (C2) through inverter (I1); (M1) and drain electrode (M2) be connected to power supply, its grid is connected to source electrode each other, and connects electric capacity (C1) and top crown (C2) respectively;
Described grid voltage follower comprise five NMOS pipe (M3), (M4), (M6), (M8) and (M9), two PMOS manage (M5) and (M7), an electric capacity (C3), wherein: the grid of NMOS pipe (M3) is connected with the grid of NMOS pipe (M2) in the clock boosting device, drain electrode connects power supply, source electrode connects the top crown of electric capacity (C3), the grid of NMOS pipe (M4) is by the inversion clock signal controlling, source electrode is connected to ground, and drain electrode connects the bottom crown of electric capacity (C3); The source electrode of PMOS pipe (M7) and drain electrode are connected the top crown of electric capacity (C3) and the grid of NMOS pipe (M9) respectively, and the drain electrode that NMOS manages (M9) and source electrode are connected the bottom crown and the input of electric capacity (C3) respectively; The grid of NMOS pipe (M6) is by the control of positive clock signal, and drain electrode connects the grid of (M7), and source electrode connects the bottom crown of electric capacity (C3); (M8) grid links to each other with the grid of (M9), and drain electrode connects the grid of (M7), and source electrode connects the bottom crown of electric capacity (C3); (M5) grid is by the control of positive clock signal, and source electrode connects power supply, and drain electrode connects the grid of (M7);
Described actuating switch comprises a NMOS pipe (M10), and its source electrode and drain electrode are connected respectively to input and output, and grid links to each other with the grid of NMOS pipe (M9) in the grid voltage follower;
The described intensifier circuit that discharges and recharges comprises two NMOS pipes (M13) and (M14), and wherein: grid (M13) is by the control of positive clock signal, and drain electrode connects power supply, and source electrode connects the drain electrode that PMOS manages (M7); The grid of NMOS pipe (M14) is by the inversion clock signal controlling, and drain electrode connects the grid of (M9), and source electrode connects the drain electrode of (M9).
2. the bootstrap type sampling switch that is applied to high-speed high linearity analog to digital converter according to claim 1 is characterized in that: the supply voltage of the several times that described clock boosting device produces is the electric capacity charging; Its several times are two times.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 201110108268 CN102185596A (en) | 2011-04-28 | 2011-04-28 | Bootstrapping sampling switch applied to high-speed and high-linearity analog-to-digital converter |
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| CN 201110108268 CN102185596A (en) | 2011-04-28 | 2011-04-28 | Bootstrapping sampling switch applied to high-speed and high-linearity analog-to-digital converter |
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Cited By (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102386924A (en) * | 2011-09-21 | 2012-03-21 | 北京工业大学 | Low-voltage asynchronous successive approximation analog-to-digital converter and conversion method |
| CN103326700A (en) * | 2013-05-23 | 2013-09-25 | 苏州苏尔达信息科技有限公司 | Bootstrap sampling switch circuit |
| CN103346765A (en) * | 2013-07-09 | 2013-10-09 | 东南大学 | Gate-source following sampling switch |
| CN104113316A (en) * | 2014-05-12 | 2014-10-22 | 西安电子科技大学 | CMOS bootstrapped switch circuit |
| CN105119604A (en) * | 2015-09-21 | 2015-12-02 | 东南大学 | Bootstrap switch circuit suitable for sampling of an analog-to-digital converter in a low power and voltage condition |
| CN106063207A (en) * | 2014-03-03 | 2016-10-26 | 高通股份有限公司 | Systems and methods for frequency detection |
| CN108696270A (en) * | 2018-05-24 | 2018-10-23 | 上海艾为电子技术股份有限公司 | A kind of analog switching circuit |
| CN109639133A (en) * | 2018-12-28 | 2019-04-16 | 上海贝岭股份有限公司 | Clock level booster circuit |
| CN112787644A (en) * | 2019-11-11 | 2021-05-11 | 圣邦微电子（北京）股份有限公司 | Bootstrap circuit with power-on reset function |
| CN113315505A (en) * | 2021-04-27 | 2021-08-27 | 西安电子科技大学 | Bandwidth enhanced sample-hold switching circuit for ultra-high-speed analog-to-digital converter |
-
2011
- 2011-04-28 CN CN 201110108268 patent/CN102185596A/en active Pending
Non-Patent Citations (1)
| Title |
|---|
| 《Circuits and Systems (APCCAS), 2010 IEEE Asia Pacific Conference on》 20101209 Guanzhong Huang等 《A fast bootstrapped switch for high-speed high-resolution A/D converter 》 382-385 , * |
Cited By (17)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102386924B (en) * | 2011-09-21 | 2014-01-01 | 北京工业大学 | Low-voltage asynchronous successive approximation analog-to-digital converter |
| CN102386924A (en) * | 2011-09-21 | 2012-03-21 | 北京工业大学 | Low-voltage asynchronous successive approximation analog-to-digital converter and conversion method |
| CN103326700A (en) * | 2013-05-23 | 2013-09-25 | 苏州苏尔达信息科技有限公司 | Bootstrap sampling switch circuit |
| CN103346765A (en) * | 2013-07-09 | 2013-10-09 | 东南大学 | Gate-source following sampling switch |
| CN106063207A (en) * | 2014-03-03 | 2016-10-26 | 高通股份有限公司 | Systems and methods for frequency detection |
| CN106063207B (en) * | 2014-03-03 | 2018-01-05 | 高通股份有限公司 | System and method for frequency detecting |
| CN104113316A (en) * | 2014-05-12 | 2014-10-22 | 西安电子科技大学 | CMOS bootstrapped switch circuit |
| CN104113316B (en) * | 2014-05-12 | 2017-12-08 | 西安电子科技大学 | A kind of CMOS boot-strapped switch circuit |
| CN105119604A (en) * | 2015-09-21 | 2015-12-02 | 东南大学 | Bootstrap switch circuit suitable for sampling of an analog-to-digital converter in a low power and voltage condition |
| CN105119604B (en) * | 2015-09-21 | 2018-04-03 | 东南大学 | A kind of bootstrap switch circuit suitable for the sampling of low supply voltage analog-digital converter |
| CN108696270A (en) * | 2018-05-24 | 2018-10-23 | 上海艾为电子技术股份有限公司 | A kind of analog switching circuit |
| CN108696270B (en) * | 2018-05-24 | 2022-02-01 | 上海艾为电子技术股份有限公司 | Analog switch circuit |
| CN109639133A (en) * | 2018-12-28 | 2019-04-16 | 上海贝岭股份有限公司 | Clock level booster circuit |
| CN112787644A (en) * | 2019-11-11 | 2021-05-11 | 圣邦微电子（北京）股份有限公司 | Bootstrap circuit with power-on reset function |
| CN112787644B (en) * | 2019-11-11 | 2023-01-10 | 圣邦微电子（北京）股份有限公司 | Bootstrap circuit with power-on reset function |
| CN113315505A (en) * | 2021-04-27 | 2021-08-27 | 西安电子科技大学 | Bandwidth enhanced sample-hold switching circuit for ultra-high-speed analog-to-digital converter |
| CN113315505B (en) * | 2021-04-27 | 2022-12-02 | 西安电子科技大学 | Bandwidth-enhanced sample-hold switching circuit for ultra-high-speed analog-to-digital converter |
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Application publication date: 20110914 |