CN110912542B

CN110912542B - Low-power consumption dynamic bias comparator

Info

Publication number: CN110912542B
Application number: CN201911062150.4A
Authority: CN
Inventors: 李宗源; 穆庚; 叶大蔚; 张怡云; 史传进
Original assignee: Fudan University
Current assignee: Fudan University
Priority date: 2019-11-02
Filing date: 2019-11-02
Publication date: 2023-05-02
Anticipated expiration: 2039-11-02
Also published as: CN110912542A

Abstract

The invention belongs to the technical field of analog circuit signal processing, and particularly relates to a low-power consumption dynamic bias comparator. The dynamic bias comparator mainly comprises a preamplifier, a latch and a timing control circuit. According to the invention, by adding the discharging paths and related time sequence control circuits between the tail capacitor Ctail and the reset capacitors Cp1 and Cp2, when the reset phase of the comparator starts, the residual charges on the tail capacitor are transferred to the two reset capacitors, so that the purpose of energy multiplexing is achieved, and the energy efficiency of the comparator is improved; in the timing control circuit, it is ensured that no short circuit occurs in the comparator reset stage.

Description

Low-power consumption dynamic bias comparator

Technical Field

The invention belongs to the technical field of analog circuit signal processing, and particularly relates to a low-power consumption dynamic bias comparator.

Background

The comparator is one of basic analog circuit modules in modern integrated circuit chips, and has wide application in the fields of AD/DA conversion systems, signal detection systems, biomedical electronics and the like. With the development of low-power consumption technology and the continuous improvement of the requirements of people on chip performance, the contradiction between various indexes is more prominent when the performance of a comparator is continuously improved, and particularly the relation between power consumption and speed is more prominent.

To resolve finer voltage differences in the comparator, it is often necessary to reduce the speed of the comparator in exchange for more comparison time, to allow the comparator more time to get the correct result, and this method allows the comparator to be in the on state for a longer time, and thus the more dynamic power consumption. The dynamic bias comparator utilizes the method, and the working state of the input pair tube is changed to enter a subthreshold region, so that the on-state current is reduced, and the dynamic power consumption is saved (for example, A1.2V Dynamic Bias Latch-Type Comparator in 65nm CMOS With 0.4mV Input Noise issued by Harijot et al in the journal of JSSC in 2018). But after the comparison phase is completed, the charge on the tail capacitor is discharged directly to ground, resulting in underutilization of this portion of the charge.

On the premise of not changing the comparison speed of the comparator, the residual electric quantity on the tail capacitor after the comparison phase is finished is needed to be reused for the following reset phase to achieve efficient utilization of energy, and the method is an important method for reducing power consumption in an analog integrated circuit.

Disclosure of Invention

The invention aims to provide a low-power-consumption dynamic bias comparator with good safety and strong operability.

The invention provides a low-power consumption dynamic bias comparator, the circuit structure of which is shown in figure 1, comprising: a preamplifier, a latch and a timing control circuit; wherein:

in the preamplifier, the sources of the input pair transistors M1 and M2 are connected with the drain electrode of the transistor M14, the source electrode of the transistor M14 is connected with the upper polar plate of the tail capacitor Ctail, the lower polar plate of the tail capacitor Ctail is respectively connected with the drain electrode of the transistor M15 and the drain electrode of the transistor M16, the source electrode of the transistor M15 is connected with VDD, and the source electrode of the transistor M16 is grounded; the drains of the input pair transistors M1 and M2 are respectively connected with the drains of the transistor M3 and the transistor M4, the sources of the transistor M3 and the transistor M4 are connected with the drain of the transistor M17 and the upper polar plate of the tail capacitor Ctail, and the source of the transistor M17 is connected with VDD; the drains of the input pair transistors M1 and M2 are respectively connected with upper polar plates of reset capacitors Cp1 and Cp2, and lower polar plates of the reset capacitors Cp1 and Cp2 are grounded; the upper polar plates of the reset capacitors Cp1 and Cp2 are respectively connected with the latch input tubes M11 and M10.

In the latch, sources of the input transistors M11 and M10 are respectively connected to drains of the transistors M13 and M12, sources of the transistors M13 and M12 are connected to VDD, a gate of the transistor M13 is connected to a gate of the transistor M7 and a drain of the transistor M10, a gate of the transistor M12 is connected to a gate of the transistor M8 and a drain of the transistor M11, drains of the transistor M11 are connected to drains of the transistors M5 and M7, drains of the transistor M10 are connected to drains of the transistors M8 and M6, and sources of the transistors M5, M7, M8 and M6 are grounded.

In the time sequence control circuit, a clock signal clk is connected with the gates of transistors M3, M4, M14 and M16, a clkn signal is connected with the gates of transistors M5 and M6, and a clk1 signal is connected with the gate of transistor M15.

In the comparator comparison phase, the charge on the plates of reset capacitors Cp1 and Cp2 charges Ctail through the input to transistors M1 and M2 and on transistor M14, and simultaneously the latch is opened along with the decrease of the voltage on the plates of Cp1 and Cp2, and the results are compared rapidly. In the reset phase, for the conventional dynamic bias comparator, i.e. no transistor M15, the upper electrode plate of the Ctail is not connected to the sources of the transistors M3 and M4, and the drain electrode and the source electrode of the transistor M16 are respectively connected to the upper electrode plate, the lower electrode plate and the source electrode of the Ctail to be grounded, the charge stored in the upper electrode plate of the Ctail after the transistor M16 is turned on is directly discharged to the ground, which causes a loss of power consumption. For the low-power-consumption dynamic bias comparator, in the reset stage, the transistor M16 is disconnected, the connection between Ctail and the ground is cut off, the electric quantity of the upper polar plate of Ctail can be transmitted to the upper polar plates of Cp1 and Cp2 through the on transistors M3 and M4 to charge Cp1 and Cp2, the purpose of energy multiplexing is achieved, and therefore power consumption is saved.

In the pre-amplifier circuit, the lower plate of the tail capacitor Ctail is connected to the drain of the transistor M15, and the source of the transistor M15 is connected to VDD, so that the driving voltage VDD is provided in the reset stage of the comparator. The power supply voltage to which transistor M17 is connected, the voltages on Cp1 and Cp2 are eventually charged to VDD through turned-on transistors M17 and M3, M4 to ensure that the next comparison has the same initial state as the previous comparison.

In the timing control circuit, before the reset phase of the comparator starts, the clock signal clk is changed into a low level, the transistor M16 is turned off, the path between the Ctail and the ground is cut off, then the clock signal clk1 is changed into a low level, and the reset phase starts, so that the short circuit condition can not occur in the switching process of the switch. Similarly, at the end of the reset phase, the clock signal clk1 first goes high, and then the clock signal clk goes high, which also ensures that no short circuit occurs.

The low-power-consumption dynamic bias comparator provided by the invention is characterized in that a connecting passage between the upper polar plate of the tail capacitor Ctail and the reset capacitors Cp1 and Cp2 is constructed, namely, the residual electric quantity on the tail capacitor can be transferred to the reset capacitor in a reset stage through the transistors M3 and M4, so that the residual electric quantity is utilized in the next comparison stage, and the power consumption consumed on the original tail capacitor is saved.

The invention ensures the simplicity and operability of the sequential logic circuit on the basis of further reducing the power consumption of the comparator.

Drawings

Fig. 1 is a schematic diagram of a low power dynamic bias comparator circuit.

Fig. 2 is a simplified schematic diagram of the comparator comparing stage.

Fig. 3 is a simplified schematic diagram of the comparator reset stage operating circuit.

FIG. 4 is a timing diagram of clock signals.

Description of the embodiments

The invention aims to achieve the purpose of saving the power consumption of the dynamic bias comparator by multiplexing the residual electric quantity on the tail capacitor.

Fig. 2 shows a simplified structure of the comparison phase of the dynamic bias comparator. The upper plates of the reset capacitors Cp1 and Cp2 have been charged to the supply voltage VDD during the reset phase. Firstly, the clock signal clk1 becomes high level firstly, so that Ctail is disconnected from the power supply voltage, and then becomes high level again, so that the lower polar plate of the Ctail is grounded, and the condition that the circuit is short-circuited is avoided is ensured. Next, cp1 and Cp2 charge the upper plate of tail capacitor Ctail via input to transistors M1, M2, respectively, and then via transistor M14. Along with the rising of the pole plate voltage on the tail capacitor, the input pair-pipe grid source voltage is reduced, and the input pair-pipe gradually enters a subthreshold state. At the same time, the decrease in the plate voltage on Cp1, cp2 results in transistors M11 and M10 turning on, causing the latch to open, enter a latched state, and rapidly compare the results. After which a reset phase is entered.

Fig. 3 shows a simplified structure of the reset phase. First, the clock signal clk goes low and clk1 goes low at small intervals to ensure that no short circuit occurs during switching. At this time, the power supply voltage VDD is connected to the lower plate of the Ctail through the turned-on transistor M15, and drives the Ctail to flow the charges of the upper plate into the upper plates of the Cp1 and Cp2 through the turned-on transistors M3 and M4, charge the reset capacitor, and multiplex the charges remaining on the upper plate of the Ctail. And the power supply voltage charges Cp1 and Cp2 through the M17 transistor at the same time, so that the voltage of the upper polar plate of the reset capacitor is VDD when the reset phase is finished, and the reset is complete. In addition, in the reset phase, the clock signal clkn goes high, causing the latch to be reset.

The invention only adds two transistor switches on the basis of the dynamic bias comparator, thus causing little increase of power consumption, and in addition, although energy loss exists in the process of moving the electrode plate charge on the Ctail, the sum of the two is far smaller than the saved power consumption, so the total power consumption performance of the comparator is improved.

The clock signal clkn is inverted from clk. Fig. 4 shows a timing diagram of clk, clkn, and clk 1.

Claims

1. A low power dynamic bias comparator, the comparator circuit comprising: a preamplifier, a latch and a timing control circuit; wherein:

in the preamplifier, the sources of the input pair transistors M1 and M2 are connected with the drain electrode of the transistor M14, the source electrode of the transistor M14 is connected with the upper polar plate of the tail capacitor Ctail, the lower polar plate of the tail capacitor Ctail is respectively connected with the drain electrode of the transistor M15 and the drain electrode of the transistor M16, the source electrode of the transistor M15 is connected with VDD, and the source electrode of the transistor M16 is grounded; the drains of the input pair transistors M1 and M2 are respectively connected with the drains of the transistor M3 and the transistor M4, the sources of the transistor M3 and the transistor M4 are connected with the drain of the transistor M17 and the upper polar plate of the tail capacitor Ctail, and the source of the transistor M17 is connected with VDD; the drains of the input pair transistors M1 and M2 are respectively connected with upper polar plates of reset capacitors Cp1 and Cp2, and lower polar plates of the reset capacitors Cp1 and Cp2 are grounded; the upper polar plates of the reset capacitors Cp1 and Cp2 are respectively connected with latch input tubes M11 and M10;

in the latch, sources of an input transistor pair M11 and M10 are respectively connected with drains of transistors M13 and M12, sources of the transistors M13 and M12 are connected with VDD, a grid of the transistor M13 is connected with a grid of a transistor M7 and a drain of a transistor M10, a grid of the transistor M12 is connected with a grid of a transistor M8 and a drain of a transistor M11, drains of the transistor M11 are connected with drains of transistors M5 and M7, drains of the transistor M10 are connected with drains of transistors M8 and M6, and sources of the transistors M5, M7, M8 and M6 are grounded;

in the timing control circuit, a clock signal clk is connected to the gates of the transistors M3, M4, M14, and M16, a clock signal clkn is connected to the gates of the transistors M5 and M6, and a clock signal clk1 is connected to the gate of the transistor M15.

2. The low power dynamic bias comparator according to claim 1, wherein during the comparator comparison phase, the charge on the plates of reset capacitors Cp1 and Cp2 charges Ctail through the input to transistors M1, M2 and on transistor M14, and the latch is opened as the voltage on the plates of Cp1 and Cp2 decreases, and the result is compared rapidly; in the reset stage, the transistor M16 is disconnected, the connection between Ctail and the ground is cut off, the electric quantity of the upper polar plate of Ctail is transmitted to the upper polar plates of Cp1 and Cp2 through the on transistors M3 and M4, and Cp1 and Cp2 are charged, so that the purpose of energy multiplexing is achieved, and the power consumption is saved.

3. The low power consumption dynamic bias comparator according to claim 1, wherein in the pre-amplifier circuit, a lower plate of the tail capacitor Ctail is connected to a drain of the transistor M15, and a source of the transistor M15 is connected to VDD, so that the driving voltage VDD is provided in a reset phase of the comparator; the power supply voltage connected to the transistor M17 charges the voltages on Cp1 and Cp2 to VDD finally through the turned-on transistors M17 and M3, M4, ensuring that the next comparison has the same initial state as the previous comparison.

4. The low power consumption dynamic bias comparator according to claim 1, wherein in the timing control circuit, before the start of the comparator reset phase, the clock signal clk first goes low, turns off the transistor M16, cuts off the path between the Ctail and ground, and then the clock signal clk1 goes low; starting a reset stage, and ensuring that a short circuit condition does not occur in the switching process of the switch; similarly, at the end of the reset phase, the clock signal clk1 changes to the high level first, and then the clock signal clk changes to the high level, so as to ensure that no short circuit occurs.