CN111525791B - Low-voltage high-conversion-efficiency charge pump circuit - Google Patents

Abstract

The invention discloses a low-voltage high-conversion-efficiency charge pump circuit. By adjusting the respective gate voltage clock signals of four MOS transistors of a traditional cross-coupled charge pump to reduce leakage current and conduction loss, firstly add two auxiliary capacitors and Two auxiliary clocks are used to generate the clock for driving the NMOS tube to avoid the leakage current caused by the overlap of the charge pump clocks. Secondly, two inverters are added and the highest and lowest voltages of the inverters are changed to achieve a high-swing driving clock. To drive the PMOS transistor to reduce conduction losses. Therefore, the charge pump circuit can work at a lower voltage, and at the same time, a higher power conversion efficiency can be obtained.

Description

A low voltage high conversion efficiency charge pump circuit

technical field

The invention belongs to the field of charge pump circuits, in particular to a charge pump circuit capable of realizing low voltage and high conversion efficiency.

Background technique

The charge pump module is an important module in the energy harvesting system, and the charge pump circuit mainly plays the role of boosting in the energy harvesting system. Due to the low input voltage of the energy harvesting system, the energy that can be harvested is very limited, so it is very important to design a charge pump circuit with low input voltage and high conversion efficiency. Therefore, the present invention proposes a charge pump circuit capable of realizing low voltage and high conversion efficiency, and the circuit can be applied to an energy harvesting system.

Existing mainstream charge pump circuits include Dickson charge pump and cross-coupled charge pump. Dickson's output voltage is lower due to threshold losses and affects conversion efficiency. The cross-coupled charge pump eliminates the influence of the threshold loss in the Dickson charge pump through the alternate conduction of the two branches, but the traditional cross-coupled charge pump will generate leakage current when the clocks overlap and the VGS swing of the switch MOS tube is not large enough. The resulting conduction loss will reduce its conversion efficiency.

SUMMARY OF THE INVENTION

Purpose of the invention: The purpose of the present invention is to propose a charge pump circuit capable of realizing low voltage and high conversion efficiency. As a basic unit of an energy harvesting circuit, the circuit can realize a charge pump with low voltage and high conversion efficiency.

The present invention proposes a low-voltage high-conversion-efficiency charge pump circuit. The main idea of the design is to add two auxiliary capacitors and two auxiliary clocks to generate a clock for driving an NMOS tube, so as to avoid leakage current caused by the overlapping of the charge pump clocks, and at the same time Add two inverters and change the highest and lowest voltages of the inverters to achieve a high-swing drive clock to drive the PMOS tube to reduce conduction losses.

Technical scheme: in order to solve the above-mentioned technical problems, the present invention adopts the following technical scheme:

A charge pump circuit with low voltage and high conversion efficiency, the charge pump circuit is composed of a cross-coupled charge pump, a first inverter and a second inverter, first and second auxiliary capacitors and first and second auxiliary NMOS transistors ;

The cross-coupled charge pump consists of first and second NMOS transistors, first and second PMOS transistors, and first and second capacitors. The first inverter consists of a fifth NMOS transistor and a third PMOS transistor. The second inverter consists of a fifth NMOS transistor and a third PMOS transistor. The device is composed of the sixth NMOS tube and the fourth PMOS tube;

The input end of the charge pump circuit is respectively connected with the drain and substrate of the first NMOS transistor, the drain and substrate of the second NMOS transistor, the drain and substrate of the first auxiliary NMOS transistor, and the drain of the second auxiliary NMOS transistor. The electrode is connected to the substrate; the source of the first NMOS tube is respectively connected to the gate of the first auxiliary NMOS tube, the source of the first PMOS tube, the source of the fourth PMOS tube and the lower plate of the first capacitor; The gate of an NMOS transistor is respectively connected to the source of the first auxiliary NMOS transistor and the upper plate of the first auxiliary capacitor; the upper plate of the first capacitor is connected to the first clock signal; the lower plate of the first auxiliary capacitor is connected to the The second auxiliary clock signal is connected; the source of the fifth NMOS tube is connected to the substrate and then connected to the second clock signal; the drain of the fifth NMOS tube is connected to the drain of the third PMOS tube and then connected to the first PMOS tube The gate is connected to the gate; the gate of the fifth NMOS tube is connected to the gate of the third PMOS tube and then connected to the first clock signal; the source of the second NMOS tube is respectively connected to the gate of the second auxiliary NMOS tube, the second PMOS tube The source of the third PMOS tube is connected to the upper plate of the second capacitor; the gate of the second NMOS tube is connected to the source of the second auxiliary NMOS tube and the upper plate of the second auxiliary capacitor respectively; The lower plate of the second auxiliary capacitor is connected with the first auxiliary clock signal; the lower plate of the second capacitor is connected with the second clock signal; the source of the sixth NMOS tube is connected with the substrate and connected with the first clock signal; The drain of the six NMOS tubes is connected to the drain of the fourth PMOS tube and then connected to the gate of the second PMOS tube; the gate of the sixth NMOS tube is connected to the gate of the fourth PMOS tube and then connected to the second clock signal; The substrate and drain of the first PMOS transistor, the substrate of the third PMOS transistor, the substrate of the fourth PMOS transistor, and the drain and the substrate of the second PMOS transistor are connected to the output end of the charge pump circuit. .

Beneficial effect: Compared with the existing technology, the present invention has the following advantages:

The low-voltage and high-conversion-efficiency charge pump circuit proposed by the invention changes the driving signal of the switch tube on the basis of the traditional cross-coupled charge pump, reduces the leakage current and conduction loss of the traditional cross-coupled charge pump circuit, and can realize high-conversion efficiency charge For the pump, due to the increase of the clock swing of the PMOS switch tube, the present invention can work normally under a lower input voltage, and at the same time, compared with using four auxiliary capacitors, the layout area is reduced.

Description of drawings

1 is a circuit topology diagram of the present invention;

Fig. 2 is the sequence diagram of the present invention;

Fig. 3 is the change curve of the output voltage with the input voltage when the load current of the charge pump realized by the present invention is 100 μA;

Fig. 4 is the change curve of the conversion efficiency with the input voltage when the load current of the charge pump realized by the present invention is 100 μA;

Fig. 5 is the change curve of the output voltage with the load current when the input voltage of the charge pump realized by the present invention is 0.55V.

Fig. 6 is the change curve of the conversion efficiency with the load current when the input voltage of the charge pump realized by the present invention is 0.55V.

Detailed ways

The present invention will be further described below with reference to the accompanying drawings.

As shown in Figure 1, a low-voltage high-conversion-efficiency charge pump circuit consists of the basic circuit structure of a cross-coupled charge pump, two inverters INV1 and INV2, two auxiliary capacitors and two auxiliary NMOS transistors. On the basis of the traditional cross-coupled charge pump, the driving signal of the switch tube is changed, the leakage current and conduction loss of the traditional cross-coupled charge pump circuit are reduced, and a low-voltage high-conversion-efficiency charge pump can be realized.

The input signals of the charge pump circuit are VIN, CLKA, CLKB, CLK2A, CLK2B, and the overall output signal of the circuit is VOUT.

The basic circuit structure of the cross-coupled charge pump is composed of MN1, MN2, MP1, MP2, C1, and C2. The inverter INV1 is composed of MN5 and MP3. The inverter INV2 is composed of MN6 and MP4. The two auxiliary capacitors are Cs1, Cs2, the two auxiliary MOS transistors are MN3 and MN4, of which MN1, MN2, MN3, MN4, MN5, and MN6 are NMOS transistors, MP1, MP2, MP3, and MP4 are PMOS transistors, and C1, C2, Cs1, and Cs2 are capacitors.

The input terminals of the charge pump circuit are respectively connected with the signal VIN, the drain and substrate of MN1, the drain and substrate of MN2, the drain and substrate of MN3, and the drain and substrate of MN4; the source of MN1 They are respectively connected to the gate of MN3, the source of MP1, the source of MP4 and the lower plate of C1; the gate of MN1 is respectively connected to the source of MN3 and the upper plate of Cs1; the lower plate of Cs1 is connected to the clock signal CLK2B is connected; the upper plate of C1 is connected to the clock signal CLKA; the source of MN5 is connected to the substrate and then connected to the clock signal CLKB; the drain of MN5 is connected to the drain of MP3 and is connected to the gate of MP1; The gate is connected to the gate of MP3 and then connected to the clock signal CLKA; the source of MN2 is respectively connected to the gate of MN4, the source of MP2, the source of MP3 and the lower plate of C2; the gate of MN2 is respectively connected to MN4 The source of MN6 is connected to the upper plate of Cs2; the lower plate of C2 is connected to the clock signal CLKB; the lower plate of Cs2 is connected to the clock signal CLK2A; the source of MN6 is connected to the substrate and connected to the clock signal CLKA; MN6 The drain of MN6 is connected to the drain of MP4 and then connected to the gate of MP2; the gate of MN6 is connected to the gate of MP4 and then connected to the clock signal CLKB; the substrate and drain of MP1, the substrate of MP3, the substrate of MP4 The bottom and the drain of MP2 are connected to the substrate and then connected to the output end of the charge pump circuit.

The low-voltage high-conversion-efficiency charge pump circuit proposed by the present invention can effectively reduce the leakage current and conduction loss of the cross-coupled charge-pump circuit, thereby reducing the minimum input voltage, improving the conversion efficiency, and reducing the layout area. Cost savings. The proposed circuit structure can be used in energy harvesting systems. The working principle is described in detail below in conjunction with the specific circuit and simulation results.

Combined with the timing diagram in Figure 2, when CLKA is 0 in ① interval, MN3 is turned off, and CLK2B is VIN at this time. Before that, A2 will be charged to VIN, so A2 will be raised to 2VIN at this time, MN1 will be turned on, and point A Charge to VIN, and because CLKB is VIN, so MN6 is turned on, P2 is 0, MP2 is turned on. When CLKB is VIN, the level of point B is raised to 2VIN, MN4 is turned on, B2 will be charged to VIN, CLK2A is 0, MN2 is turned off, and because CLKA is 0, MP3 is turned on, P1 is 2VIN, MP1 off.

In the ② interval, when CLKA is 0, MN3 is turned off. At this time, CLK2B is 0, A2 will not be raised, and it is still VIN, and MN1 is turned off. At this time, point A is VIN, and because CLKB is VIN, MN6 is turned on, and P2 If it is 0, MP2 is turned on. When CLKB is VIN, point B is raised to 2VIN, MN4 is turned on, B2 will be charged to VIN, so MN2 is turned on, point A is charged to VIN, and since CLKA is 0, MP3 is turned on, P1 is 2VIN, MP1 off.

When CLKA is VIN in ③ interval, point A is raised to 2VIN, MN3 is turned on, CLK2B is 0, A2 is VIN, MN1 is turned off, and because CLKB is VIN, MP4 is turned on, P2 is 2VIN, and MP2 is turned off. When CLKB is VIN, point B is raised to 2VIN, MN4 is turned on, CLK2A is 0, B2 is VIN, MN2 is turned off, and because CLKA is VIN, MP3 is turned on, P1 is 2VIN, and MP1 is turned off.

In the ④ interval, when CLKA is VIN, point A will be raised to 2VIN, MN3 is turned on, CLK2B is 0, A2 is VIN, MN1 is turned off, and because CLKB is 0, MP4 is turned on, P2 is 2VIN, and MP2 is turned off . When CLKB is 0, B is VIN, MN4 is turned off, CLK2A is 0, B2 is VIN, MN2 is turned off, and because CLKA is VIN, MN5 is turned on, P1 is 0, and MP1 is turned on.

In the ⑤ interval, when CLKA is VIN, point A will be raised to 2VIN, MN3 is turned on, CLK2B is 0, A2 is VIN, MN1 is turned off, and because CLKB is 0, MP4 is turned on, P2 is 2VIN, MP2 is turned off break. When CLKB is 0, MN4 is turned off, CLK2A is VIN, B2 is raised to 2VIN, MN2 is turned on, point B is charged to VIN, and since CLKA is VIN, MN5 is turned on, P1 is 0, and MP1 is turned on.

Through the above analysis, it can be found that when point A is VIN, MP1 is always turned off; when point A is 2VIN, MN1 is always turned off; when point B is VIN, MP2 is always turned off; When the point is 2VIN, MN2 is always turned off; MN1 and MP1 are not turned on at the same time, and MN2 and MP2 are not turned on at the same time, which effectively avoids the occurrence of leakage current. At the same time, it can be found that the swings of P1 and P2 are both from 0 to 2VIN, which effectively increases the clock swing of the PMOS switch, thereby reducing the conduction loss and reducing the minimum input voltage.

FIG. 3 is a graph showing the variation curve of the output voltage with the input voltage when the load current of the charge pump implemented by the present invention is 100 μA. As the input voltage increases, the output voltage also increases. Comparing the four curves, it is found that only the present invention can work normally at a lower input voltage.

FIG. 4 is a graph showing the variation curve of the conversion efficiency with the input voltage when the load current of the charge pump realized by the present invention is 100 μA. Each curve has peak efficiency. Comparing the four curves, it is found that the present invention has the highest efficiency at low voltage, and when the input voltage is higher than 0.4V, the conversion efficiency is higher than 70%.

Fig. 5 is the change curve of the output voltage with the load current when the input voltage of the charge pump realized by the present invention is 0.55V. As the load current increases, the output voltage decreases accordingly. Comparing the four curves, it is found that the output voltage of the present invention under heavy load is significantly higher than other curves.

FIG. 6 is a curve showing the change of the conversion efficiency with the input voltage when the input voltage of the charge pump realized by the present invention is 0.55V. Each curve has a peak efficiency. Comparing the four curves, it is found that the peak efficiency of the present invention is the highest, and under heavy load conditions, the efficiency is significantly higher than other curves.

Claims (1)

1. A low-voltage high-conversion-efficiency charge pump circuit, characterized in that: the charge pump circuit consists of a cross-coupled charge pump, a first inverter and a second inverter, first and second auxiliary capacitors, and first and second auxiliary capacitors. The second auxiliary NMOS tube is composed; The cross-coupled charge pump consists of first and second NMOS transistors, first and second PMOS transistors, and first and second capacitors. The first inverter consists of a fifth NMOS transistor and a third PMOS transistor. The second inverter consists of a fifth NMOS transistor and a third PMOS transistor. The device is composed of the sixth NMOS tube and the fourth PMOS tube; The input end of the charge pump circuit is respectively connected with the drain and substrate of the first NMOS transistor, the drain and substrate of the second NMOS transistor, the drain and substrate of the first auxiliary NMOS transistor, and the drain of the second auxiliary NMOS transistor. The electrode is connected to the substrate; the source of the first NMOS tube is respectively connected to the gate of the first auxiliary NMOS tube, the source of the first PMOS tube, the source of the fourth PMOS tube and the lower plate of the first capacitor; The gate of an NMOS transistor is respectively connected to the source of the first auxiliary NMOS transistor and the upper plate of the first auxiliary capacitor; the upper plate of the first capacitor is connected to the first clock signal; the lower plate of the first auxiliary capacitor is connected to the The second auxiliary clock signal is connected; the source of the fifth NMOS tube is connected to the substrate and then connected to the second clock signal; the drain of the fifth NMOS tube is connected to the drain of the third PMOS tube and then connected to the first PMOS tube The gate is connected to the gate; the gate of the fifth NMOS tube is connected to the gate of the third PMOS tube and then connected to the first clock signal; the source of the second NMOS tube is respectively connected to the gate of the second auxiliary NMOS tube, the second PMOS tube The source of the third PMOS tube is connected to the upper plate of the second capacitor; the gate of the second NMOS tube is connected to the source of the second auxiliary NMOS tube and the upper plate of the second auxiliary capacitor respectively; The lower plate of the second auxiliary capacitor is connected with the first auxiliary clock signal; the lower plate of the second capacitor is connected with the second clock signal; the source of the sixth NMOS tube is connected with the substrate and connected with the first clock signal; The drain of the six NMOS tubes is connected to the drain of the fourth PMOS tube and then connected to the gate of the second PMOS tube; the gate of the sixth NMOS tube is connected to the gate of the fourth PMOS tube and then connected to the second clock signal; The substrate and drain of the first PMOS transistor, the substrate of the third PMOS transistor, the substrate of the fourth PMOS transistor, and the drain and the substrate of the second PMOS transistor are connected to the output end of the charge pump circuit. .

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