CN111525791B - Low-voltage high-conversion-efficiency charge pump circuit - Google Patents

Abstract

The invention discloses a low-voltage high-conversion-efficiency charge pump circuit, which reduces leakage current and conduction loss by adjusting respective gate voltage clock signals of four MOS (metal oxide semiconductor) tubes of a traditional cross-coupled charge pump. Thereby enabling the charge pump circuit to operate at lower voltages while achieving higher power conversion efficiency.

Description

Low-voltage high-conversion-efficiency charge pump circuit

Technical Field

The invention belongs to the field of charge pump circuits, and particularly relates to a charge pump circuit capable of realizing low voltage and high conversion efficiency.

Background

The charge pump module is an important module in an energy acquisition system, and a charge pump circuit mainly plays a role in boosting in the energy acquisition system. Because the input voltage of the energy collection system is low, the energy capable of being collected is very limited, and therefore, the design of a charge pump circuit with low input voltage and high conversion efficiency is very important. Therefore, the invention provides a charge pump circuit capable of realizing low voltage and high conversion efficiency, and the charge pump circuit can be applied to an energy acquisition system.

The existing mainstream charge pump circuit comprises a Dickson charge pump and a cross-coupling charge pump. Dickson has a low output voltage due to threshold loss and affects conversion efficiency. The cross-coupled charge pump eliminates the influence of threshold loss in the Dickson charge pump through the alternate conduction of the two branches, but the traditional cross-coupled charge pump can generate leakage current when clocks are overlapped and the VGS swing of the switching MOS tube is not large enough, so that the conduction loss can reduce the conversion efficiency of the traditional cross-coupled charge pump.

Disclosure of Invention

The purpose of the invention is as follows: the invention aims to provide a charge pump circuit capable of realizing low voltage and high conversion efficiency, which is used as a basic unit of an energy acquisition circuit and can realize a charge pump with low voltage and high conversion efficiency.

The invention provides a low-voltage high-conversion-efficiency charge pump circuit, which is mainly designed by adding two auxiliary capacitors and two auxiliary clocks to generate a clock for driving an NMOS (N-channel metal oxide semiconductor) tube so as to avoid leakage current caused by overlapping clocks of the charge pump, and simultaneously adding two phase inverters and changing the highest voltage and the lowest voltage of the phase inverters to realize that a high-swing driving clock drives a PMOS tube so as to reduce conduction loss.

The technical scheme is as follows: in order to solve the technical problems, the invention adopts the following technical scheme:

a low-voltage high-conversion-efficiency charge pump circuit is composed of a cross-coupled charge pump, a first inverter, a second inverter, a first auxiliary capacitor, a second auxiliary capacitor, a first auxiliary NMOS transistor and a second auxiliary NMOS transistor;

the cross-coupling charge pump consists of a first NMOS tube, a second NMOS tube, a first PMOS tube, a second PMOS tube, a first capacitor and a second capacitor, the first phase inverter consists of a fifth NMOS tube and a third PMOS tube, and the second phase inverter consists of a sixth NMOS tube and a fourth PMOS tube;

the input end of the charge pump circuit is respectively connected with the drain electrode and the substrate of the first NMOS tube, the drain electrode and the substrate of the second NMOS tube, the drain electrode and the substrate of the first auxiliary NMOS tube, and the drain electrode and the substrate of the second auxiliary NMOS tube; the source electrode of the first NMOS tube is respectively connected with the grid electrode of the first auxiliary NMOS tube, the source electrode of the first PMOS tube, the source electrode of the fourth PMOS tube and the lower pole plate of the first capacitor; the grid electrode of the first NMOS tube is respectively connected with the source electrode of the first auxiliary NMOS tube and the upper polar plate of the first auxiliary capacitor; the upper polar plate of the first capacitor is connected with a first clock signal; the lower pole plate of the first auxiliary capacitor is connected with a second auxiliary clock signal; the source electrode of the fifth NMOS tube is connected with the substrate and then connected with a second clock signal; the drain electrode of the fifth NMOS tube is connected with the drain electrode of the third PMOS tube and then is connected with the grid electrode of the first PMOS tube; the grid electrode of the fifth NMOS tube is connected with the grid electrode of the third PMOS tube and then is connected with the first clock signal; the source electrode of the second NMOS tube is respectively connected with the grid electrode of the second auxiliary NMOS tube, the source electrode of the second PMOS tube, the source electrode of the third PMOS tube and the upper polar plate of the second capacitor; the grid electrode of the second NMOS tube is respectively connected with the source electrode of the second auxiliary NMOS tube and the upper polar plate of the second auxiliary capacitor; the lower pole plate of the second auxiliary capacitor is connected with the first auxiliary clock signal; the lower pole plate of the second capacitor is connected with a second clock signal; the source electrode of the sixth NMOS tube is connected with the substrate and then connected with the first clock signal; the drain electrode of the sixth NMOS tube is connected with the drain electrode of the fourth PMOS tube and then is connected with the grid electrode of the second PMOS tube; the grid electrode of the sixth NMOS tube is connected with the grid electrode of the fourth PMOS tube and then is connected with a second clock signal; the substrate and the drain electrode of the first PMOS tube, the substrate of the third PMOS tube, the substrate of the fourth PMOS tube, and the drain electrode and the substrate of the second PMOS tube are connected and then connected with the output end of the charge pump circuit.

Has the advantages that: compared with the prior art, the invention has the following advantages:

the low-voltage high-conversion-efficiency charge pump circuit provided by the invention changes the driving signal of the switching tube on the basis of the traditional cross-coupled charge pump, reduces the leakage current and conduction loss of the traditional cross-coupled charge pump circuit, can realize the high-conversion-efficiency charge pump, can normally work under lower input voltage due to the increase of the clock swing of the PMOS switching tube, and simultaneously reduces the layout area compared with the use of four auxiliary capacitors.

Drawings

FIG. 1 is a circuit topology of the present invention;

FIG. 2 is a timing diagram of the present invention;

FIG. 3 is a curve of the variation of the output voltage with the input voltage of the charge pump implemented by the present invention when the load current is 100 μ A;

FIG. 4 is a curve of the conversion efficiency of a charge pump implemented by the present invention with respect to the input voltage at a load current of 100 μ A;

fig. 5 is a curve of the output voltage of the charge pump with the load current when the input voltage is 0.55V.

Fig. 6 is a curve of the conversion efficiency of the charge pump implemented by the invention with the change of the load current when the input voltage is 0.55V.

Detailed Description

The invention is further described below with reference to the accompanying drawings.

As shown in fig. 1, a charge pump circuit with low voltage and high conversion efficiency is composed of a basic circuit structure of a cross-coupled charge pump, two inverters INV1 and INV2, two auxiliary capacitors and two auxiliary NMOS transistors. The driving signal of the switching tube is changed on the basis of the traditional cross-coupling charge pump, so that the leakage current and the conduction loss of the traditional cross-coupling charge pump circuit are reduced, and the charge pump with low voltage and high conversion efficiency can be realized.

The input signals of the charge pump circuit are VIN, CLKA, CLKB, CLK2A and CLK2B, and the output signal of the whole circuit is VOUT.

The basic circuit structure of the cross-coupled charge pump is composed of MN1, MN2, MP1, MP2, C1 and C2, an inverter INV1 is composed of MN5 and MP3, an inverter INV2 is composed of MN6 and MP4, two auxiliary capacitors are Cs1 and Cs2 respectively, two auxiliary MOS transistors are MN3 and MN4 respectively, wherein MN1, MN2, MN3, MN4, MN5 and MN6 are NMOS transistors, MP1, MP2, MP3 and MP4 are PMOS transistors, and C1, C2, Cs1 and Cs2 are capacitors.

The input end of the charge pump circuit is respectively connected with the signals VIN, the drain electrode and the substrate of MN1, the drain electrode and the substrate of MN2, the drain electrode and the substrate of MN3 and the drain electrode and the substrate of MN 4; the source electrode of MN1 is respectively connected with the gate electrode of MN3, the source electrode of MP1, the source electrode of MP4 and the lower plate electrode of C1; the gate of MN1 is respectively connected with the source of MN3 and the upper plate of Cs 1; the lower plate of Cs1 is connected to clock signal CLK 2B; the upper plate of C1 is connected to clock signal CLKA; the source electrode and the substrate of the MN5 are connected and then connected with a clock signal CLKB; the drain electrode of the MN5 is connected with the drain electrode of the MP3 and then is connected with the gate electrode of the MP 1; the gate of MN5 is connected with the gate of MP3 and then connected with a clock signal CLKA; the source electrode of MN2 is respectively connected with the gate electrode of MN4, the source electrode of MP2, the source electrode of MP3 and the lower plate electrode of C2; the gate of MN2 is respectively connected with the source of MN4 and the upper plate of Cs 2; the lower plate of C2 is connected to clock signal CLKB; the lower plate of Cs2 is connected to clock signal CLK 2A; the source electrode of the MN6 is connected with the substrate and then connected with a clock signal CLKA; the drain electrode of the MN6 is connected with the drain electrode of the MP4 and then is connected with the gate electrode of the MP 2; the gate of MN6 is connected with the gate of MP4 and then connected with a clock signal CLKB; the substrate and the drain of the MP1, the substrate of the MP3, the substrate of the MP4 and the drain and the substrate of the MP2 are connected with the output end of the charge pump circuit.

The low-voltage high-conversion-efficiency charge pump circuit provided by the invention can effectively reduce the leakage current and conduction loss of the cross-coupled charge pump circuit, thereby reducing the lowest input voltage, improving the conversion efficiency, reducing the layout area and saving the cost. The proposed circuit structure can be applied in energy harvesting systems. The operation principle of the simulation method is described in detail below with reference to specific circuits and simulation results.

With reference to the timing diagram of fig. 2, when the section CLKA is 0, MN3 is turned off, and CLK2B is VIN, and a2 is charged to VIN before this time, so a2 is raised to 2VIN, MN1 is turned on, and point a is charged to VIN, and since CLKB is VIN, MN6 is turned on, P2 is 0, and MP2 is turned on. When CLKB is VIN, the level of B point is raised to 2VIN, MN4 is turned on, B2 is charged to VIN, CLK2A is 0, MN2 is turned off, and since CLKA is 0, MP3 is turned on, P1 is 2VIN, and MP1 is turned off.

When the CLKA is 0, MN3 is turned off, CLK2B is 0 at this time, a2 is not lifted and still is VIN, MN1 is turned off, point a is VIN at this time, and since CLKB is VIN, MN6 is turned on, P2 is 0, and MP2 is turned on. When CLKB is VIN, point B is raised to 2VIN, MN4 is turned on, B2 is charged to VIN, so MN2 is turned on, point a is charged to VIN, and since CLKA is 0, MP3 is turned on, P1 is 2VIN, and MP1 is turned off.

When the CLKA of the interval (c) is VIN, the point a is raised to 2VIN, MN3 is turned on, CLK2B is 0, a2 is VIN, MN1 is turned off, and since CLKB is VIN, MP4 is turned on, P2 is 2VIN, and MP2 is turned off. When CLKB is VIN, point B is raised to 2VIN, MN4 is on, CLK2A is 0, B2 is VIN, MN2 is off, and since CLKA is VIN, MP3 is on, P1 is 2VIN, and MP1 is off.

When the CLKA is VIN, the point a is raised to 2VIN, MN3 is turned on, CLK2B is 0, a2 is VIN, MN1 is turned off, and since CLKB is 0, MP4 is turned on, P2 is 2VIN, and MP2 is turned off. When CLKB is 0, B is VIN, MN4 is off, CLK2A is 0, B2 is VIN, MN2 is off, and since CLKA is VIN, MN5 is on, P1 is 0, and MP1 is on.

When CLKA is VIN, point a is raised to 2VIN, MN3 is on, CLK2B is 0, a2 is VIN, MN1 is off, and since CLKB is 0, MP4 is on, P2 point is 2VIN, MP2 is off. When CLKB is 0, MN4 is turned off, CLK2A is VIN, B2 is raised to 2VIN, MN2 is turned on, point B is charged to VIN, MN5 is turned on, P1 is 0, and MP1 is turned on.

From the above analysis, it can be found that when the point a is VIN, MP1 is always off; when point a is 2VIN, MN1 is always off; when the point B is VIN, MP2 is always turned off; when point B is 2VIN, MN2 is always off; MN1 and MP1 are not conducted at the same time, and MN2 and MP2 are not conducted at the same time, so that the leakage current is effectively avoided. Meanwhile, the swing of the points P1 and P2 is from 0 to 2VIN, so that the clock swing of the PMOS switching tube is effectively increased, the conduction loss is reduced, and the lowest input voltage is reduced.

Fig. 3 is a curve of the variation of the output voltage with the input voltage of the charge pump realized by the invention when the load current is 100 mua. With the increase of the input voltage, the output voltage also increases, and comparing the four curves shows that only the invention can work normally under the lower input voltage.

Fig. 4 is a curve of conversion efficiency of a charge pump implemented by the present invention with respect to input voltage at a load current of 100 μ a. The peak efficiency of each curve exists, and the comparison of the four curves shows that the efficiency of the invention is highest at low voltage, and when the input voltage is higher than 0.4V, the conversion efficiency is higher than 70%.

Fig. 5 is a curve of the output voltage of the charge pump with the load current when the input voltage is 0.55V. The output voltage is reduced along with the increase of the load current, and the comparison of the four curves shows that the output voltage of the invention is obviously higher than that of other curves under the heavy load.

Fig. 6 is a curve of conversion efficiency of a charge pump implemented by the invention with respect to an input voltage when the input voltage is 0.55V. The peak efficiency of each curve is found by comparing the four curves, and the peak efficiency of the invention is the highest and the efficiency is obviously higher than that of other curves under the heavy load condition.

Claims (1)

1. A low-voltage high-conversion-efficiency charge pump circuit is characterized in that: the charge pump circuit consists of a cross-coupled charge pump, a first phase inverter, a second phase inverter, a first auxiliary capacitor, a second auxiliary capacitor, a first auxiliary NMOS tube and a second auxiliary NMOS tube;

the cross-coupling charge pump consists of a first NMOS tube, a second NMOS tube, a first PMOS tube, a second PMOS tube, a first capacitor and a second capacitor, the first phase inverter consists of a fifth NMOS tube and a third PMOS tube, and the second phase inverter consists of a sixth NMOS tube and a fourth PMOS tube;

the input end of the charge pump circuit is respectively connected with the drain electrode and the substrate of the first NMOS tube, the drain electrode and the substrate of the second NMOS tube, the drain electrode and the substrate of the first auxiliary NMOS tube, and the drain electrode and the substrate of the second auxiliary NMOS tube; the source electrode of the first NMOS tube is respectively connected with the grid electrode of the first auxiliary NMOS tube, the source electrode of the first PMOS tube, the source electrode of the fourth PMOS tube and the lower pole plate of the first capacitor; the grid electrode of the first NMOS tube is respectively connected with the source electrode of the first auxiliary NMOS tube and the upper polar plate of the first auxiliary capacitor; the upper polar plate of the first capacitor is connected with a first clock signal; the lower pole plate of the first auxiliary capacitor is connected with a second auxiliary clock signal; the source electrode of the fifth NMOS tube is connected with the substrate and then connected with a second clock signal; the drain electrode of the fifth NMOS tube is connected with the drain electrode of the third PMOS tube and then is connected with the grid electrode of the first PMOS tube; the grid electrode of the fifth NMOS tube is connected with the grid electrode of the third PMOS tube and then is connected with the first clock signal; the source electrode of the second NMOS tube is respectively connected with the grid electrode of the second auxiliary NMOS tube, the source electrode of the second PMOS tube, the source electrode of the third PMOS tube and the upper polar plate of the second capacitor; the grid electrode of the second NMOS tube is respectively connected with the source electrode of the second auxiliary NMOS tube and the upper polar plate of the second auxiliary capacitor; the lower pole plate of the second auxiliary capacitor is connected with the first auxiliary clock signal; the lower pole plate of the second capacitor is connected with a second clock signal; the source electrode of the sixth NMOS tube is connected with the substrate and then connected with the first clock signal; the drain electrode of the sixth NMOS tube is connected with the drain electrode of the fourth PMOS tube and then is connected with the grid electrode of the second PMOS tube; the grid electrode of the sixth NMOS tube is connected with the grid electrode of the fourth PMOS tube and then is connected with a second clock signal; the substrate and the drain electrode of the first PMOS tube, the substrate of the third PMOS tube, the substrate of the fourth PMOS tube, and the drain electrode and the substrate of the second PMOS tube are connected and then connected with the output end of the charge pump circuit.

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