CN104993816A - Voltage doubling circuit - Google Patents
Voltage doubling circuit Download PDFInfo
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- CN104993816A CN104993816A CN201510465530.8A CN201510465530A CN104993816A CN 104993816 A CN104993816 A CN 104993816A CN 201510465530 A CN201510465530 A CN 201510465530A CN 104993816 A CN104993816 A CN 104993816A
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Abstract
The invention provides a voltage doubling circuit. The voltage doubling circuit comprises a transistor group formed by means of cascading of a voltage-regulating circuit, a first thin-gate PMOS (P-Channel Metal Oxide Semiconductor) transistor and a thin-gate NMOS (N-Channel Metal Oxide Semiconductor) transistor, and a switching control circuit, wherein the switching control circuit is coupled to the gate of the first thin-gate PMOS transistor, and is suitable for conducting the first thin-gate PMOS transistor on the falling edge of power supply voltage and keeping the gate voltage of the first thin-gate PMOS transistor at a high level after conduction of the first thin-gate PMOS transistor. Through adoption of the voltage doubling circuit, the thin-gate transistors are taken as boosting elements instead of a conventional thick-gate transistor, so that the space occupied by the transistors is reduced. Moreover, the voltage doubling circuit is simple in structure, easy to implement, and beneficial to the integration of the circuit.
Description
Technical field
The present invention relates to technical field of semiconductors, particularly relate to a kind of voltage-multiplying circuit.
Background technology
In integrated circuit fields, often need to boost to input voltage, such as, after boosting, export the voltage doubling input voltage, develop various voltage-multiplying circuit in prior art for this reason.
Please refer to Fig. 1, is a kind of in prior art structural representation of voltage-multiplying circuit.In the voltage-multiplying circuit of described prior art, adopt thick grid PMOS P10 and P20 and thick grid NMOS tube N.Wherein, the thickness of grid oxide layer scope of thick grid metal-oxide-semiconductor is: 6.0nm ~ 20.0nm.
The voltage-multiplying circuit of the prior art comes with some shortcomings part, as owing to adopting thick gate transistor, makes the volume of circuit comparatively large, for the integrated difficulty caused to a certain degree of later stage circuit.Therefore, when supply voltage is lower, can export the volume that multiplication of voltage can reduce again circuit is a urgent problem.
Summary of the invention
The technical problem that the present invention solves is the volume reducing voltage-multiplying circuit.
For solving the problems of the technologies described above, the embodiment of the present invention provides a kind of voltage-multiplying circuit, comprising:
Voltage-regulating circuit, couples the power input of described voltage-multiplying circuit, is suitable for exporting the adjustment voltage that the supply voltage inputted with described power input exists consistent difference;
First thin grid PMOS, its drain electrode couples the output of described voltage-regulating circuit, and source electrode is as the output of described voltage-multiplying circuit;
The transistor group that thin grid NMOS tube cascade is formed, the source electrode of the first thin grid PMOS described in a termination of described transistor group, other end ground connection; The conducting when described supply voltage is high level of described transistor group, ends when described supply voltage is low level;
ON-OFF control circuit, couples the grid of described first thin grid PMOS, is suitable for the first thin grid PMOS described in the trailing edge conducting of described supply voltage, and the grid voltage maintaining the first thin grid PMOS after the first thin grid PMOS described in conducting is high level.
Further, ON-OFF control circuit comprises pulse generator, and its one end couples the input of described voltage-multiplying circuit, and the other end couples the grid of described first thin grid PMOS; Described pulse generator is suitable for producing pulse at the trailing edge of described supply voltage.
Pulse generator comprises input and the swept resistance that input couples described voltage-multiplying circuit, exports the NOR-logic door of termination inverter.
Further, transistor group comprises the first thin grid NMOS tube and the second thin grid NMOS tube, and the source electrode of described first thin grid NMOS tube connects the source electrode of described first thin grid PMOS, the grounded drain of described second thin grid NMOS tube.
The grid of the second thin grid NMOS tube connects described supply voltage.
Further, voltage-regulating circuit comprises inverter, electric capacity and the second thin grid PMOS; Described inverter and capacitances in series are between the input and the drain electrode of described thin grid PMOS of described voltage-multiplying circuit; The source electrode of described second thin grid PMOS couples described electric capacity, drain electrode connects supply voltage, and described second thin grid PMOS conducting when the output voltage of described voltage-multiplying circuit is low level, ends when the output voltage of described voltage-multiplying circuit is high level.
The grid of the second thin grid PMOS connects the output of described voltage-multiplying circuit.
The thickness of grid oxide layer scope of described thin grid PMOS and described thin grid NMOS tube is: 1.5nm ~ 4.0nm.
Compared with prior art, the technical scheme of the embodiment of the present invention has following beneficial effect:
Thick oxygen gate transistor is replaced with thin gate transistor in technical solution of the present invention, the grid of described first thin grid PMOS is coupled by ON-OFF control circuit, the first thin grid PMOS described in the trailing edge conducting of described supply voltage, and the grid voltage maintaining the first thin grid PMOS after the first thin grid PMOS described in conducting is high level, thin grid nmos pass transistor group voltage is modulated by cascade structure, thus the multiplication of voltage of output supply voltage.Compared with prior art, reduce transistor and take volume, and then reduce the volume of voltage-multiplying circuit.
Accompanying drawing explanation
Fig. 1 is the structural representation of a kind of voltage-multiplying circuit in prior art;
Fig. 2 is the schematic diagram of a kind of voltage-multiplying circuit of the embodiment of the present invention;
Fig. 3 is the structural representation of a kind of voltage-multiplying circuit of the embodiment of the present invention;
Fig. 4 is the structural representation of the pulse generator of a kind of voltage-multiplying circuit of the embodiment of the present invention;
Fig. 5 is the time diagram of each signal of a kind of voltage-multiplying circuit of the embodiment of the present invention.
Embodiment
As described in the background art, voltage-multiplying circuit of the prior art adopts thick gate transistor, and circuit volume is taken greatly.
In order to realize the technique effect of the volume reducing voltage-multiplying circuit, the present invention, by improving circuit structure, adopts thin gate transistor to replace traditional thick gate transistor as boosting element, can reduce taking up room of transistor.
For enabling above-mentioned purpose of the present invention, feature and advantage more become apparent, and are described in detail specific embodiments of the invention below in conjunction with accompanying drawing.
Fig. 2 is the schematic diagram of a kind of voltage-multiplying circuit of the embodiment of the present invention.
Voltage-multiplying circuit comprises, the transistor group 21 that the thin grid PMOS P1 of voltage-regulating circuit 20, first, thin grid NMOS tube cascade are formed and ON-OFF control circuit 22.
Wherein, voltage-regulating circuit 20, couples the power input of voltage-multiplying circuit, is suitable for exporting the adjustment voltage that the supply voltage inputted with power input exists consistent difference.
First thin grid PMOS P1, its drain electrode couples the output of voltage-regulating circuit, and source electrode is as the output of voltage-multiplying circuit.
The transistor group 21 that thin grid NMOS tube cascade is formed, the source electrode of the thin grid PMOS P1 of a termination first of transistor group, other end ground connection.The conducting when described supply voltage is high level of described transistor group 21, ends when described supply voltage is low level;
ON-OFF control circuit 22 one end couples the input of voltage-multiplying circuit, and the other end couples the grid of the first thin grid PMOS P1.ON-OFF control circuit 22 is suitable for the first thin grid PMOS P1 described in the trailing edge conducting of described supply voltage, and the grid voltage maintaining the first thin grid PMOS after the first thin grid PMOS described in conducting is high level.
In described voltage-multiplying circuit, when the supply voltage inputted is high level, the conducting of described transistor group 21; Described first thin grid PMOS P1 ends, and the output voltage of described voltage-multiplying circuit is low level.
When the supply voltage inputted is converted to low level from high level, described transistor group 21 is ended; At the trailing edge of supply voltage, the grid voltage that ON-OFF control circuit 22 controls described first thin grid PMOS is low level, and with the first thin grid PMOS P1 described in conducting, the output voltage of described voltage-multiplying circuit is converted to high level thereupon.Owing to needing the normal work maintaining described first thin grid PMOS P1, after grid PMOS P1 thin described in conducting, the grid voltage that described ON-OFF control circuit 22 maintains the first thin grid PMOS is thereupon high level.
Because transistor group 21 comprises thin grid NMOS tube, therefore adopt cascade structure, to ensure that each thin grid NMOS tube is all operated in its withstand voltage scope.
Wherein, the thickness of grid oxide layer scope of described thin grid PMOS and described thin grid NMOS tube is: 1.5nm ~ 4.0nm.
Fig. 3 is the structural representation of a kind of voltage-multiplying circuit of the embodiment of the present invention.
The transistor group 21 that voltage-multiplying circuit comprises the thin grid PMOS P1 of voltage-regulating circuit 20, first, thin grid NMOS tube cascade is formed and ON-OFF control circuit 22.
Particularly, voltage-regulating circuit 20 comprises inverter INV1, electric capacity C and the second thin grid PMOS P2; Inverter INV and electric capacity C is series between the input of voltage-multiplying circuit and the drain electrode of described second thin grid PMOS P2; Source electrode coupling capacitance C, the drain electrode of the second thin grid PMOS P2 meet supply voltage VDD.
The grid of the second thin grid PMOS P2 connects the output of voltage-multiplying circuit.
Described ON-OFF control circuit 22 comprises pulse generator PB.
Described pulse generator PB can adopt existing pulse-generating circuit to realize.
In the lump with reference to Fig. 4, as NOR-logic door NOR input couples input and the swept resistance R of voltage-multiplying circuit, export termination inverter INV2 and form, also have other alternative embodiments in addition, the embodiment of the present invention does not limit this.
Transistor group 21 comprises the first thin grid NMOS tube N1 and the second thin grid NMOS tube N2, and the source electrode of the first thin grid NMOS tube N1 connects the source electrode of the first thin grid PMOS P1, the grounded drain of the second thin grid NMOS tube N2.
The grid of the second thin grid NMOS tube N2 connects supply voltage.
For convenience of description, the signal post that ON-OFF control circuit exports is designated as PB, and the signal post of voltage-multiplying circuit input is designated as IN, and the signal post of output is designated as OUT.
As Fig. 5, it is the time diagram of each signal of a kind of voltage-multiplying circuit of the embodiment of the present invention.Composition graphs 3 and Fig. 5 are described in further details in the lump below.
Input signal IN is the low level of rule be 0V and high level is the square-wave signal of VDD, wherein,
When input signal IN is high level, the pulse generator PB of ON-OFF control circuit 22 exports high level, first thin grid PMOS P1 ends, grid couples the second thin grid NMOS tube N2 conducting of input signal, and the first thin grid PMOS P1 drain electrode end exports the low level signal OUT identical with the second thin grid NMOS tube N2 source voltage.
Meanwhile, the second thin grid PMOS P2 conducting, the source voltage making the first thin grid PMOS P1 is VDD, and the two poles of the earth voltage difference of appointing of the first thin grid PMOS P1 is no more than VDD.
Become low level trailing edge at input signal IN from high level, the inverter INV in voltage-regulating circuit 20 and electric capacity C, the drain voltage making the second thin grid PMOS P2 is 2VDD.
Meanwhile, the pulse generator PB output low level pulse signal of ON-OFF control circuit 22, the first thin grid PMOS P1 conducting, drain electrode end exports the high level signal OUT identical with the drain voltage of the second thin grid PMOS P2.
The grid voltage maintaining the first thin grid PMOS P1 after the thin grid PMOS P1 of pulse generator PB output low level pulse signal conducting first is high level VDD, makes the two poles of the earth voltage difference of appointing of the first thin grid PMOS P1 be no more than VDD.
Simultaneously due to the cascade of the thin grid NMOS tube N1 of transistor group 21 first and the second thin grid NMOS tube N2, make each transistor voltage be VDD, be no more than its withstand voltage scope.
Alternatively, the magnitude of voltage at the A point place of pulse signal PB is 0-0.3V.The magnitude of voltage at described A point place is the receiver voltage value of the first thin grid PMOS P1 grid.
Technical scheme provided by the invention controls the grid end of thin grid PMOS by the mode of the thin grid NMOS tube and ON-OFF control circuit generation pulse that arrange cascaded structure, achieving thin gate transistor replaces traditional thick gate transistor as boosting element, substantially reduces taking up room of transistor.In addition, the structure that the invention provides circuit is simple, is easy to realize, is also conducive to the integrated of circuit.
Although the present invention discloses as above, the present invention is not defined in this.Any those skilled in the art, without departing from the spirit and scope of the present invention, all can make various changes or modifications, and therefore protection scope of the present invention should be as the criterion with claim limited range.
Claims (8)
1. a voltage-multiplying circuit, is characterized in that, comprising:
Voltage-regulating circuit, couples the power input of described voltage-multiplying circuit, is suitable for exporting the adjustment voltage that the supply voltage inputted with described power input exists consistent difference;
First thin grid PMOS, its drain electrode couples the output of described voltage-regulating circuit, and source electrode is as the output of described voltage-multiplying circuit;
The transistor group that thin grid NMOS tube cascade is formed, the source electrode of the first thin grid PMOS described in a termination of described transistor group, other end ground connection; The conducting when described supply voltage is high level of described transistor group, ends when described supply voltage is low level;
ON-OFF control circuit, couples the grid of described first thin grid PMOS, is suitable for the first thin grid PMOS described in the trailing edge conducting of described supply voltage, and the grid voltage maintaining the first thin grid PMOS after the first thin grid PMOS described in conducting is high level.
2. voltage-multiplying circuit according to claim 1, is characterized in that, described ON-OFF control circuit comprises pulse generator, and its one end couples the input of described voltage-multiplying circuit, and the other end couples the grid of described first thin grid PMOS; Described pulse generator is suitable for producing pulse at the trailing edge of described supply voltage.
3. voltage-multiplying circuit according to claim 2, is characterized in that, described pulse generator comprises input and the swept resistance that input couples described voltage-multiplying circuit, exports the NOR-logic door of termination inverter.
4. voltage-multiplying circuit according to claim 1, it is characterized in that, described transistor group comprises the first thin grid NMOS tube and the second thin grid NMOS tube, and the source electrode of described first thin grid NMOS tube connects the source electrode of described first thin grid PMOS, the grounded drain of described second thin grid NMOS tube.
5. voltage-multiplying circuit according to claim 4, is characterized in that, the grid of described second thin grid NMOS tube connects described supply voltage.
6. voltage-multiplying circuit according to claim 1, is characterized in that, described voltage-regulating circuit comprises inverter, electric capacity and the second thin grid PMOS; Described inverter and capacitances in series are between the input and the drain electrode of described second thin grid PMOS of described voltage-multiplying circuit; The source electrode of described second thin grid PMOS couples described electric capacity, drain electrode connects supply voltage, and described second thin grid PMOS conducting when the output voltage of described voltage-multiplying circuit is low level, ends when the output voltage of described voltage-multiplying circuit is high level.
7. voltage-multiplying circuit according to claim 6, is characterized in that, the grid of described second thin grid PMOS connects the output of described voltage-multiplying circuit.
8., according to the arbitrary described voltage-multiplying circuit of claim 1-7, it is characterized in that, the thickness of grid oxide layer scope of described thin grid PMOS and described thin grid NMOS tube is: 1.5nm ~ 4.0nm.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201510465530.8A CN104993816B (en) | 2015-07-31 | 2015-07-31 | Voltage-multiplying circuit |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201510465530.8A CN104993816B (en) | 2015-07-31 | 2015-07-31 | Voltage-multiplying circuit |
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| CN104993816A true CN104993816A (en) | 2015-10-21 |
| CN104993816B CN104993816B (en) | 2018-04-27 |
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| CN201510465530.8A Active CN104993816B (en) | 2015-07-31 | 2015-07-31 | Voltage-multiplying circuit |
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106787691A (en) * | 2017-01-06 | 2017-05-31 | 上海华虹宏力半导体制造有限公司 | Charge pump circuit, charge pump system and memory |
| CN107612317A (en) * | 2017-09-26 | 2018-01-19 | 上海华虹宏力半导体制造有限公司 | A kind of charge pump circuit |
| CN107634647A (en) * | 2017-09-26 | 2018-01-26 | 上海华虹宏力半导体制造有限公司 | A kind of voltage multiplying circuit |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN1221257A (en) * | 1997-12-24 | 1999-06-30 | 日本电气株式会社 | Static latch circuit and static logic circuit |
| US6731156B1 (en) * | 2003-02-07 | 2004-05-04 | United Memories, Inc. | High voltage transistor protection technique and switching circuit for integrated circuit devices utilizing multiple power supply voltages |
| CN1992489A (en) * | 2005-12-27 | 2007-07-04 | 株式会社半导体能源研究所 | Charge pump circuit and semiconductor device having the same |
| CN102843123A (en) * | 2012-08-31 | 2012-12-26 | 电子科技大学 | High-voltage driving circuit |
-
2015
- 2015-07-31 CN CN201510465530.8A patent/CN104993816B/en active Active
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1221257A (en) * | 1997-12-24 | 1999-06-30 | 日本电气株式会社 | Static latch circuit and static logic circuit |
| US6731156B1 (en) * | 2003-02-07 | 2004-05-04 | United Memories, Inc. | High voltage transistor protection technique and switching circuit for integrated circuit devices utilizing multiple power supply voltages |
| CN1992489A (en) * | 2005-12-27 | 2007-07-04 | 株式会社半导体能源研究所 | Charge pump circuit and semiconductor device having the same |
| CN102843123A (en) * | 2012-08-31 | 2012-12-26 | 电子科技大学 | High-voltage driving circuit |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106787691A (en) * | 2017-01-06 | 2017-05-31 | 上海华虹宏力半导体制造有限公司 | Charge pump circuit, charge pump system and memory |
| CN106787691B (en) * | 2017-01-06 | 2019-08-27 | 上海华虹宏力半导体制造有限公司 | Charge pump circuit, charge pump system and memory |
| CN107612317A (en) * | 2017-09-26 | 2018-01-19 | 上海华虹宏力半导体制造有限公司 | A kind of charge pump circuit |
| CN107634647A (en) * | 2017-09-26 | 2018-01-26 | 上海华虹宏力半导体制造有限公司 | A kind of voltage multiplying circuit |
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| CN104993816B (en) | 2018-04-27 |
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