CN206341200U - Grid driving circuit - Google Patents
Grid driving circuit Download PDFInfo
- Publication number
- CN206341200U CN206341200U CN201621302107.2U CN201621302107U CN206341200U CN 206341200 U CN206341200 U CN 206341200U CN 201621302107 U CN201621302107 U CN 201621302107U CN 206341200 U CN206341200 U CN 206341200U
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- control module
- pmos
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- peak control
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- 238000000034 method Methods 0.000 abstract description 5
- 238000009931 pascalization Methods 0.000 abstract description 4
- 230000003071 parasitic effect Effects 0.000 abstract description 2
- 230000005611 electricity Effects 0.000 description 8
- 239000004065 semiconductor Substances 0.000 description 8
- 230000015556 catabolic process Effects 0.000 description 5
- 238000010586 diagram Methods 0.000 description 3
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- 230000005540 biological transmission Effects 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 230000003750 conditioning effect Effects 0.000 description 1
- 238000013499 data model Methods 0.000 description 1
- 230000007812 deficiency Effects 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
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Classifications
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
- H03K17/51—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used
- H03K17/56—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices
- H03K17/687—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices the devices being field-effect transistors
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02B—CLIMATE CHANGE MITIGATION TECHNOLOGIES RELATED TO BUILDINGS, e.g. HOUSING, HOUSE APPLIANCES OR RELATED END-USER APPLICATIONS
- Y02B70/00—Technologies for an efficient end-user side electric power management and consumption
- Y02B70/10—Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes
Abstract
The utility model provides a gate drive circuit, include: an inverter; a first PMOS tube; a second PMOS tube; a third PMOS tube; a first current input end of the voltage peak value control module is connected with a drain electrode of the first PMOS tube, a second current input end of the voltage peak value control module is connected with a drain electrode of the second PMOS tube, a third current input end of the voltage peak value control module is connected with a drain electrode of the third PMOS tube, a first voltage input end of the voltage peak value control module is connected with a first regulation voltage end, and a second voltage input end of the voltage peak value control module is connected with a second regulation voltage end; a first current mirror; a second current mirror; and a ninth NMOS transistor. The utility model discloses can utilize the low pressure device to accomplish the circuit design of relative high pressure processing procedure, reduce the area, save the cost, simultaneously, less device, parasitic capacitance hinders also less, easy drive, and speed is very fast.
Description
Technical field
The utility model belongs to electronic technology field, more particularly to a kind of gate driving circuit.
Background technology
Traditional gate driving circuit typically use frequency converter framework as shown in Figure 1, by top PMOS MP1 ' and
NMOS tube MN1 ' the compositions of lower section.In the circuit, the necessary pressure-resistant VPP-VNN of MP1 ' and MN1 ' voltage difference scope.Also
It is to say, if the voltage difference between power supply VPP and ground VNN is 10V, the device MP1 ' selected and MN1 ' must also select pressure-resistant
10V device.It is well known, however, that pressure-resistant higher device, area is bigger, cost is higher, fierce all the more in price competition, system
Selecting under fewer and feweri environment for journey, the circuit design of relatively high pressure processing procedure is completed using low-voltage device, is integrated at present
One trend of circuit design.
Utility model content
For above-mentioned the deficiencies in the prior art, the utility model provides a kind of improved gate driving circuit, and it being capable of profit
The raster data model of relatively high pressure processing procedure is completed with low-voltage device.
To achieve these goals, the utility model is adopted the following technical scheme that：
A kind of gate driving circuit, including：
One phase inverter, its input connects a signal input part；
One first PMOS, its grid connects the input of the phase inverter, and source electrode and base stage connect a positive voltage terminal；
One second PMOS, its grid connects the output end of the phase inverter, and source electrode and base stage connect the positive voltage terminal；
One the 3rd PMOS, its grid connects the input of the phase inverter, and source electrode and base stage connect the positive voltage terminal；
One voltage peak control module, its first current input terminal connects the drain electrode of first PMOS, the second electric current
Input connects the drain electrode of second PMOS, and the 3rd current input terminal connects the drain electrode of the 3rd PMOS, the first electricity
Input connection one first is pressed to regulate and control voltage end, second voltage input connection one second regulates and controls voltage end；
One first current mirror, its current input terminal connects the first output end of the voltage peak control module, and electric current is defeated
Go out the 3rd output end of the end connection voltage peak control module, voltage input end connects a negative voltage side；
One second current mirror, its current input terminal connects the second output end of the voltage peak control module, and electric current is defeated
Go out the 3rd output end of the end connection voltage peak control module, voltage input end connects the negative voltage side；And
One the 9th NMOS tube, its grid connects the 3rd output end of the voltage peak control module, and source electrode and backgate connect
Connect the negative voltage side, the 4th output end and a signal output part of the drain electrode connection voltage peak control module.
Further, the circuit also includes：One electric capacity, it is connected to the input and the first PMOS of the phase inverter
Between the grid of pipe；And a resistance, it is connected between the grid of first PMOS and the positive voltage terminal.
Further, the voltage peak control module includes：
One low current generation module, its first output end connects the first electric current input of the voltage peak control module
End, the 3rd output end connects the second current input terminal of the voltage peak control module, and the 4th output end connects the voltage
3rd current input terminal of peak value control module；
One the 4th PMOS, its grid connects the first voltage input of the voltage peak control module, source electrode and base
Pole connects the first current input terminal of the voltage peak control module；
One the 5th PMOS, its grid connects the first voltage input of the voltage peak control module, source electrode and base
Pole connects the second output end of the low current generation module；
One the 6th PMOS, its grid connects the first voltage input of the voltage peak control module, source electrode and base
Pole connects the second current input terminal of the voltage peak control module；
One the 6th PMOS, its grid connects the first voltage input of the voltage peak control module, source electrode and base
Pole connects the 3rd current input terminal of the voltage peak control module；
One the 7th PMOS, its grid connects the first voltage input of the voltage peak control module, source electrode and base
Pole connects the 4th current input terminal of the voltage peak control module；
One first NMOS tube, its grid connects the second voltage input of the voltage peak control module, source electrode and base
Pole connects the first output end of the voltage peak control module, the drain electrode of drain electrode connection the 4th PMOS；
One second NMOS tube, its grid connects the second voltage input of the voltage peak control module, source electrode and base
Pole connects the second output end of the voltage peak control module, the drain electrode of drain electrode connection the 5th PMOS；
One the 3rd NMOS tube, its grid connects the second voltage input of the voltage peak control module, source electrode and base
Pole connects the 3rd output end of the voltage peak control module, the drain electrode of drain electrode connection the 6th PMOS；And
One the 4th NMOS tube, its grid connects the second voltage input of the voltage peak control module, source electrode and base
Pole connects the 4th output end of the voltage peak control module, the drain electrode of drain electrode connection the 7th PMOS.
Further, the low current generation module includes：
The tenth PMOS, its source electrode and base stage connect the positive voltage terminal, drain electrode one current terminal of connection；
11st PMOS, its source electrode and base stage connect the positive voltage terminal, the drain electrode connection low current generation module
The first output end, grid connects the grid of the tenth PMOS；
12nd PMOS, its source electrode and base stage connect the positive voltage terminal, the drain electrode connection low current generation module
The second output end, grid connects the grid of the tenth PMOS；
13rd PMOS, its source electrode and base stage connect the positive voltage terminal, the drain electrode connection low current generation module
The 3rd output end, grid connects the grid of the tenth PMOS；And
14th PMOS, its source electrode and base stage connect the positive voltage terminal, the drain electrode connection low current generation module
The 4th output end, grid connects the grid of the tenth PMOS.
Further, first current mirror includes：
One the 5th NMOS tube, its drain and gate connects the current input terminal of first current mirror, and source electrode and base stage connect
Connect the voltage input end of first current mirror；And
One the 6th NMOS tube, the current output terminal of its connection first current mirror that drains, grid connection first electricity
The current input terminal of mirror is flowed, source electrode and base stage connect the voltage input end of first current mirror.
Further, second current mirror includes：
One the 7th NMOS tube, its drain and gate connects the current input terminal of second current mirror, and source electrode and base stage connect
Connect the voltage input end of second current mirror；And
One the 8th NMOS tube, the current output terminal of its connection second current mirror that drains, grid connection second electricity
The current input terminal of mirror is flowed, source electrode and base stage connect the voltage input end of second current mirror.
The utility model has the advantages that：All MOS in circuit can be controlled by voltage peak control module
The maximum of the drain-source voltage of pipe is not over breakdown voltage, therefore, even if the pressure difference between positive voltage terminal and negative voltage side
Larger, metal-oxide-semiconductor can be realized using resistance to low-voltage device in circuit of the present utility model, that is to say, that the utility model can
The circuit design of relatively high pressure processing procedure is completed using low-voltage device, area is reduced, cost is saved, meanwhile, less device
Part, parasitic capacitance resistance is also smaller, easily driving, speed.
Brief description of the drawings
Fig. 1 is the circuit theory diagrams of the gate driving circuit of prior art；
Fig. 2 is the circuit theory diagrams of gate driving circuit of the present utility model；
Fig. 3 is the circuit theory diagrams of the utility model small current generation module.
Embodiment
It is careful to coordinate accompanying drawing to give citing further again to make to give farther insight into technological means of the present utility model and feature
Illustrate in rear：
Gate driving circuit of the present utility model is as shown in figure 1, including phase inverter IVN, electric capacity C1, resistance R1, first
PMOS MP1, the second PMOS MP2, the 3rd PMOS MP3, voltage peak control module 1, the first current mirror 2, the second electric current
The NMOS tube MN9 of mirror 3 and the 9th.Wherein, phase inverter INV input connects a signal input part, receives into an input signal IN；
Electric capacity C1 is connected between phase inverter INV input and the first PMOS PM1 grid；Resistance R1 is connected to the first PMOS
Between MP1 grid and positive voltage terminal VPP；First PMOS MP1 source electrode and base stage connection positive voltage terminal VPP；2nd PMOS
Pipe MP2 grid connection phase inverter INV output end, source electrode and base stage connection positive voltage terminal VPP；3rd PMOS MP3 grid
Pole connection phase inverter INV input, source electrode and base stage connection positive voltage terminal VPP；First electric current of voltage peak control module 1
Input connects the first PMOS MP1 drain electrode, and the second current input terminal connects the second PMOS MP2 drain electrode, the 3rd electric current
Input connects the 3rd PMOS MP3 drain electrode, and first voltage input connection one first regulates and controls voltage end, to receive a regulation and control
Voltage VA, second voltage input connection one second regulates and controls voltage end, to receive a regulation and control voltage VB；The electricity of first current mirror 2
Flow the first output end of input connection voltage peak control module 1, the of current output terminal connection voltage peak control module 1
Three output ends, voltage input end connects a negative voltage side VNN；The current input terminal connection voltage peak control of second current mirror 2
Second output end of module 1, the 3rd output end of current output terminal connection voltage peak control module 1, voltage input end connection
Negative voltage side VNN；3rd output end of the 9th NMOS tube MN9 grid connection voltage peak control module 1, source electrode and backgate connect
Meet negative voltage side VNN, the 4th output end and a signal output part of drain electrode connection voltage peak control module 1, to export one
Signal OUT.
In the present embodiment, R1, C1 and MP1 constitute immediate current generation module, and its function is to accelerate the transmission of electric signal,
Save the electric current consumed during work switching.Specifically, when IN signals from high to low when, electric capacity C1 negative terminal can be drawn by moment
Low, then MP1 is shown in a fully open operation, you can supply electric current, MP1 gate terminal because being connected to VPP by drawing high resistance R,
MP1 gate terminal can finally be pulled to VPP, so that the time that MP1 closings, wherein MP1 gate terminal are pulled to VPP can lead to
The value for crossing R, C is adjusted.In other words, when IN signals from high to low when, MP1 can be broken instantaneously, but by it is of short duration when
Between again can close, so MP1 can only produce the electric current of moment, the substitute is afterwards by low current generation module below
Power supply.
The function of above-mentioned voltage peak control module is the voltage by adjusting VA, VB, makes the MOS in whole drive circuit
Pipe is pressure-resistant to be no more than collapse of voltage point, and in the embodiment shown in Figure 2, it includes low current generation module, the 4th PMOS
MP4, the 5th PMOS MP5, the 6th PMOS MP6, the 7th PMOS MP7, the first NMOS tube MN1, the second NMOS tube MN2,
Three NMOS tube MN3 and the 4th NMOS tube MN4.Wherein, the first output end connection voltage peak control of low current generation module
First current input terminal of module 1, the second current input terminal of the 3rd output end connection voltage peak control module 1, the 4th is defeated
Go out the 3rd current input terminal of end connection voltage peak control module 1.4th PMOS MP4 grid connection voltage peak control
First current input terminal of the first voltage input of module 1, source electrode and base stage connection voltage peak control module 1；5th
The first voltage input of PMOS MP5 grid connection voltage peak control module 1, source electrode and base stage connection low current are produced
Second output end of module；The first voltage input of 6th PMOS MP6 grid connection voltage peak control module 1, source
Pole and the second current input terminal of base stage connection voltage peak control module 1；7th PMOS MP7 grid connection voltage peak
4th current input terminal of the first voltage input of control module 1, source electrode and base stage connection voltage peak control module 1；The
The second voltage input of one NMOS tube MN1 grid connection voltage peak control module 1, source electrode and base stage connection voltage peak
First output end of control module 1, the 4th PMOS MP4 of drain electrode connection drain electrode；Second NMOS tube MN2 grid connection voltage
Second output end of the second voltage input of peak value control module 1, source electrode and base stage connection voltage peak control module 1, leakage
Pole connects the 5th PMOS MP5 drain electrode；The second voltage of 3rd NMOS tube MN3 grid connection voltage peak control module 1
3rd output end of input, source electrode and base stage connection voltage peak control module 1, the 6th PMOS MP6 of drain electrode connection leakage
Pole；The second voltage input of 4th NMOS tube MP4 grid connection voltage peak control module 1, source electrode and base stage connection electricity
4th output end of voltage crest value control module 1, the 7th PMOS MP7 of drain electrode connection drain electrode.
Wherein, the operation principle of voltage peak control module 1 is as follows：MP4, MP5, MP6 and MP7 can be made respectively by VA
Source/base voltage it is minimum be fixed on VA+VTH (VTH refer to correspondence metal-oxide-semiconductor cut-in voltage), so as to avoid MP1, MP2, MP3
Vds reaches too big pressure difference so that more than its breakdown voltage.MN1, MN2, MN3 and MN4 source/base can be made respectively by VB
Pole tension highest is fixed on VB-VTH (VTH refers to the cut-in voltage of correspondence metal-oxide-semiconductor), so as to avoid MN5, MN6, MN7, MN8, MN9
Vds reach too big pressure difference so that more than its breakdown voltage, should by control moreover, OUT maximum potentials are VB-VTH
The maximum of voltage, can be easy to the specification of metal-oxide-semiconductor for selecting OUT to be driven.Wherein, VA, VB value are according to four following bars
Part is set, to ensure all metal-oxide-semiconductors not over breakdown voltage：
(1) MP1 Vds is VPP- (VA+VTH) to the maximum；
(2) MP4 Vds is VPP- (VB-VTH to the maximumMN1+VdsMN1) or (VA+VTH)-VdsMN1-VTHMN5-VNN；
(3) MN1 Vds is VPP-Vds to the maximumMP4-(VB-VTHMN1) or VA+VTHMP4-VdsMP4-VTHMN5-VNN；
(4) MN5 Vds is VB-VTH to the maximumMN1-VNN。
Above-mentioned low current generation module as shown in figure 3, including：The PMOS MP10 of ten, the 11,12,13 and 14,
MP11、MP12、MP13、MP14.Wherein, the tenth PMOS MP10 source electrode and base stage connection positive voltage terminal VPP, drain electrode connection one
Current terminal, to receive a current input signal Iin；11st PMOS MP11 source electrode and base stage connection positive voltage terminal VPP, leakage
Pole connects the first output end of low current generation module, and grid connects the tenth PMOS MP10 grid；12nd PMOS
MP12 source electrode and base stage connection positive voltage terminal VPP, the second output end of drain electrode connection low current generation module, grid connection the
Ten PMOS MP10 grid；13rd PMOS MP13 source electrode and base stage connection positive voltage terminal VPP, drain electrode connection low current
3rd output end of generation module, grid connects the tenth PMOS MP10 grid；14th PMOS MP14 source electrode and base
Pole connects positive voltage terminal VPP, and the 4th output end of drain electrode connection low current generation module, grid connects the tenth PMOS MP10's
Grid.Low current generation module in the present embodiment is substantially a current mirroring circuit for providing fixed low current, and its function is
Enable whole drive circuit normal work with minimum electric current.When drive circuit always operationally, the end of each of which metal-oxide-semiconductor
Point voltage is all controlled in expected fixed range, and whether can so grasp in whole drive circuit has metal-oxide-semiconductor to exceed collapse electricity
Pressure is used, and whole drive circuit is maintained operation under low current, and when waiting the conversion of IN signals, drive circuit can be anti-immediately
Should, without first closing, then restart.
Referring again to Fig. 2, foregoing first current mirror 2 is made up of the 5th and the 6th NMOS tube MN5, MN6, wherein, the 5th
NMOS tube MN5 drain and gate connects the current input terminal of the first current mirror 2, and source electrode and base stage connect the first current mirror 2
Voltage input end；The current output terminal of 6th NMOS tube MN6 drain electrode the first current mirror 2 of connection, grid connects the first current mirror 2
Current input terminal, source electrode and base stage connect the voltage input end of the first current mirror 2.Second current mirror 3 is by the 7th and the 8th
NMOS tube MN7, MN8 is constituted, wherein, the 7th NMOS tube MN7 drain and gate connects the current input terminal of the second current mirror 3,
Source electrode and base stage connect the voltage input end of the second current mirror 3；The electricity of 8th NMOS tube MN8 drain electrode the second current mirror 3 of connection
Output end is flowed, grid connects the current input terminal of the second current mirror 3, and source electrode and base stage connect the control source of the second current mirror
End.
Operation principle of the present utility model is as follows：When IN signals are high, MP1 is closed, and MP3 is closed, and MP2 is opened and its electricity
Electric current of the stream much larger than MN8, now MN9 grid voltage is height, then OUT signal is low；When IN signals are low, MP2 is closed,
MN8 can drag down MN9 grid voltage, cause MN9 to close, then now because MP3 is opened, so OUT signal is height, so that
Realize the driving to subsequent conditioning circuit.Wherein, the utility model can control all MOS in circuit by voltage peak control module
The maximum of the drain-source voltage of pipe is not over breakdown voltage, therefore, even if between positive voltage terminal VPP and negative voltage side VNN
Pressure difference is larger, and all metal-oxide-semiconductors can be realized using resistance to low-voltage device in this circuit.
Above-described, preferred embodiment only of the present utility model is not limited to scope of the present utility model, this
Above-described embodiment of utility model can also make a variety of changes.I.e. every claims according to the present utility model application and
Simple, equivalence changes and modification that description is made, fall within the claims of the utility model patent.This
Utility model not detailed description is routine techniques content.
Claims (6)
1. a kind of gate driving circuit, it is characterised in that including：
One phase inverter, its input connects a signal input part；
One first PMOS, its grid connects the input of the phase inverter, and source electrode and base stage connect a positive voltage terminal；
One second PMOS, its grid connects the output end of the phase inverter, and source electrode and base stage connect the positive voltage terminal；
One the 3rd PMOS, its grid connects the input of the phase inverter, and source electrode and base stage connect the positive voltage terminal；
One voltage peak control module, its first current input terminal connects the drain electrode of first PMOS, the input of the second electric current
The drain electrode of end connection second PMOS, the 3rd current input terminal connects the drain electrode of the 3rd PMOS, and first voltage is defeated
Enter end connection one first and regulate and control voltage end, second voltage input connection one second regulates and controls voltage end；
One first current mirror, its current input terminal connects the first output end of the voltage peak control module, current output terminal
The 3rd output end of the voltage peak control module is connected, voltage input end connects a negative voltage side；
One second current mirror, its current input terminal connects the second output end of the voltage peak control module, current output terminal
The 3rd output end of the voltage peak control module is connected, voltage input end connects the negative voltage side；And
One the 9th NMOS tube, its grid connects the 3rd output end of the voltage peak control module, source electrode and back-gate connection institute
State negative voltage side, the 4th output end and a signal output part of the drain electrode connection voltage peak control module.
2. gate driving circuit according to claim 1, it is characterised in that the circuit also includes：
One electric capacity, it is connected between the grid of the input of the phase inverter and first PMOS；And
One resistance, it is connected between the grid of first PMOS and the positive voltage terminal.
3. gate driving circuit according to claim 1, it is characterised in that the voltage peak control module includes：
One low current generation module, its first output end connects the first current input terminal of the voltage peak control module, the
Three output ends connect the second current input terminal of the voltage peak control module, and the 4th output end connects the voltage peak control
3rd current input terminal of molding block；
One the 4th PMOS, its grid connects the first voltage input of the voltage peak control module, and source electrode and base stage connect
Connect the first current input terminal of the voltage peak control module；
One the 5th PMOS, its grid connects the first voltage input of the voltage peak control module, and source electrode and base stage connect
Connect the second output end of the low current generation module；
One the 6th PMOS, its grid connects the first voltage input of the voltage peak control module, and source electrode and base stage connect
Connect the second current input terminal of the voltage peak control module；
One the 6th PMOS, its grid connects the first voltage input of the voltage peak control module, and source electrode and base stage connect
Connect the 3rd current input terminal of the voltage peak control module；
One the 7th PMOS, its grid connects the first voltage input of the voltage peak control module, and source electrode and base stage connect
Connect the 4th current input terminal of the voltage peak control module；
One first NMOS tube, its grid connects the second voltage input of the voltage peak control module, and source electrode and base stage connect
Connect the first output end of the voltage peak control module, the drain electrode of drain electrode connection the 4th PMOS；
One second NMOS tube, its grid connects the second voltage input of the voltage peak control module, and source electrode and base stage connect
Connect the second output end of the voltage peak control module, the drain electrode of drain electrode connection the 5th PMOS；
One the 3rd NMOS tube, its grid connects the second voltage input of the voltage peak control module, and source electrode and base stage connect
Connect the 3rd output end of the voltage peak control module, the drain electrode of drain electrode connection the 6th PMOS；And
One the 4th NMOS tube, its grid connects the second voltage input of the voltage peak control module, and source electrode and base stage connect
Connect the 4th output end of the voltage peak control module, the drain electrode of drain electrode connection the 7th PMOS.
4. gate driving circuit according to claim 3, it is characterised in that the low current generation module includes：
The tenth PMOS, its source electrode and base stage connect the positive voltage terminal, drain electrode one current terminal of connection；
11st PMOS, its source electrode and base stage connect the positive voltage terminal, and the of the drain electrode connection low current generation module
One output end, grid connects the grid of the tenth PMOS；
12nd PMOS, its source electrode and base stage connect the positive voltage terminal, and the of the drain electrode connection low current generation module
Two output ends, grid connects the grid of the tenth PMOS；
13rd PMOS, its source electrode and base stage connect the positive voltage terminal, and the of the drain electrode connection low current generation module
Three output ends, grid connects the grid of the tenth PMOS；And
14th PMOS, its source electrode and base stage connect the positive voltage terminal, and the of the drain electrode connection low current generation module
Four output ends, grid connects the grid of the tenth PMOS.
5. gate driving circuit according to claim 1, it is characterised in that first current mirror includes：
One the 5th NMOS tube, its drain and gate connects the current input terminal of first current mirror, source electrode and base stage connection institute
State the voltage input end of the first current mirror；And
One the 6th NMOS tube, the current output terminal of its connection first current mirror that drains, grid connects first current mirror
Current input terminal, source electrode and base stage connect the voltage input end of first current mirror.
6. gate driving circuit according to claim 1, it is characterised in that second current mirror includes：
One the 7th NMOS tube, its drain and gate connects the current input terminal of second current mirror, source electrode and base stage connection institute
State the voltage input end of the second current mirror；And
One the 8th NMOS tube, the current output terminal of its connection second current mirror that drains, grid connects second current mirror
Current input terminal, source electrode and base stage connect the voltage input end of second current mirror.
Applications Claiming Priority (4)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| TW105134035A TW201817169A (en) | 2016-10-21 | 2016-10-21 | Gate driving circuit for driving high voltage or negative voltage speeds up transmission of circuit signals by way of utilizing instantaneous current |
| TW105216101 | 2016-10-21 | ||
| TW105134035 | 2016-10-21 | ||
| TW105216101U TWM534936U (en) | 2016-10-21 | 2016-10-21 | Gate driving circuit for driving high voltage or negative voltage |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN206341200U true CN206341200U (en) | 2017-07-18 |
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ID=58353644
Family Applications (2)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201611080793.8A Active CN106533410B (en) | 2016-10-21 | 2016-11-30 | Gate drive circuit |
| CN201621302107.2U Withdrawn - After Issue CN206341200U (en) | 2016-10-21 | 2016-11-30 | Grid driving circuit |
Family Applications Before (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201611080793.8A Active CN106533410B (en) | 2016-10-21 | 2016-11-30 | Gate drive circuit |
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| CN (2) | CN106533410B (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106533410A (en) * | 2016-10-21 | 2017-03-22 | 上海灿瑞科技股份有限公司 | Grid driving circuit |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108682393B (en) * | 2018-05-22 | 2020-07-07 | 京东方科技集团股份有限公司 | Driving method and device of pixel circuit |
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| US6414534B1 (en) * | 2001-02-20 | 2002-07-02 | Taiwan Semiconductor Manufacturing Company | Level shifter for ultra-deep submicron CMOS designs |
| US7277077B2 (en) * | 2004-02-26 | 2007-10-02 | Himax Technologies, Inc. | Gate driving apparatus |
| CN102064678B (en) * | 2010-11-29 | 2013-01-23 | Bcd半导体制造有限公司 | Gate drive circuit of switch power supply |
| CN102005909B (en) * | 2010-11-30 | 2013-10-30 | Bcd半导体制造有限公司 | Grid driving circuit for switching power supply |
| KR101420538B1 (en) * | 2012-12-27 | 2014-07-16 | 삼성전기주식회사 | Gate driver |
| CN103472880B (en) * | 2013-09-13 | 2014-12-10 | 电子科技大学 | Low dropout regulator |
| CN103529901B (en) * | 2013-10-28 | 2015-03-25 | 无锡中星微电子有限公司 | Circuit used for supplying power for bootstrap circuit |
| CN104795029B (en) * | 2014-01-16 | 2017-06-06 | 矽创电子股份有限公司 | Gate driver and circuit buffer thereof |
| JP6416650B2 (en) * | 2015-02-06 | 2018-10-31 | エイブリック株式会社 | Constant voltage circuit and oscillation device |
| CN105871180B (en) * | 2016-04-08 | 2018-07-17 | 厦门大学 | A kind of high current CMOS push-pull driver circuits and its control method |
| CN105915211A (en) * | 2016-05-17 | 2016-08-31 | 深圳芯能半导体技术有限公司 | Non-superposing circuit and high-voltage driving circuit |
| CN106533410B (en) * | 2016-10-21 | 2023-09-01 | 上海灿瑞微电子有限公司 | Gate drive circuit |
-
2016
- 2016-11-30 CN CN201611080793.8A patent/CN106533410B/en active Active
- 2016-11-30 CN CN201621302107.2U patent/CN206341200U/en not_active Withdrawn - After Issue
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106533410A (en) * | 2016-10-21 | 2017-03-22 | 上海灿瑞科技股份有限公司 | Grid driving circuit |
| CN106533410B (en) * | 2016-10-21 | 2023-09-01 | 上海灿瑞微电子有限公司 | Gate drive circuit |
Also Published As
| Publication number | Publication date |
|---|---|
| CN106533410B (en) | 2023-09-01 |
| CN106533410A (en) | 2017-03-22 |
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