TW201817169A - Gate driving circuit for driving high voltage or negative voltage speeds up transmission of circuit signals by way of utilizing instantaneous current - Google Patents

Abstract

A gate driving circuit for driving high voltage or negative voltage includes a signal input end; a switch circuit connected to the signal input end and comprising an instantaneous current generating unit, an inverter, a second PMOS transistor and a third PMOS transistor, wherein the instantaneous current generating module, an input end of the inverter and the third PMOS transistor are connected to the signal input end, and an output end of the inverter is connected to the second PMOS transistor, and the instantaneous current generating unit, the second PMOS transistor and the third PMOS transistor are connected to a first bias power source; a voltage peak control circuit connected to the switch circuit and comprising a first voltage input end, a second voltage input end, a current provision unit, a PMOS transistor unit and an NMOS transistor unit, wherein the first voltage input end is connected to a gate of the PMOS transistor unit, and the second voltage input end is connected to a gate of the NMOS transistor unit, and the current provision unit is configured to provide low current and connected to the PMOS transistor unit; a current controlled switch circuit connected to the voltage peak control circuit and comprising a first current mirror, a second current mirror and a ninth NMOS transistor; and a signal output end configured to output a digital output signal for driving the load.

Description

Gate driving circuit for driving high or negative voltage

The present invention relates to a gate driver circuit, and more particularly to a gate driver circuit suitable for high voltage or negative voltage.

At the time when environmental protection and green energy technology are being promoted around the world, low-power circuit design has become the main research and development direction of current semiconductor component applications to reduce the energy consumed by electronic products during operation. In general, to achieve the goal of low power consumption, the most direct and effective method is to reduce the operating voltage of the circuit, but once the circuit is operated at a low operating voltage, the current driving capability of the transistors in the circuit will be significantly reduced. As a result, the operation speed of the circuit is slow. In this case, a circuit with a larger area needs to be designed to overcome this defect.

On the other hand, if you want to drive a relatively high-voltage component, you need to use a high-voltage transistor to design the drive circuit. Please refer to FIG. 1. FIG. 1 is a conventional inverter driving circuit, which is composed of a PMOS transistor above and an NMOS transistor below. The PMOS transistor system is connected to a relatively high-voltage potential VPP. The NMOS transistor system is connected to a relatively low potential VNN, and both the PMOS transistor and the NMOS transistor must be able to withstand voltages in the voltage difference range of VPP-VNN. For example, if the voltage difference between VPP-VNN is 10V, the PMOS transistor and the NMOS transistor must withstand 10V.

At the same time, in terms of component manufacturing, in the face of intense price competition, the selectivity of component manufacturing is becoming less and less, so the use of low-voltage components to complete relatively high-voltage circuit design is also a trend in current chip design.

One object of the present invention is to use a low-voltage component to design a driving circuit capable of driving a high-voltage or a negative-voltage load, so as to solve the circuit application that can still cope with a relatively high voltage difference under the limitation of process selection, and make the circuit more compatible. High, can not use the lower price and specifications of the component process.

Another object of the present invention is that, because low-voltage components are used to design the driving circuit, the components required are small, so the area required for the circuit manufacturing process can be saved. At the same time, when the circuit is operated, its parasitic capacitance and resistance are relatively small. Therefore, it is easier to drive the circuit, and the operation speed of the circuit is faster.

To achieve the above object, the present invention provides a gate driving circuit for driving a load of high voltage or negative voltage, including: a signal input terminal for inputting a digital input signal; a switch circuit connected to the signal input terminal It includes: a transient current generating unit, an inverter, a second PMOS transistor and a third PMOS transistor, wherein the transient current generating module, the input terminal of the inverter and the third PMOS transistor The crystal system is connected to the signal input terminal, and the output terminal of the inverter is connected to the second PMOS transistor; the instantaneous current generating unit, the second PMOS transistor and the third PMOS transistor system are connected to a first bias voltage. Power supply; a voltage peak control circuit connected to the switch circuit, which includes a first voltage input terminal, a second voltage input terminal, a current supply unit, a PMOS transistor unit and an NMOS transistor unit, wherein the first A voltage input terminal is connected to the gate of the PMOS transistor unit, the second voltage input terminal is connected to the gate of the NMOS transistor unit, and a drain of the PMOS transistor unit is connected to the NMOS transistor The drain of the element, the current supply unit is used to provide a low current and connected to the PMOS transistor unit; and a current controlled switch circuit is connected to the voltage peak control circuit, which includes a first current mirror, a first Two current mirrors and a ninth NMOS transistor; and a signal output terminal connected to the voltage peak control circuit and the ninth NMOS transistor to output a digital output signal to drive the load.

In one embodiment of the present invention, the transient current generating unit includes: a PMOS transistor, a gate of the PMOS transistor is connected to the signal input terminal, and a drain of the PMOS transistor is connected to a source; The resistor is connected to the PMOS transistor and the first bias power source; a first PMOS transistor, and the gate of the first PMOS transistor is connected to the PMOS transistor and the resistor, the source of the first PMOS transistor The pole is connected to the first bias power source.

In one embodiment of the present invention, the PMOS transistor unit includes: a fourth PMOS transistor, a fifth PMOS transistor, a sixth PMOS transistor, and a seventh PMOS transistor, wherein the fourth PMOS transistor The source of the transistor is connected to the drain of the first PMOS transistor and the current supply unit, the source of the fifth PMOS transistor is connected to the current supply unit, and the source of the sixth PMOS transistor is connected to the The drain of the second PMOS transistor and the current supply unit, and the source of the seventh PMOS transistor is connected to the drain of the third PMOS transistor and the current supply unit.

In one embodiment of the present invention, the NMOS transistor unit includes: a first NMOS transistor, a second NMOS transistor, a third NMOS transistor, and a fourth NMOS transistor, wherein the first NMOS transistor The drain of the transistor is connected to the drain of the fourth PMOS transistor, the drain of the second NMOS transistor is connected to the drain of the fifth PMOS transistor, and the drain of the third NMOS transistor is connected to the The drain of the sixth PMOS transistor, the drain of the fourth NMOS transistor is connected to the drain of the seventh PMOS transistor, and the source of the fourth NMOS transistor is connected to the drain of the ninth NMOS transistor. And the signal output.

In an embodiment of the present invention, the first current mirror includes: a fifth NMOS transistor and a sixth NMOS transistor, wherein a gate phase of the fifth NMOS transistor and the sixth NMOS transistor Connected, the drain of the fifth NMOS transistor is connected to the source of the first NMOS transistor, and the drain of the sixth NMOS transistor is connected to the source of the third NMOS transistor and the ninth NMOS transistor Gate.

In an embodiment of the present invention, the second current mirror includes: a seventh NMOS transistor and an eighth NMOS transistor, wherein the seventh NMOS transistor and the gate system phase of the eighth NMOS transistor Connected, the drain of the seventh NMOS transistor is connected to the source of the second NMOS transistor, and the drain of the eighth NMOS transistor is connected to the source of the third NMOS transistor and the ninth NMOS transistor Gate.

In one embodiment of the present invention, the first PMOS transistor, the second PMOS transistor, the third PMOS transistor, and the ninth NMOS transistor system switching transistor.

Therefore, the present invention uses the design of the voltage peak control circuit in the gate driving circuit to achieve the use of a low-voltage transistor element to complete a high-voltage or negative-voltage driving circuit. At the same time, through the design of the instantaneous current generating unit in the gate driving circuit, the use of the instantaneous current is used to accelerate the transmission of circuit signals without relatively consuming power.

In order to fully understand the purpose, features and effects of the present invention, the following specific embodiments are used in conjunction with the accompanying drawings to make a detailed description of the present invention, which will be described later:

Please refer to FIG. 2, which is a schematic diagram of a circuit structure of a gate driving circuit 1 according to an embodiment of the present invention. As shown in FIG. 2, the gate driving circuit 1 of the present invention cooperates with a first bias power source VPP and a second bias power source VNN to drive a load (not shown), which includes: a signal input terminal 10, A switching circuit 20, a voltage peak control circuit 30, a current-controlled switching circuit 40, and a signal output terminal 50.

The signal input terminal 10 inputs a digital input signal V _IN .

The switching circuit 20 includes a transient current generating unit 21, an inverter 22, a second PMOS transistor MP2, and a third PMOS transistor MP3. The instantaneous current generating module 21, the input terminal of the inverter 22 and the third PMOS transistor MP3 are connected to the signal input terminal 10, and the output terminal of the inverter 22 is connected to the second PMOS transistor MP2; The instantaneous current generating unit 22, the second PMOS transistor MP2, and the third PMOS transistor MP3 are connected to the first bias power source VPP.

The instantaneous current generating unit 21 includes a PMOS transistor 211, a resistor 212, and a first PMOS transistor MP1. The gate of the PMOS transistor 211 is connected to the signal input terminal 10 to input the digital input signal V _IN , and the drain of the PMOS transistor 211 is connected to the source. Thus, the PMOS transistor 211 can be regarded as a coupling capacitor. . One end of the resistor 212 is connected to the PMOS transistor 211, and the other end of the resistor 212 is connected to the first bias power source VPP. The gate of the first PMOS transistor MP1 is connected to the PMOS transistor 211 and the resistor 212, and the source of the first PMOS transistor MP1 is connected to the first bias power source VPP. In this way, the PMOS transistor 211 can couple the digital input signal V _IN to the resistor and the first PMOS transistor MP1, that is, to provide an instantaneous voltage signal to the first PMOS transistor MP1. And because one end of the resistor 212 is connected to the first bias power source VPP, the digital input signal V _IN coupled to the resistor will gradually weaken, and the instantaneous current generating module 21 can use a short time instantaneous current, The signal transmission speed becomes faster, that is, the transmission speed of the digital input signal V _IN from the signal input terminal 10 to the signal output terminal 50 becomes faster.

The voltage peak control circuit 30 includes a first voltage input terminal VA, a second voltage input terminal VB, a current supply unit 31, a PMOS transistor unit 32, and an NMOS transistor unit 33. The first voltage input terminal VA is connected to the gate of the PMOS transistor unit 32, and the second input terminal VB is connected to the gate of the NMOS transistor unit 33. The drain of the PMOS transistor unit 32 is connected to the drain of the NMOS transistor unit 33. In this way, the voltage peak control circuit 30 adjusts the voltages of the first voltage input terminal VA and the second voltage input terminal VB so that the withstand voltage of each transistor of the gate driving circuit 1 does not exceed its breakdown voltage. .

The current supply unit 31 is connected to the PMOS transistor unit 32. The response speed of the gate driving circuit 1 can be controlled by adjusting the current, and a fixed low current can be provided so that the digital input signal V _IN does not have a floating potential generated during switching and achieves power saving effects.

The PMOS transistor unit 32 includes a fourth PMOS transistor MP4, a fifth PMOS transistor MP5, a sixth PMOS transistor MP6, and a seventh PMOS transistor MP7. The source of the fourth PMOS transistor MP4 is connected to the drain of the first PMOS transistor MP1 and the current supply unit 31. The source of the fifth PMOS transistor MP5 is connected to the current supply unit 31. The source of the sixth PMOS transistor MP6 is connected to the drain of the second PMOS transistor MP2 and the current supply unit 31. The source of the seventh PMOS transistor MP7 is connected to the drain of the third PMOS transistor MP3 and the current supply unit. The first voltage input terminal VA can control the source / base potential of the fourth PMOS transistor MP4, the fifth PMOS transistor MP5, the sixth PMOS transistor MP6, and the seventh PMOS transistor MP7 at a minimum fixed at VA + VTH to avoid that the drain-source voltage Vds of the first PMOS transistor MP1, the second PMOS transistor MP2, and the third PMOS transistor MP3 is greater than its breakdown voltage.

The NMOS transistor unit 33 includes a first NMOS transistor MN1, a second NMOS transistor MN2, a third NMOS transistor MN3, and a fourth NMOS transistor MN4. The drain of the first NMOS transistor MN1 is connected to the drain of the fourth PMOS transistor MP4. The drain of the second NMOS transistor MN2 is connected to the drain of the fifth PMOS transistor MP5. The drain of the third NMOS transistor MN3 is connected to the drain of the sixth PMOS transistor MP6. The drain of the fourth NMOS transistor MN4 is connected to the drain of the seventh PMOS transistor MP7, and the source of the fourth NMOS transistor MN4 is connected to the drain of the ninth NMOS transistor MN9 and the signal output terminal. 50.

The current-controlled switching circuit 40 includes a first current mirror 41, a second current mirror 42, and the ninth NMOS transistor MN9.

The first current mirror 41 includes a fifth NMOS transistor MN5 and a sixth NMOS transistor MN6. The gates of the fifth NMOS transistor MN5 and the sixth NMOS transistor MN6 are connected, the drain of the fifth NMOS transistor MN5 is connected to the source of the first NMOS transistor MN1, and the sixth NMOS transistor The drain of the crystal MN6 is connected to the source of the third NMOS transistor MN3 and the gate of the ninth NMOS transistor MN9. The second current mirror 42 includes a seventh NMOS transistor MN7 and an eighth NMOS transistor MN8, wherein the gates of the seventh NMOS transistor MN7 and the eighth NMOS transistor MN8 are connected, and the seventh NMOS The drain of transistor MN7 is connected to the source of the second NMOS transistor MN2, and the drain of the eighth NMOS transistor MN8 is connected to the source of the third NMOS transistor MN3 and the ninth NMOS transistor MN9. Gate. The second signal input terminal VB can control the source / base potential of the first NMOS transistor MN1, the second NMOS transistor MN2, the third NMOS transistor MN3, and the fourth NMOS transistor MN4 at a maximum fixed at VB-VTH to avoid the drain-source of the fifth NMOS transistor MN5, the sixth NMOS transistor MN6, the seventh NMOS transistor MN7, the eighth NMOS transistor MN8, and the ninth NMOS transistor MN9 The pole voltage Vds is greater than its breakdown voltage. In this way, the digital output signal V _{OUT of} the signal output terminal 50 is the highest VB-VTH. Therefore, the specifications of the load (not shown) connected to the signal output terminal 50 can be selected by controlling VB-VTH.

Please refer to FIG. 3, which is a schematic diagram of a first operation state of the gate driving circuit 1 according to an embodiment of the present invention. Among them, in this first operating state, the digital input signal V _IN is switched from a low potential state L (VNN) to a high potential state H (VPP).

First, when the digital input signal V _IN is switched from a low potential state L to a high potential state H, the first PMOS transistor MP1 and the third PMOS transistor MP3 are turned off. Since the inverter 22 converts the digital input signal V _IN from a high potential state H to a low potential state L, the second PMOS transistor MP2 is turned on. As such, the sources of the fourth PMOS transistor MP4, the fifth PMOS transistor MP5, and the seventh PMOS transistor MP7 only input a low current i _S provided by the current supply unit 31, and the sixth PMOS transistor The source of MP6 inputs the low current i _S and the current I _{P2 of} the second PMOS transistor MP2.

Second, since the seventh NMOS transistor MN7 and the eighth NMOS transistor MN8 are a set of current mirrors, the drain current of the eighth NMOS transistor MN8 and the drain current of the seventh NMOS transistor MN7 are Equally large (i _S ), that is, the current I _P2 (from the first bias power source VPP) of the second PMOS transistor MP2 is much larger than the drain current (i _S ) of the eighth NMOS transistor MN8, so that The gate input signal of the ninth NMOS transistor MN9 is a high potential state H, so that the ninth NMOS transistor MN9 is turned on, and the source terminal of the ninth NMOS transistor MN9 is connected to a second bias power source VNN. The digital output signal V _OUT is in a low potential state L.

Please refer to FIG. 4, which is a schematic diagram of a second operation state of the gate driving circuit 1 according to an embodiment of the present invention. In this second operating state, the digital input signal V _IN is switched from a high-potential state H (VPP) to a low-potential state L (VNN).

First, when the digital input signal V _IN is switched from a high potential state H to a low potential state L, the third PMOS transistor MP3 is turned on. Since the inverter 22 converts the digital input signal V _IN from a low potential state L to a high potential state H, the second PMOS transistor MP2 is turned off. The PMOS transistor 211 couples the low potential state L of the digital input signal V _IN to the first PMOS transistor MP1, and the first PMOS transistor MP1 is turned on, so that the drain of the first PMOS transistor MP1 outputs an instant. The short-time high current I _P1 to the fourth PMOS transistor MP4, so that the signal transmission speed becomes faster, that is, the transmission speed of the digital input signal V _IN from the signal input terminal to the signal output terminal 50 becomes faster. In addition, since the output terminal of the PMOS transistor 211 is connected to the resistor 212, the gate input signal of the first PMOS transistor MP1 will gradually decrease to turn off the first PMOS transistor MP1.

Secondly, because the second PMOS transistor MP2 is turned off, the eighth NMOS transistor MN8 is an input signal to the gate of the ninth NMOS transistor MN9 at a low potential state L. Thus, the ninth NMOS transistor MN9 The system is turned off, and since the third PMOS transistor MP3 outputs a current IP3 from the first bias power source VPP, the digital output signal V _OUT is in a high potential state H.

Therefore, the gate driving circuit of the present invention controls a first PMOS transistor, a second PMOS transistor, and a third PMOS by a digital input signal (high-potential state or low-potential state) inputted from the signal input terminal. The switching state of the transistor; and, a current is provided by a current supply unit to a fourth PMOS transistor, a fifth PMOS transistor, a sixth PMOS transistor, and a seventh PMOS transistor. The instantaneous current generating module makes the signal transmission speed faster by a short-time instantaneous current to achieve the effect of saving power. Furthermore, a first current mirror and a second current mirror are used to control the ninth NMOS transistor. The switching state of the signal output terminal to determine the digital output signal at the signal output terminal; and by controlling the voltage of the first voltage input terminal and the second voltage input terminal of the voltage peak control circuit, the transistor of the gate driving circuit does not exceed its breakdown voltage In order to achieve the purpose of driving high voltage or negative pressure load by low voltage transistor components.

The present invention has been disclosed in the foregoing with a preferred embodiment, but those skilled in the art should understand that this embodiment is only for describing the present invention, and should not be interpreted as limiting the scope of the present invention. It should be noted that all changes and substitutions equivalent to this embodiment should be included in the scope of the present invention. Therefore, the scope of protection of the present invention shall be defined by the scope of the patent application.

1‧‧‧Gate driving circuit

10‧‧‧Signal input

20‧‧‧Switch circuit

21‧‧‧Momentary current generating unit

211‧‧‧PMOS transistor

212‧‧‧Resistor

22‧‧‧Inverter

30‧‧‧Voltage peak control circuit

31‧‧‧Current supply unit

32‧‧‧PMOS transistor unit

33‧‧‧NMOS transistor unit

40‧‧‧Current Controlled Switching Circuit

41‧‧‧First Current Mirror

42‧‧‧Second Current Mirror

50‧‧‧Signal output

MP1 ~ MP7‧‧‧‧First PMOS transistor ~ Seventh PMOS transistor

MN1 ~ MN9‧‧‧‧First NMOS transistor ~ Ninth NMOS transistor

VA‧‧‧The first voltage input terminal

VB‧‧‧second voltage input terminal

V _IN ‧‧‧ Digital input signal

V _OUT ‧‧‧Digital output signal

VPP‧‧‧First Bias Power Supply

VNN‧‧‧Second Bias Power Supply

[Figure 1] is a conventional inverter drive circuit. [Fig. 2] A schematic diagram of a circuit structure of a gate driving circuit according to an embodiment of the present invention. [FIG. 3] It is a schematic diagram of a first operation state of a gate driving circuit according to an embodiment of the present invention. [FIG. 4] A schematic diagram of a second operation state of a gate driving circuit according to an embodiment of the present invention.

Claims (7)

A gate driving circuit is used to drive a load of high voltage or negative voltage, and includes: a signal input terminal for inputting a digital input signal; a switch circuit connected to the signal input terminal, which includes: a momentary current generation A unit, an inverter, a second PMOS transistor and a third PMOS transistor, wherein the instantaneous current generating module, the input terminal of the inverter and the third PMOS transistor system are connected to the signal input terminal, The output terminal of the inverter is connected to the second PMOS transistor; the instantaneous current generating unit, the second PMOS transistor and the third PMOS transistor system are connected to a first bias power source; a voltage peak control circuit, Is connected to the switching circuit, and includes a first voltage input terminal, a second voltage input terminal, a current supply unit, a PMOS transistor unit and an NMOS transistor unit, wherein the first voltage input terminal is connected to the PMOS The gate of the transistor unit, the second voltage input terminal is connected to the gate of the NMOS transistor unit, the drain of the PMOS transistor unit is connected to the drain of the NMOS transistor unit, and the current provides The element is used to provide a low current and connected to the PMOS transistor unit; and a current controlled switch circuit is connected to the voltage peak control circuit, which includes a first current mirror, a second current mirror and a ninth NMOS A transistor; and a signal output terminal connected to the voltage peak control circuit and the ninth NMOS transistor to output a digital output signal to drive the load. The gate driving circuit according to claim 1, wherein the transient current generating unit includes: a PMOS transistor, the gate of the PMOS transistor is connected to the signal input terminal, and the drain of the PMOS transistor is connected to the source A resistor connected to the PMOS transistor and the first bias power source; a first PMOS transistor whose gate is connected to the PMOS transistor and the resistor; the first PMOS transistor The source of the crystal is connected to the first bias power source. The gate driving circuit according to claim 1, wherein the PMOS transistor unit includes: a fourth PMOS transistor, a fifth PMOS transistor, a sixth PMOS transistor, and a seventh PMOS transistor, wherein the The source of the fourth PMOS transistor is connected to the drain of the first PMOS transistor and the current supply unit. The source of the fifth PMOS transistor is connected to the current supply unit. The source of the sixth PMOS transistor is Is connected to the drain of the second PMOS transistor and the current supply unit, and the source of the seventh PMOS transistor is connected to the drain of the third PMOS transistor and the current supply unit. The gate driving circuit according to claim 3, wherein the NMOS transistor unit includes: a first NMOS transistor, a second NMOS transistor, a third NMOS transistor, and a fourth NMOS transistor, wherein The drain of the first NMOS transistor is connected to the drain of the fourth PMOS transistor, the drain of the second NMOS transistor is connected to the drain of the fifth PMOS transistor, and the drain of the third NMOS transistor is connected Is connected to the drain of the sixth PMOS transistor, the drain of the fourth NMOS transistor is connected to the drain of the seventh PMOS transistor, and the source of the fourth NMOS transistor is connected to the ninth NMOS transistor Drain and the signal output. The gate driving circuit according to claim 4, wherein the first current mirror includes: a fifth NMOS transistor and a sixth NMOS transistor, wherein a gate of the fifth NMOS transistor and the sixth NMOS transistor The drain system of the fifth NMOS transistor is connected to the source of the first NMOS transistor, and the drain system of the sixth NMOS transistor is connected to the source of the third NMOS transistor and the ninth. NMOS transistor gate. The gate driving circuit according to claim 4, wherein the second current mirror includes: a seventh NMOS transistor and an eighth NMOS transistor, wherein the gate of the seventh NMOS transistor and the eighth NMOS transistor The drain system of the seventh NMOS transistor is connected to the source of the second NMOS transistor, and the drain system of the eighth NMOS transistor is connected to the source of the third NMOS transistor and the ninth. NMOS transistor gate. The gate driving circuit according to claim 1 or 2, wherein the first PMOS transistor, the second PMOS transistor, the third PMOS transistor, and the ninth NMOS transistor are a switching transistor.