TW201405275A - Driver circuit and current control circuit thereof - Google Patents

Abstract

A current control circuit is operable to control a driver circuit such that the driver circuit is operable to drive a power MOS correspondingly. The current control circuit includes a current mirror, a clamping PMOS, and a peak current control branch, wherein the peak current control branch includes a capacitor, a resistor, and a control NMOS. If a switch signal the capacitor receives is at a voltage level state, the control NMOS is turned on such that a first branch of the current mirror provides a peak current, and a second branch of the current mirror outputs a control current to a control node of the driver circuit correspondingly. Sequentially, a driving current outputted to the power MOS by the driver circuit decreases thereby turning the power MOS on.

Description

Drive circuit and current control circuit there

The present disclosure relates to an electronic circuit, and more particularly to a drive circuit and a current control circuit therefor.

Electronic products have become an integral part of modern life. In a wide variety of electronic devices, semiconductor components that can be used in these devices are needed. The characteristics of a semiconductor component are primarily determined by the process of making the component. Since semiconductor components are often complicated, the process is also subject to change. A variety of transistors with different characteristics are required in semiconductor components. High-voltage piezoelectric crystals are designed to meet the requirements of high-voltage operation.

In addition, in order to meet the needs of modern people, electronic products are gradually designed into a light and thin type to facilitate people to carry. Considering the trade-off between electronic products and their component speeds, how to design a power MOS semi-transistor with the same or even faster switching speed in the case of small maintenance area is discussed by those skilled in the art. One of the problems.

One aspect of the present invention relates to a current control circuit for controlling a drive circuit by which the aforementioned drive circuit drives a power MOS transistor. The current control circuit includes a current mirror, a clamped P-type MOS transistor, and a peak current control branch. Further, the peak The current control branch contains capacitors, resistors, and control N-type MOS transistors. The first current branch of the current mirror and one end of the second current branch are electrically coupled to a common end point, and the common end point is for receiving the first potential. The control terminal of the clamped P-type MOS transistor is configured to receive a reference voltage, and the first end of the clamped P-type MOS transistor is electrically coupled to the first current branch of the current mirror.

In addition, the first end of the capacitor in the aforementioned peak current control branch is for receiving the switching signal, and the second end outputs a coupling signal. The first end of the resistor is electrically coupled to the second end of the capacitor, and the second end is configured to receive a second potential. The control terminal of the N-type MOS transistor is electrically coupled to the second end of the capacitor, and the second end is electrically coupled to the second end of the clamped P-type MOS transistor.

When the aforementioned switching signal received by the first end of the capacitor is in a voltage level state, the control N-type MOS transistor is turned on, and the first current branch of the current mirror provides a peak current, the current mirror The second current branch correspondingly outputs a control current to the control terminal of the driving circuit, so that the driving voltage of the power gate outputted by the driving circuit to the power MOS transistor is decreased to turn on the power gold oxide Semi-transistor.

According to an embodiment of the invention, the first current branch of the current mirror provides the peak current for a specific time.

According to another embodiment of the invention, the aforementioned specific time is less than about 20 nanoseconds.

According to still another embodiment of the present invention, before the aforementioned peak current control branch The resistor discharges the aforementioned coupling signal.

According to still another embodiment of the present invention, the first potential is a positive potential, and the second potential is smaller than the first potential.

According to still another embodiment of the present invention, the power MOS transistor is a high voltage MOS transistor.

Another aspect of the present invention is directed to a drive circuit for driving a power MOS transistor. The aforementioned driving circuit includes a current control circuit, a first driving branch, and a second driving branch. Further, the current control circuit includes a current mirror, a first clamped P-type MOS transistor, and a peak current control branch. The first driving branch includes a current source, a second clamped P-type MOS transistor, and a first switch N-type MOS transistor. The second driving branch includes a current supply P-type MOS transistor, a third clamp P-type MOS transistor, and a second switch N-type MOS transistor. Among them, the peak current control branch includes a capacitor, a resistor, and a control N-type MOS transistor.

In addition, in the current control circuit, the first current branch of the current mirror and one end of the second current branch are electrically coupled to a common end point, and the common end point is used to receive the first potential. The control end of the first clamp P-type MOS transistor is configured to receive a reference voltage, and the first end thereof is electrically coupled to the first current branch of the current mirror. The control terminal of the second clamp P-type MOS transistor in the first driving branch is configured to receive the reference voltage, and the first end thereof is electrically coupled to the control terminal and the current source. The control terminal of the first switch N-type MOS transistor is configured to receive the reverse-phase switching signal, and the first end thereof is electrically coupled to the second clamp P-type MOS transistor Said the second end.

The control terminal of the current supply P-type MOS transistor in the second driving branch is electrically coupled to the control terminal, and the first terminal thereof is configured to receive the first potential. The control terminal of the third clamp P-type MOS transistor is configured to receive the reference voltage, and the first end thereof is electrically coupled to the second end of the current supply P-type MOS transistor, and the first end thereof The terminal outputs a driving voltage to the power gate of the aforementioned power MOS transistor. The control end of the second switch N-type MOS transistor in the second driving branch is configured to receive the switching signal, and the first end thereof is electrically coupled to the third clamping N-type MOS transistor Second end.

In addition, the first end of the capacitance of the peak current control branch in the aforementioned peak current control branch is for receiving the switching signal, and the second terminal outputs the coupling signal. The first end of the resistor is electrically coupled to the second end of the capacitor, and the second end of the resistor is configured to receive a second potential. The control terminal of the front control N-type MOS transistor is electrically coupled to the second end of the capacitor, and the first end thereof is electrically coupled to the second end of the clamped P-type MOS transistor.

As described above, when the aforementioned switching signal received by the first end of the capacitor is in a voltage level state, the control N-type MOS transistor is turned on, and the first current branch of the current mirror provides a peak current. The second current branch of the current mirror correspondingly outputs a control current to a control terminal of the driving circuit, so that a driving voltage of the power gate outputted by the driving circuit to the power MOS transistor is lowered to turn on the foregoing Power MOS semi-transistor.

According to an embodiment of the invention, the first current branch of the current mirror The road provides the aforementioned peak current for a specific time.

According to another embodiment of the invention, the aforementioned specific time is less than about 20 nanoseconds.

According to still another embodiment of the present invention, the resistor of the peak current control branch discharges the coupling signal.

According to still another embodiment of the present invention, the first potential is a positive potential, and the second potential is smaller than the first potential.

According to still another embodiment of the present invention, the power MOS transistor is a high voltage MOS transistor.

Yet another aspect of the present invention is directed to a current control circuit for controlling a drive circuit whereby a drive circuit drives a power MOS transistor. The current control circuit includes a current mirror, a clamped N-type MOS transistor, and a peak current control branch. Further, the aforementioned peak current control branch includes a capacitor, a resistor, and a P-type MOS transistor. The first current branch of the current mirror and one end of the second current branch are electrically coupled to a common end point, and the common end point is for receiving the first potential. The control terminal of the clamping N-type MOS transistor is configured to receive a reference voltage, and the first end thereof is electrically coupled to the first current branch of the current mirror.

In addition, the first end of the capacitor in the aforementioned peak current control branch is for receiving the switching signal, and the second end outputs a coupling signal. The first end of the resistor is electrically coupled to the second end of the capacitor, and the second end is configured to receive a second potential. The control terminal of the P-type MOS transistor is electrically coupled to the second end of the capacitor, and the first end thereof is electrically coupled to the second end of the clamped N-type MOS transistor. When the aforementioned capacitance is the aforementioned When the switching signal received at one end is in a voltage level state, the P-type MOS transistor is turned on, and the current is supplied by the first current branch of the current mirror, and the second current branch of the current mirror is correspondingly The current is drawn by the control terminal, and the driving voltage of the power gate outputted by the driving circuit to the power MOS transistor is increased to turn on the power MOS transistor.

According to an embodiment of the invention, the first current branch of the current mirror provides the peak current for a specific time.

According to another embodiment of the invention, the aforementioned specific time is less than about 20 nanoseconds.

According to still another embodiment of the present invention, the current control circuit further includes a voltage supply N-type MOS transistor, including a first end and a second end, wherein the first end is electrically coupled to the peak current control branch The second end of the P-type MOS transistor is controlled, and the second end is for receiving a high voltage potential.

According to still another embodiment of the present invention, the resistor of the peak current control branch charges the second end of the capacitor.

According to still another embodiment of the present invention, the first potential is a negative potential, and the second potential is greater than the first potential.

According to still another embodiment of the present invention, the power MOS transistor is a high voltage MOS transistor.

Still another aspect of the present invention is directed to a driving circuit for driving a power MOS transistor. The aforementioned driving circuit includes a current control circuit, a first driving branch, and a second driving branch. Further, the current control circuit includes a current mirror, a first clamp N-type gold oxide semi-electric crystal Body and peak current control branch. The first driving branch includes a current source, a second clamped N-type MOS transistor, and a first switch P-type MOS transistor. The second driving branch includes a current supply N-type MOS transistor, a third clamp N-type MOS transistor, and a second switch P-type MOS transistor. Wherein, the peak current control branch includes a capacitor, a resistor, and a P-type MOS transistor.

In addition, in the current control circuit, the first current branch of the current mirror and one end of the second current branch are electrically coupled to a common end point, and the common end point is used to receive the first potential. The control terminal of the first clamp N-type MOS transistor is configured to receive a reference voltage, and the first end thereof is electrically coupled to the first current branch of the current mirror. The control terminal of the second clamp N-type MOS transistor in the first driving branch is configured to receive the reference voltage, and the first end thereof is electrically coupled to the control terminal and the current source. The control terminal of the first switch P-type MOS transistor is configured to receive the inverted switch signal, and the first end thereof is electrically coupled to the second end of the second clamp N-type MOS transistor.

The control terminal of the current supply N-type MOS transistor in the second driving branch is electrically coupled to the control terminal, and the first end thereof is configured to receive the first potential. The control end of the third clamp N-type MOS transistor is configured to receive the reference voltage, and the first end thereof is electrically coupled to the second end of the current supply N-type MOS transistor, and the first end thereof The terminal outputs a driving voltage to the power gate of the aforementioned power MOS transistor. The control end of the second switch P-type MOS transistor in the second driving branch is configured to receive the switch signal, and the first end thereof is electrically coupled to the third clamp N-type MOS semi-electrode The second end of the body.

In addition, the first end of the capacitance of the peak current control branch in the current control circuit is for receiving the switching signal, and the second terminal outputs the coupling signal. The first end of the resistor is electrically coupled to the second end of the capacitor, and the second end is configured to receive a second potential. The control terminal of the P-type MOS transistor is electrically coupled to the second end of the capacitor, and the first end thereof is electrically coupled to the second of the first clamp N-type MOS transistor. end.

According to the above, when the first switch received by the first end of the capacitor is in a voltage level state, the P-type MOS transistor is turned on, and the first current branch of the current mirror provides a peak current. The second current branch of the current mirror correspondingly draws current from the control terminal, wherein the first end of the third clamped N-type MOS transistor is output to the power of the power MOS transistor The aforementioned driving voltage of the gate rises to turn on the aforementioned power MOS transistor.

According to an embodiment of the invention, the first current branch of the current mirror provides the peak current for a specific time.

According to another embodiment of the invention, the aforementioned specific time is less than about 20 nanoseconds.

According to still another embodiment of the present invention, the driving circuit further includes a voltage supply N-type MOS transistor, including a first end and a second end, wherein the first end is electrically coupled to the control P type of the current control circuit. The second end of the MOS transistor and the second end are configured to receive a high voltage potential.

According to still another embodiment of the present invention, before the aforementioned peak current control branch The resistor charges the second end of the capacitor.

According to still another embodiment of the present invention, the first potential is a positive potential, and the second potential is greater than the first potential.

According to still another embodiment of the present invention, the power MOS transistor is a high voltage MOS transistor.

Therefore, according to the technical content of the present invention, an embodiment of the present invention provides a driving circuit and a current control circuit therein, thereby improving a propagation delay phenomenon of the power transistor, and further reducing the transmission delay phenomenon to 50 nm. Within seconds.

In order to make the description of the present disclosure more complete and complete, reference is made to the accompanying drawings and the accompanying drawings. However, the embodiments provided are not intended to limit the scope of the invention, and the description of the operation of the structure is not intended to limit the order of its execution, and any device that is recombined by the components produces equal devices. The scope covered by the invention.

The drawings are for illustrative purposes only and are not drawn to the original dimensions. On the other hand, well-known elements and steps are not described in the embodiments to avoid unnecessarily limiting the invention.

In addition, the term "coupled" or "connected" as used herein may mean that two or more elements are in direct physical or electrical contact with each other, or indirectly in physical or electrical contact with each other, or Multiple components operate or act upon each other.

1 is a schematic diagram of a driving circuit for driving a power MOS transistor MP0 according to an embodiment of the invention. As shown, the drive circuit 100 includes a current control circuit 110 and a drive stage 120. The drive stage 120 in turn includes a first drive branch 122 and a second drive branch 124.

In the present embodiment, the power MOS transistor MPO is a P-type high voltage MOS transistor. High voltage MOS (HVMOS) is a transistor that can withstand high voltage. In one embodiment, it refers to a high voltage that can withstand up to about 10 volts or more, which is different from the common normal withstand voltage ( Such as 3.3 volts or 5 volts). In some semiconductor fabrication techniques, a power MOS transistor having a source and a drain that can withstand high voltages and a gate that can only withstand a small voltage (eg, 5 volts) can be fabricated. The power MOS semi-transistor designed in this way will be able to reduce the on-resistance (R _DS (on)) of the power MOS transistor in a small area, further achieving the power MOS half. The transmission delay of the transistor is reduced, and the rising time and the falling time are reduced.

In order to enable the above-mentioned type of power MOS semi-transistor to further improve the propagation delay phenomenon when driving, the embodiment of the present invention designs a driving circuit, which is derived from the configuration of the overall circuit architecture. Sexual operation can meet the requirements of this type of power MOS semi-transistor, and reduce the transmission delay phenomenon of power MOS semi-transistor to less than 50 nanoseconds. The structure and electrical operation mode of the driving circuit of the embodiment of the present invention will be described in detail below to make the object and effect of the present invention easier to understand.

First, in the overall operational concept, the switching signal is received by the current control circuit 110, and the control current is output to the driving stage 120 according to the switching signal, so that the driving stage 120 drives the power MOS transistor MP0 accordingly.

The current control circuit 110 includes a current mirror 112, a first clamped P-type MOS transistor MP3, and a peak current control branch 114. As shown in FIG. 1, further, the current mirror 112 includes a first P-type MOS transistor MP1 and a second P-type MOS transistor MP2, wherein the first P-type MOS transistor is located at the first A current branch, and the second P-type MOS transistor MP2 is located on the second current branch. In addition, the peak current control branch 114 includes a capacitor C1, a resistor R1, and a control N-type MOS transistor MN1.

The first current branch of the current mirror 112 of the current control circuit 110 and one end of the second current branch are electrically coupled to the common terminal N1 for receiving the first potential VGH. The control terminal of the first clamped P-type MOS transistor MP3 of the current control circuit 110 is configured to receive a reference voltage VM, and the first end thereof is electrically coupled to the first current branch of the current mirror 112.

In the peak current control branch 114 of the current control circuit 110, the first end of the capacitor C1 is for receiving the switching signal IN, and the second terminal outputs a coupling signal. The first end of the resistor R1 is electrically coupled to the second end of the capacitor C1, and the second end thereof is configured to receive the second potential VSS. The control terminal of the N-type MOS transistor MN1 is electrically coupled to the second end of the capacitor C1, and the first end thereof is electrically coupled to the second terminal of the first clamp P-type MOS transistor MP3.

It should be noted that, in the embodiment of the present invention, the control terminal of each type of metal oxide semi-transistor may be a gate, and the first end and the second end thereof may be selectively used according to the requirements of the actual circuit configuration. Extreme or bungee.

For electrical operation, peak current control in current control circuit 110 When the switch signal IN received by the first end of the capacitor C1 of the branch 114 is in a high state, the N-type MOS transistor MN1 is controlled to be turned on, and the first current branch of the current mirror 112 provides a peak current, and the current mirror is The two current branches correspondingly output control current to the control terminal N2 of the driving stage 120, so that the driving voltage of the driving stage 120 outputted to the control terminal of the power MOS transistor M0 is decreased to turn on the power MOS transistor MPO. .

It should be further noted that the first current branch of the current mirror 112 in the current control circuit 110 provides a peak current for a certain period of time. In an embodiment, the specific time is less than about 20 nanoseconds. Therefore, the current control circuit 110 of the driving circuit 100 of the embodiment of the present invention can rapidly generate a peak current in a very short time, and correspondingly at the same time. The control current is output to the driving stage 120 for the purpose of quickly turning on the power MOS transistor MP0. However, the present invention is not intended to limit the present invention, and those skilled in the art can selectively adopt appropriate parameters, and the concept is the same as the present invention, that is, falls within the scope of the present invention.

In one embodiment, after the peak current derives the effect of rapidly turning on the power MOS transistor MP0, the resistor R1 of the peak current control branch 114 in the current control circuit 110 discharges the second end of the capacitor C1. Therefore, the N-type MOS transistor MN1 is turned off, and at this time, the peak current will also disappear together, so that after the power MOS transistor M0 is quickly turned on, the N-type MOS transistor MN1 is turned off. There will be no unnecessary electrical energy loss on the current control circuit 110.

The driving branch 122 of the driving stage 120 includes a current source 123, a second clamp P-type MOS transistor MP4, and a first switching N-type MOS transistor MN2. The control terminal of the second clamp P-type MOS transistor MP4 is configured to receive the reference voltage VM, the first end of which is electrically coupled to the control terminal N2 and the current source 123, and is configured to receive the current mirror in the current control circuit 110. The control current of the second current branch of 112 is output. The control end of the first switch N-type MOS transistor MN2 is configured to receive an inverted switch signal The first end is electrically coupled to the second end of the second clamp P-type MOS transistor MP4.

Furthermore, the second driving branch 124 of the driving stage 120 includes a current supply P-type MOS transistor MP5, a third clamp P-type MOS transistor M6, and a second switch N-type MOS transistor MN3. . The control terminal of the current supply P-type MOS transistor 5 is electrically coupled to the control terminal N2, and the first terminal thereof is configured to receive the first potential VGH. The control terminal of the third clamp P-type MOS transistor 6 is configured to receive the reference voltage VM, and the first end thereof is electrically coupled to the second end of the current supply P-type MOS transistor 5, and the first end thereof The terminal outputs a driving voltage to the control terminal of the power MOS transistor MP0. The control terminal of the second switch N-type MOS transistor MN3 is configured to receive the switch signal IN, and the first end thereof is electrically coupled to the second end of the third clamp P-type MOS transistor.

In this embodiment, in the electrical operation, when the switching signal IN received by the first end of the capacitor C1 of the peak current control branch 114 in the current control circuit 110 is in a high state, the N-type MOS transistor is controlled. MN1 is turned on, and the second switch N-type MOS transistor MN3 of the second driving branch 124 in the driving stage 120 is turned on, the first current branch of the current mirror 112 provides a peak current, and the second current branch of the current mirror 112 The circuit accordingly outputs a control current to the control terminal N2 to control the voltage rise of the terminal N2. Since the voltage of the control terminal N2 is the control terminal receiving of the current supply P-type MOS transistor 5 The voltage, and thus the current supply P-type MOS transistor MP5, will be turned off at the voltage rise of control terminal N2.

At this time, the first end of the second switch N-type MOS transistor MN3 of the second driving branch 124 draws the output voltage Vp, so that the first end of the third clamp P-type MOS transistor 6 is output. The driving voltage Vp of the control terminal of the power MOS transistor MPO is lowered to turn on the power MOS transistor MP0.

In one embodiment, the first potential VGH is a positive potential and the second potential VSS is less than the first potential VG. In an embodiment, the second potential VSS can be a ground potential.

2 is a schematic diagram of a driving circuit for driving a power MOS transistor MN0 according to an embodiment of the invention. As shown, the drive circuit 200 includes a current control circuit 210 and a drive stage 220. The drive stage 220 in turn includes a first drive branch 222 and a second drive branch 224.

In the present embodiment, the power MOS semi-transistor MN0 is an N-type high-voltage MOS semi-transistor, and the characteristics of the high-voltage MOS semi-transistor have been described in detail in FIG. 1 and will not be described herein.

In order to enable the above-mentioned type of power MOS semi-transistor to further improve the propagation delay phenomenon when driving, the embodiment of the present invention designs a driving circuit, which is derived from the configuration of the overall circuit architecture. Sexual operation can meet the requirements of this type of power MOS semi-transistor, and reduce the transmission delay phenomenon of power MOS semi-transistor to less than 50 nanoseconds. The structure and electrical operation mode of the driving circuit of the embodiment of the present invention will be described in detail below to make the object and effect of the present invention easier to understand.

First, in the overall operational concept, it is connected by the current control circuit 210. The switching signal is received, and the control current is output to the driving stage 220 according to the switching signal, so that the driving stage 220 drives the power MOS transistor MN0 accordingly.

The current control circuit 210 includes a current mirror 212, a first clamp N-type MOS transistor MN1, and a peak current control branch 214. As shown in FIG. 2, further, the current mirror 212 includes a first N-type MOS transistor MN2 and a second N-type MOS transistor MN3, wherein the first N-type MOS transistor MN2 is located at A current branch, and the second N-type MOS transistor MN3 is located on the second current branch. In addition, the peak current control branch 214 includes a capacitor C1, a resistor R1, and a control P-type MOS transistor MP1.

The first current branch of the current mirror 212 of the current control circuit 210 and one end of the second current branch are electrically coupled to the common terminal N1 for receiving the first potential VEE. The control terminal of the first clamp N-type MOS transistor MN1 of the current control circuit 210 is configured to receive the reference voltage VM, and the first end thereof is electrically coupled to the first current branch of the current mirror 212.

In the peak current control branch 214 of the current control circuit 210, the first end of the capacitor C1 is for receiving the switching signal IN and the second terminal is for outputting the coupling signal. The first end of the resistor R1 is electrically coupled to the second end of the capacitor C1, and the second end thereof is configured to receive the second potential VDDX. The control terminal of the P-type MOS transistor is electrically coupled to the second end of the capacitor C1, and the first end thereof is electrically coupled to the second end of the first clamp N-type MOS transistor MN1. .

In electrical operation, when the first end of the capacitor C1 of the peak current control branch 214 in the current control circuit 210 receives the switching signal IN as a low state When the capacitor C1 outputs a coupling signal to control the P-type MOS transistor MP1 to be turned on, at this time, the first current branch of the current mirror 212 provides a peak current, and the second current branch of the current mirror is correspondingly driven by the driver stage. The control terminal N2 of 220 draws current, so that the driving voltage of the driving stage 220 outputted to the control terminal of the power MOS transistor MN0 rises to turn on the power MOS transistor MN0.

It should be further noted that the first current branch of the current mirror 212 in the current control circuit 210 provides a peak current for a certain period of time. In an embodiment, the specific time is less than about 20 nanoseconds. Therefore, the current control circuit 210 of the driving circuit 200 of the embodiment of the present invention can rapidly generate a peak current in a very short time, and correspondingly at the same time. The current is drawn by the driver stage 220 to achieve the purpose of quickly turning on the power MOS transistor MN0. However, the present invention is not intended to limit the present invention, and those skilled in the art can selectively adopt appropriate parameters, and the concept is the same as the present invention, that is, falls within the scope of the present invention.

In one embodiment, after the peak current derives the effect of rapidly turning on the power MOS transistor MN0, the resistor R1 of the peak current control branch 214 in the current control circuit 210 charges the second end of the capacitor C1. Therefore, the P-type MOS transistor MP1 is turned off, and at this time, the peak current will also disappear together, so that after the power MOS transistor MN0 is quickly turned on, the P-type MOS transistor is turned off. There will be no unnecessary electrical energy loss on the current control circuit 210.

In another embodiment, the current control circuit 210 further includes a voltage supply N-type MOS transistor MN7, and the voltage supply N-type MOS transistor MN7 includes a first end and a second end. The second end is configured to receive a high voltage potential VGH, the first end is electrically coupled to the second end of the P-type MOS transistor MP1 of the peak current control branch 214, and the control terminal thereof can receive an external potential VDD. For example, the second potential VDDX may be VDD-Vth (threshold voltage).

Under the design architecture, when the P-type MOS transistor MP1 is controlled to be turned on, the second end of the first N-type MOS transistor MN2 on the first branch of the current mirror 212 is drawn by the high voltage potential VGH. Rather than drawing a current to the second potential VDDX to generate the aforementioned peak current. In this way, the overall circuit operation can be made more stable.

The first driving branch 222 of the driving stage 220 includes a current source 223, a second clamp N-type MOS transistor MN4, and a first switch P-type MOS transistor MP2. The control terminal of the second clamp N-type MOS transistor MN4 is configured to receive the reference voltage VM, and the first end thereof is electrically coupled to the control terminal N2 and the current source 223. The control end of the first switch P-type MOS transistor is used to receive an inverted switch signal The first end is electrically coupled to the second end of the second clamp N-type oxynitride MN4.

Furthermore, the second driving branch 224 of the driving stage 220 includes a current supply N-type MOS transistor MN6, a third clamp N-type MOS transistor MN5, and a second switch P-type MOS transistor MP3. . The control terminal of the current supply N-type MOS transistor MN6 is electrically coupled to the control terminal N2, and the first terminal thereof is configured to receive the first potential VEE. The control terminal of the third clamp N-type MOS transistor MN5 is configured to receive the reference voltage VM, and the first end thereof is electrically coupled to the second end of the current supply N-type MOS transistor MN6, and the first end thereof The terminal outputs a driving voltage to the control terminal of the power MOS transistor MN0. The control end of the second switch P-type MOS transistor MP3 is used to receive the open The signal IN is turned off, and the first end thereof is electrically coupled to the second end of the third clamp N-type oxynitride MN5.

In the embodiment, when the switching signal IN received by the first end of the capacitor C1 of the peak current control branch 214 in the current control circuit 210 is in a low state, the capacitor C1 outputs a coupling signal to make the control P. The MOS transistor MP1 is turned on, and the second switch P-type MOS transistor MP3 of the second driving branch 224 in the driving stage 220 is turned on, and the first current branch of the current mirror 212 generates a peak current, and the current mirror The second current branch of 212 accordingly draws current from control terminal N2, controlling the voltage drop at terminal N2. Since the voltage of the control terminal N2 is the voltage received by the control terminal of the current supply N-type MOS transistor MN6, the current supply N-type MOS transistor MN6 will be turned off at the voltage drop of the control terminal N2.

At this time, the first end of the second switch P-type MOS transistor MP3 of the second driving branch 224 supplies a voltage, so that the first end of the third clamp N-type MOS transistor MN5 is output to the power. The driving voltage Vp of the control terminal of the metal oxide semiconductor MN0 rises to turn on the power MOS transistor MN0.

In an embodiment, the first potential VEE is a negative potential, and the second potential VDDX is greater than the first potential VEE.

It will be apparent from the above-described embodiments of the present invention that the application of the present invention has the following advantages. The embodiment of the present invention improves the propagation delay phenomenon of the power transistor by providing a driving circuit and a current control circuit therein, and further reduces the transmission delay phenomenon to within 50 nanoseconds. Furthermore, after the power MOS transistor is quickly turned on, the MOS transistor will be turned off due to the control of the peak current control branch in the current control circuit, so there will be no unnecessary power loss on the current control circuit.

The present disclosure has been disclosed in the above embodiments, but it is not intended to limit the disclosure, and any person skilled in the art can make various changes and refinements without departing from the spirit and scope of the disclosure. The scope of protection of the disclosure is subject to the definition of the scope of the patent application.

100, 200‧‧‧ drive circuit

110, 210‧‧‧ Current control circuit

112, 212‧‧‧current mirror

114, 214‧‧‧ Peak current control branch

120, 220‧‧‧ drive level

122, 222‧‧‧ first drive branch

123, 223‧‧‧ current source

124, 224‧‧‧Second drive branch

The above and other objects, features, advantages and embodiments of the present disclosure will be more apparently understood. The description of the drawings is as follows: FIG. 1 is a schematic diagram of a circuit of a driving circuit according to an embodiment of the disclosure; And FIG. 2 is a schematic circuit diagram of a driving circuit in another embodiment of the disclosure.

100‧‧‧ drive circuit

110‧‧‧ Current Control Circuit

112‧‧‧current mirror

114‧‧‧ Peak current control branch

120‧‧‧Driver

122‧‧‧First drive branch

123‧‧‧current source

124‧‧‧Second drive branch

Claims (26)

A current control circuit for controlling a driving circuit, wherein the driving circuit correspondingly drives a power MOS transistor, comprising: a current mirror comprising a first current branch and a second current branch, wherein One end of the first current branch and the second current branch are electrically coupled to a common end point for receiving a first potential; a clamped P-type MOS transistor, comprising a a control terminal, a first end, and a second end, wherein the control end is configured to receive a reference voltage, the first end is electrically coupled to the first current branch of the current mirror; and a peak current control branch The method includes a capacitor, including a first end, wherein the first end is configured to receive a switching signal, and a resistor includes a first end and a second end, wherein the first end is electrically coupled to the capacitor a second end, the second end is configured to receive a second potential; and a control N-type MOS transistor includes a control end and a first end, wherein the control end is electrically coupled to the capacitor The second end is electrically coupled to the clamped P-type The second end of the oxygen semiconductor, wherein the control N-type MOS transistor is turned on when the first signal received by the first end of the capacitor is in a voltage level state, the current mirror is first The current branch provides a peak current, and the second current branch of the current mirror correspondingly outputs a control current to a control terminal of the driving circuit, so that the driving circuit outputs power to the power MOS transistor One of the gates drives a voltage drop to turn on the power MOS transistor. The current control circuit of claim 1, wherein the first current branch of the current mirror provides the peak current for a specified time. The current control circuit of claim 2, wherein the specific time is less than about 20 nanoseconds. The current control circuit of claim 1, wherein the resistance of the peak current control branch discharges the coupled signal. The current control circuit of claim 1, wherein the first potential is a positive potential and the second potential is less than the first potential. The current control circuit of claim 1, wherein the power MOS transistor is a high voltage MOS transistor. A driving circuit for driving a power MOS transistor, comprising: a current control circuit comprising: a current mirror comprising a first current branch and a second current branch, wherein the first current branch And one end of the second current branch is electrically coupled to a common end point for receiving a first potential; a first clamped P-type MOS transistor, comprising a control end And a first end, wherein the control end is configured to receive a reference voltage, the first end is electrically coupled to the first current branch of the current mirror; and a peak current control branch includes: a capacitor, including a first end, wherein the first end is configured to receive a switching signal; a resistor includes a first end and a second end, wherein the first end is electrically coupled to the second end of the capacitor, The second end is configured to receive a second potential; and a control N-type MOS transistor includes a control end and a first end, wherein the control end is electrically coupled to the second end of the capacitor, The first end is electrically coupled to one of the second ends of the first clamped P-type MOS transistor; a first driving branch comprising: a current source; and a second clamped P-type MOS The crystal includes a control terminal and a first terminal, wherein the control terminal is configured to receive the reference voltage, the first terminal is electrically coupled to a control terminal and the current source; and a first switch N-type gold oxide The semi-transistor includes a control terminal and a first terminal, wherein the control terminal is configured to receive an inverted switching signal The first end is electrically coupled to one of the second ends of the second clamped P-type MOS transistor; and the second driving branch comprises: a current supply P-type MOS transistor, including a a control end and a first end, wherein the control end is electrically coupled to the control end, the first end is configured to receive the first potential; A third clamp P-type MOS transistor includes a control terminal and a first terminal, wherein the control terminal is configured to receive the reference voltage, and the first terminal is electrically coupled to the current supply P-type gold oxide a second end of the semi-transistor, the first end outputs a driving voltage to a power gate of the power MOS transistor; and a second switch N-type MOS transistor, including a control terminal and a a first end, wherein the control end is configured to receive the switch signal, the first end is electrically coupled to the second end of the third clamp P-type MOS transistor, wherein the first end of the capacitor When the switch receiving the switch signal is in a voltage level state, the control N-type MOS transistor is turned on, the first current branch of the current mirror provides a peak current, and the second current branch of the current mirror Correspondingly outputting a control current to the control terminal, wherein the driving voltage of the first gate of the third clamp P-type MOS transistor is output to the power gate of the power MOS transistor To turn on the power MOS transistor. The driving circuit of claim 7, wherein the first current branch of the current mirror provides the peak current for a specific time. The drive circuit of claim 8, wherein the specific time is less than about 20 nanoseconds. The driving circuit of claim 7, wherein the resistance of the peak current control branch discharges the second end of the capacitor. The driving circuit of claim 7, wherein the first potential is a positive potential and the second potential is less than the first potential. The driving circuit of claim 7, wherein the power MOS transistor is a high voltage MOS transistor. A current control circuit for controlling a driving circuit, wherein the driving circuit correspondingly drives a power MOS transistor, comprising: a current mirror comprising a first current branch and a second current branch, wherein One end of the first current branch and the second current branch are electrically coupled to a common end point for receiving a first potential; a clamped N-type MOS transistor, comprising a a control terminal and a first terminal, wherein the control terminal is configured to receive a reference voltage, the first end is electrically coupled to the first current branch of the current mirror; and a peak current control branch includes: The capacitor includes a first end, wherein the first end is configured to receive a switching signal; a resistor includes a first end and a second end, wherein the first end is electrically coupled to one of the capacitors The second end is configured to receive a second potential; and a control P-type MOS transistor includes a control terminal and a first terminal, wherein the control terminal is electrically coupled to the second capacitor The first end is electrically coupled to the clamp N-type oxy-half One end of the second crystal, The P-type MOS transistor is turned on when the switch signal received by the first end of the capacitor is in a voltage level state, and the current is supplied by the first current branch of the current mirror. The second current branch of the mirror correspondingly draws current from one of the control circuits, and the drive circuit outputs a voltage to the power gate of the power MOS transistor to increase the driving voltage to turn on the power. Gold oxide semi-transistor. The current control circuit of claim 13, wherein the first current branch of the current mirror provides the peak current for a specified time. The current control circuit of claim 14, wherein the particular time is less than about 20 nanoseconds. The current control circuit of claim 13, further comprising a voltage supply N-type MOS transistor, wherein the voltage supply N-type MOS transistor comprises a first end and a second end, the first end The second end of the control P-type MOS transistor is electrically coupled to the peak current control branch, and the second terminal is configured to receive a high voltage potential. The current control circuit of claim 13, wherein the resistance of the peak current control branch charges the second end of the capacitor. The current control circuit of claim 13, wherein the first potential is a negative potential and the second potential is greater than the first potential. The current control circuit of claim 13, wherein the power MOS transistor is a high voltage MOS transistor. A driving circuit for driving a power MOS transistor, comprising: a current control circuit comprising: a current mirror comprising a first current branch and a second current branch, wherein the first current branch And one end of the second current branch is electrically coupled to a common end point for receiving a first potential; a first clamped N-type MOS transistor, comprising a control end and a a first end, wherein the control end is configured to receive a reference voltage, the first end is electrically coupled to the first current branch of the current mirror; and a peak current control branch includes: a capacitor, including a first One end, wherein the first end is configured to receive a switching signal; a resistor includes a first end and a second end, wherein the first end is electrically coupled to the second end of the capacitor, the second The terminal is configured to receive a second potential; and a control P-type MOS transistor includes a control terminal and a first terminal, wherein the control terminal is electrically coupled to the second end of the capacitor, the first The terminal is electrically coupled to one of the first clamp N-type oxynitride transistors ; A first driving branch, comprising: a current source; a second clamped N-type MOS transistor comprising a control terminal and a first terminal, wherein the control terminal is configured to receive the reference voltage, the first terminal is coupled to a control terminal and the current source; A first switch P-type MOS transistor includes a control terminal and a first terminal, wherein the control terminal is configured to receive an inverted switch signal, and the first terminal is electrically coupled to the second clamp N a second end of the MOS transistor; a second driving branch comprising: a current supply N-type MOS transistor, comprising a control end and a first end, wherein the control end is electrically coupled In the control terminal, the first end is configured to receive the first potential; a third clamp N-type MOS transistor includes a control end and a first end, wherein the control end is configured to receive the reference a first end electrically coupled to the second end of the current supply N-type MOS transistor, the first end outputting a driving voltage to a power gate of the power MOS transistor; a second switch P-type MOS transistor, comprising a control end and a first end, wherein the control The terminal is configured to receive the switch signal, and the first end is electrically coupled to one of the second ends of the third clamp N-type MOS transistor. The P-type MOS transistor is turned on when the switch signal received by the first end of the capacitor is in a voltage level state, and the first current branch of the current mirror provides a peak current, the current The second current branch of the mirror correspondingly draws current from the control terminal, wherein the first end of the third clamped N-type MOS transistor is output to the power MOS transistor The driving voltage of the power gate rises to turn on the power MOS transistor. The drive circuit of claim 20, wherein the first current branch of the current mirror provides the peak current for a specified time. The drive circuit of claim 21, wherein the particular time is less than about 20 nanoseconds. The driving circuit of claim 20, further comprising a voltage supply N-type MOS transistor, wherein the voltage supply N-type MOS transistor comprises a first end and a second end, the first end is electrically The second end of the P-type MOS transistor is coupled to the current control circuit, and the second end is configured to receive a high voltage potential. The driving circuit of claim 20, wherein the resistor of the peak current control branch charges the second end of the capacitor. The driving circuit of claim 20, wherein the first potential is a positive potential and the second potential is greater than the first potential. The driving circuit of claim 20, wherein the power MOS transistor is a high voltage MOS transistor.