CN219611748U - High-voltage floating gate driving circuit and driving chip thereof - Google Patents
High-voltage floating gate driving circuit and driving chip thereof Download PDFInfo
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- CN219611748U CN219611748U CN202321370890.6U CN202321370890U CN219611748U CN 219611748 U CN219611748 U CN 219611748U CN 202321370890 U CN202321370890 U CN 202321370890U CN 219611748 U CN219611748 U CN 219611748U
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Classifications
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K7/00—Modulating pulses with a continuously-variable modulating signal
- H03K7/08—Duration or width modulation ; Duty cycle modulation
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/0175—Coupling arrangements; Interface arrangements
- H03K19/017509—Interface arrangements
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
- H03K3/02—Generators characterised by the type of circuit or by the means used for producing pulses
- H03K3/353—Generators characterised by the type of circuit or by the means used for producing pulses by the use, as active elements, of field-effect transistors with internal or external positive feedback
- H03K3/356—Bistable circuits
- H03K3/356017—Bistable circuits using additional transistors in the input circuit
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02B—CLIMATE CHANGE MITIGATION TECHNOLOGIES RELATED TO BUILDINGS, e.g. HOUSING, HOUSE APPLIANCES OR RELATED END-USER APPLICATIONS
- Y02B70/00—Technologies for an efficient end-user side electric power management and consumption
- Y02B70/10—Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes
Abstract
The utility model discloses a high-voltage floating gate driving circuit and a driving chip thereof, which comprise a PWM control signal input end, an inverter group, a level shift circuit and a gate driving circuit which are sequentially connected, wherein the inverter group is used for converting an input PWM control signal into a group of complementary signals, and the level shift circuit comprises two NMOS (N-channel metal oxide semiconductor) tubes and four PMOS (P-channel metal oxide semiconductor) tubes. The circuit has simple structure, omits a narrow pulse generating circuit at the input end and a pulse filtering and RS trigger at the output end, and replaces two resistors with four PMOS (P-channel metal oxide semiconductor) tubes in the level shifting circuit, so that the process deviation is smaller, the layout area is reduced, and the cost is reduced; the simulation device is few, the anti-interference capability is strong, and the robustness is higher.
Description
Technical Field
The utility model relates to the field of integrated circuit design, in particular to a high-voltage floating gate driving circuit and a driving chip thereof.
Background
The gate driving circuit of the high-voltage floating power tube is generally used for driving the high-voltage side MOS power tube with a bridge structure, and the gate driving circuit of the high-voltage side MOS power tube is synchronously operated at the floating high voltage because the high-voltage side MOS power tube is operated at the floating high voltage. In such a high-side floating gate driving circuit, a level shift circuit as a core part may transmit a logic control signal of a high-side channel low-voltage region to the high-voltage region for generating a final floating gate control signal.
A level shift circuit of the conventional scheme is shown in fig. 1. IN is an input PWM control signal and VCC is a low voltage power supply, e.g., 5V; GND is common ground, the global reference voltage; VS is floating ground, namely the reference voltage of the high-voltage side driving circuit, and dynamic change is presented relative to global GND, part of the time period is in high-level voltage (floating ground), part of the time period is in 0V, and the rated high-level voltage is generally between tens of V and hundreds of V; VB is a floating high-voltage power supply, and the voltage is generally a static value of not more than 20V relative to VS, but is a dynamic value of between tens of V and hundreds of V relative to GND; HO is an output control signal of the high-voltage side and is finally used for driving the grid electrode of the high-voltage side power tube. The level shift circuit includes passive device resistors R0 and R1 and MOS transistors NM0 and NM1, where the drain voltages of NM0 and NM1 are at most the voltage of VB relative to GND in its off state, and a pre-calculated on current is generated in its on state to flow through R0 or R1, and a voltage drop with amplitude of about VB-VS is generated on R0 or R1 with reference to VS, so as to drive the gate of the pulse filter at the subsequent stage, that is, the on state of NM0 or NM1, where the drain voltage is possibly VS, so that NM0 or NM1 is in a high-voltage working state not lower than VS for a long period of time, and as known from p=u×i, the long-term on power consumption is larger. In order to reduce average quiescent current and avoid various factors such as device damage caused by long-term conduction of NM0 or NM1 under high voltage, practical level shift circuits usually operate NM0 or NM1 in a pulse on state, and are turned on only for a short time, and NM0 and NM1 are turned off for most of the time. Therefore, the level shift circuit requires a narrow pulse generating circuit at the input and pulse filtering and RS flip-flop at the output. Furthermore, since the initial state of the RS flip-flop is random, in order to avoid that the final power tube is randomly turned on after power-on, a power-on reset circuit is also required to be independently implemented on the high voltage side (the power-on reset signal on the low voltage side cannot be transmitted), and the RS flip-flop is set to be in a default state for turning off the power tube after power-on.
However, the conventional high voltage floating gate driving circuit has the following drawbacks: 1. the high-voltage side driving circuit has a complex structure, the input end of the level shifting circuit needs a narrow pulse generating circuit, the output end needs a pulse filtering and RS trigger, and the power-on default state setting circuit of the high-voltage side; 2. in the level shift circuit, the ideal value of the A, B node potential is either VS with a relatively high level or VB with a relatively low level, the absolute voltage value of the relatively low level is determined by the on current of NM0 or NM1 and the resistance value of R0 or R1, the influence of manufacturing process fluctuation, working temperature and working voltage is larger, and the superposition possible error of a plurality of factors can reach +/-40%; 3. in the level shift circuit, the passive device resistors R0 and R1 have a large area in the chip.
Disclosure of Invention
The utility model aims to: in order to solve the defects of complex structure, large area and high circuit requirement of a high-voltage floating gate driving circuit in the prior art, the utility model provides a high-voltage floating gate driving circuit and a driving chip thereof.
The technical scheme is as follows: the high-voltage floating gate driving circuit comprises a PWM control signal input end, an inverter group, a level shift circuit and a gate driving circuit which are connected in sequence, wherein the inverter group is used for converting an input PWM control signal into a group of complementary signals, and the level shift circuit comprises a first NMOS tube NM0, a second NMOS tube NM1, a first PMOS tube PM0, a second PMOS tube PM1, a third PMOS tube PM2 and a fourth PMOS tube PM3; the sources of the first PMOS tube PM0 and the second PMOS tube PM1 are connected with a floating high-voltage power supply VB, the floating high-voltage power supply VB is at least 10V, the grid electrodes are respectively connected with the sources of the fourth PMOS tube PM3 and the third PMOS tube PM2, and the drain electrodes are respectively connected with the sources or the drain electrodes of the third PMOS tube PM2 and the fourth PMOS tube PM3; the gates of the third PMOS tube PM2 and the fourth PMOS tube PM3 are connected with a floating ground VS, the drains of the third PMOS tube PM2 and the fourth PMOS tube PM3 are respectively connected with the drains of the first NMOS tube NM0 and the second NMOS tube NM1, the source of the third PMOS tube PM2 or the fourth PMOS tube PM3 is connected with the input end of a gate driving circuit, and the gate driving circuit outputs a driving signal; the sources of the first NMOS tube NM0 and the second NMOS tube NM1 are connected with the common ground GND, and the gates respectively input the complementary signals; the output polarity of the gate driving circuit is opposite to the input polarity.
Further, the N-wells of the third PMOS tube PM2 and the fourth PMOS tube PM3 are connected with the source.
Further, the drains of the first PMOS tube PM0 and the second PMOS tube PM1 are respectively connected with the sources of the third PMOS tube PM2 and the fourth PMOS tube PM3; the first NMOS transistor NM0, the second NMOS transistor NM1, the third PMOS transistor PM2, and the fourth PMOS transistor PM3 are all high-voltage transistors, the rated withstand voltage of the drain electrode of the high-voltage transistor is higher than the voltage of the floating high-voltage power supply VB, and the rated withstand voltage of the drain electrode is greater than the rated withstand voltage of the gate electrode.
Further, the drains of the first PMOS tube PM0 and the second PMOS tube PM1 are respectively connected with the drains of the third PMOS tube PM2 and the fourth PMOS tube PM3; the first NMOS transistor NM0, the second NMOS transistor NM1, the first PMOS transistor PM0, the second PMOS transistor PM1, the third PMOS transistor PM2, and the fourth PMOS transistor PM3 are all high-voltage transistors, the rated withstand voltage of the drain electrode of the high-voltage transistor is higher than the voltage of the floating high-voltage power supply VB, and the rated withstand voltage of the drain electrode is greater than the rated withstand voltage of the gate electrode.
Further, the circuit further comprises a first diode D0 and a second diode D1, wherein the anodes of the first diode D0 and the second diode D1 are respectively connected with floating ground, and the cathodes of the first diode D0 and the second diode D1 are respectively connected with the grids of the second PMOS tube PM1 and the first PMOS tube PM 0.
Further, the floating resistor further comprises a resistor R0, one end of the resistor R0 is connected with the grid electrodes of the third PMOS tube PM2 and the fourth PMOS tube PM3, and the other end of the resistor R0 is connected with the floating ground.
Further, the input end of the grid driving circuit adopts a Schmitt trigger.
Further, the inverter group comprises a first inverter and a second inverter, the input end of the PWM control signal is connected with the input end of the first inverter, the output end of the first inverter is connected with the input end of the second inverter, and the output end signal of the first inverter and the output end signal of the second inverter form the complementary signal.
A high voltage floating gate driving chip integrates the high voltage floating gate driving circuit.
The utility model provides a high-voltage floating gate driving circuit and a driving chip thereof, which have the following beneficial effects compared with the prior art:
1. the circuit structure is simple. In the conventional high-voltage floating gate driving circuit, the high-voltage side driving requires a plurality of analog circuits requiring precise design, such as a narrow pulse generating circuit, a pulse filtering and RS trigger, a power-on default state setting circuit of the high-voltage side, and the like. The high-voltage floating gate driving circuit provided by the patent adopts digital static driving, has larger tolerance range for each device, omits a plurality of analog circuits such as a narrow pulse generating circuit, a pulse filtering and RS trigger, a power-on default state setting circuit at a high voltage side and the like, and has simpler overall circuit structure;
2. in the level shift circuit, A, B is a digital signal, so that the anti-interference capability is high and the robustness is higher;
3. in the traditional scheme, although a pulse filter circuit is arranged, the NM0 and the NM1 are in an off state most of the time, R0 and R1 are used for maintaining a pulse-free state, the high resistance value of the pulse filter circuit reduces the anti-interference capability, and an interference signal which is similar to the designed pulse width possibly causes the RS trigger to turn over, so that the final power tube is accidentally turned on or off, and the pulse filter circuit cannot be recovered until the next PWM pulse arrives; the static driving is adopted, the MOS device is used for realizing stronger cross driving, the anti-interference capability is strong, and even if interference pulses exist, the pulse can be recovered immediately after the pulse ends;
4. in the level shift circuit, four PMOS tubes are adopted, and compared with the traditional scheme in the background technology, two passive resistors are omitted, so that the process deviation is smaller, and the layout area is reduced.
Drawings
FIG. 1 is a schematic diagram of a high side structure of a prior art high voltage floating gate drive circuit;
fig. 2 is a schematic diagram of a high-voltage side structure of a high-voltage floating gate driving circuit according to the first embodiment;
fig. 3 is a schematic diagram of a high-voltage side structure of a high-voltage floating gate driving circuit according to a second embodiment;
fig. 4 is a schematic diagram of a high-voltage side structure of a high-voltage floating gate driving circuit according to a third embodiment.
Description of the embodiments
The utility model is further illustrated by the following description in conjunction with the accompanying drawings and specific embodiments.
Example 1
As shown in fig. 2, which is a schematic diagram of the high-side portion of the high-voltage floating gate driving circuit, the present patent content only relates to the high-side portion, and therefore only the portion related to the present patent content is shown in the figure, and other contents are omitted. The PWM control signal input end, the inverter group, the level shift circuit and the grid driving circuit are sequentially connected, wherein the inverter group is used for converting an input PWM control signal IN into a group of complementary signals INV0 and INV1, and the level shift circuit comprises a first NMOS tube NM0, a second NMOS tube NM1, a first PMOS tube PM0, a second PMOS tube PM1, a third PMOS tube PM2 and a fourth PMOS tube PM3; the sources of the first PMOS tube PM0 and the second PMOS tube PM1 are connected with a floating high-voltage power supply VB, the floating high-voltage power supply VB is at least 10V, the grid electrodes are respectively connected with the sources of the fourth PMOS tube PM3 and the third PMOS tube PM2, and the drain electrodes are respectively connected with the sources of the third PMOS tube PM2 and the fourth PMOS tube PM3; the gates of the third PMOS tube PM2 and the fourth PMOS tube PM3 are both connected to the floating ground VS, the drains are respectively connected to the drains of the first NMOS tube NM0 and the second NMOS tube NM1, the source of the fourth PMOS tube PM3 is connected to the input end of the gate driving circuit, or the source of the third PMOS tube PM2 is connected to the input end of the gate driving circuit, and for the same complementary signal input mode (for example, the INV0 input NM0 and the INV1 input NM1 shown in fig. 2), only the polarities are different; the gate driving circuit outputs a driving signal HO; the sources of the first NMOS tube NM0 and the second NMOS tube NM1 are connected with the common ground GND, and the gates respectively input the complementary signals INV0 and INV1.
The gate electrodes of the first PMOS tube PM0, the second PMOS tube PM1 and the input end of the gate driving circuit are connected to the source electrodes of the fourth PMOS tube PM3 and the third PMOS tube PM2, because the A, B point is clamped by the level, the gate voltage is not lower than VS, because the drain withstand voltage of the high voltage tube is far higher than the gate withstand voltage.
The first NMOS tube NM0, the second NMOS tube NM1, the third PMOS tube PM2 and the fourth PMOS tube PM3 are all high-voltage tubes, and the drain voltage withstand of the high-voltage tubes is not lower than VB. The high-voltage tube herein refers to a device having a drain rated withstand voltage greater than a gate rated withstand voltage. For example, VCC is 5V, VS is 20V when floating high, VB-VS is 5V, the high-voltage tube adopts an LDMOS device, the grid voltage withstand rating is 5V, the drain voltage withstand rating is not lower than VB, and the voltage withstand rating is 25V or higher. The first PMOS tube PM0 and the second PMOS tube PM1 only need to bear VB-VS voltage at the drain electrodes, and belong to common MOS devices, for example, the voltage withstanding of the grid electrode is equal to that of the drain electrode, and the rated voltage is 5V.
And the output polarity of the grid driving circuit is opposite to the input polarity, namely the final power tube corresponding to the high level of the point B is closed. This has the advantage that the power-on reset circuit can be omitted, the final power tube is ensured to be in a closed state during power-on, the point B is more prone to be high level during power-on, and after the phase inversion, HO is more prone to be low level, so that the power tube is closed. Therefore, it is preferable to select a gate driving circuit having an output polarity opposite to an input polarity. The input end of the grid driving circuit is preferably a schmitt trigger, and can also be driven by an inverter, so that the grid driving circuit has the function of providing enough driving capability and shaping function. The schmitt trigger is preferably adopted, so that the phenomenon of burrs and false overturning caused by abnormal jitter can be further prevented.
The inverter group comprises a first inverter and a second inverter, the input end of a PWM control signal is connected with the input end of the first inverter, the output end of the first inverter is connected with the input end of the second inverter, and the output end signals of the first inverter and the output end signals of the second inverter form complementary signals INV0 and INV1.
A high voltage floating gate driving chip integrates the high voltage floating gate driving circuit.
Working principle: the input signal IN is a PWM control signal, after shaping by an inverter group, the first NMOS tube NM0 and the second NMOS tube NM1 of the high-voltage tube are driven, as shown IN fig. 2, for example, when IN is at a high level, NM1 is turned on, NM0 is turned off, VS is a high-voltage floating ground, the drain terminal of the fourth PMOS tube PM3 is pulled to a low level GND by NM1, PM3 pulls the B point to about vs+vth (PM 3), the potential is at a logic low level relative to VB, so that the first PMOS tube PM0 is turned on, the potential of the a point is pulled to VB, and meanwhile, the potential of the a point closes the second PMOS tube PM1, further ensuring that the potential of the B point is at a low level, and subsequently ensuring that the HO output is at a high level VB or a low level VS (HO and IN-phase or reverse phase can be set according to requirements) by setting a suitable turning point at the input end of the gate driving circuit.
Example two
In the second embodiment, on the basis of the first embodiment, a first diode D0 and a second diode D1 of a reverse bias diode are further added, as shown in fig. 3, anodes of the first diode D0 and the second diode D1 are connected with a floating ground VS, and cathodes of the first diode D0 and the second diode D1 are respectively connected with gates of a second PMOS tube PM1 and a first PMOS tube PM 0. The reverse bias diodes D0 and D1 have the function of enhancing the protection of the gate ends of the second PMOS tube PM1 and the first PMOS tube PM0, and can be reserved according to the needs.
On the basis, a resistor R0 can be added, one end of the resistor R0 is connected with the grid electrodes of the third PMOS tube PM2 and the fourth PMOS tube PM3, and the other end of the resistor R0 is connected with the floating ground VS. The resistor R0 plays a role in protecting the grid end of the PMOS tube by the secondary ESD, and can be reserved according to the requirement.
Preferably, the N-wells of the third PMOS tube PM2 and the fourth PMOS tube PM3 are connected to their sources, i.e. the connection of the N-wells of the PMOS tubes in fig. 3. The N-well may be connected to the floating high voltage power supply VB, but the threshold voltages of the third PMOS transistor and the fourth PMOS transistor are increased, and a larger voltage margin is required, so that the connection mode of the N-well to the source is preferable.
Example III
Compared with the first embodiment, the third embodiment is different in connection manner between the first PMOS pipe PM0 and the second PMOS pipe PM1 and the third PMOS pipe PM2 and the fourth PMOS pipe PM 3. As shown in fig. 4, in the present embodiment, the drain electrode of the first PMOS tube PM0 is not connected to the source electrode of the third PMOS tube PM2, but is a drain electrode; the drain electrode of the second PMOS tube PM1 is also connected with the drain electrode of the fourth PMOS tube PM 3.
The advantage of this connection is that the pipe sizes of the third PMOS pipe PM2 and the fourth PMOS pipe PM3 can be reduced, thereby saving more area than the circuit structure of the first embodiment. Because the third PMOS tube PM2 and the fourth PMOS tube PM3 in the first embodiment require a strong driving capability to pull the potential of the point a or B low, the PMOS tubes are required to have a large size. In this embodiment, the sources of the third PMOS tube PM2 and the fourth PMOS tube PM3 are connected to the gates of the first PMOS tube PM0 and the second PMOS tube PM1, but not to the drains of the first PMOS tube PM0 and the second PMOS tube PM1, so that there is no direct current path. When the potential at the point C or the point D is pulled down by the complementary signal, the potential at the point A or the point B is pulled up to VS+VTH (PM 3) by the third PMOS tube PM2 and the fourth PMOS tube PM 3.
In this embodiment, the first NMOS transistor NM0, the second NMOS transistor NM1, the first PMOS transistor PM0, the second PMOS transistor PM1, the third PMOS transistor PM2, and the fourth PMOS transistor PM3 are all high-voltage transistors, the drain withstand voltage of the high-voltage transistors is higher than the floating high-voltage power supply VB, and the drain rated withstand voltage is greater than the gate rated withstand voltage. For example, when VS floats to be at a high level, it is 100V, VB-VS is 15V, and the high-voltage tube adopts a DMOS device, the voltage withstand rating of the gate is not lower than 15V, the voltage withstand rating of the drain is not lower than VB, and the voltage withstand rating of the drain is 115V or higher.
On the basis of the third embodiment, the resistor R0 as described in the second embodiment can be added to play a role in protecting the grid end of the PMOS tube by the secondary ESD.
Claims (9)
1. The high-voltage floating gate driving circuit is characterized by comprising a PWM control signal input end, an inverter group, a level shift circuit and a gate driving circuit which are connected in sequence, wherein the inverter group is used for converting an input PWM control signal into a group of complementary signals, and the level shift circuit comprises a first NMOS tube NM0, a second NMOS tube NM1, a first PMOS tube PM0, a second PMOS tube PM1, a third PMOS tube PM2 and a fourth PMOS tube PM3; the sources of the first PMOS tube PM0 and the second PMOS tube PM1 are connected with a floating high-voltage power supply VB, the floating high-voltage power supply VB is at least 10V, the grid electrodes are respectively connected with the sources of the fourth PMOS tube PM3 and the third PMOS tube PM2, and the drain electrodes are respectively connected with the sources or the drain electrodes of the third PMOS tube PM2 and the fourth PMOS tube PM3; the gates of the third PMOS tube PM2 and the fourth PMOS tube PM3 are connected with a floating ground VS, the drains of the third PMOS tube PM2 and the fourth PMOS tube PM3 are respectively connected with the drains of the first NMOS tube NM0 and the second NMOS tube NM1, the source of the third PMOS tube PM2 or the fourth PMOS tube PM3 is connected with the input end of a gate driving circuit, and the gate driving circuit outputs a driving signal; the sources of the first NMOS tube NM0 and the second NMOS tube NM1 are connected with the common ground GND, and the gates respectively input the complementary signals; the output polarity of the gate driving circuit is opposite to the input polarity.
2. The high voltage floating gate driving circuit according to claim 1, wherein the N-wells of the third PMOS transistor PM2 and the fourth PMOS transistor PM3 are connected to the source.
3. The high-voltage floating gate driving circuit according to claim 1 or 2, wherein the drains of the first PMOS tube PM0 and the second PMOS tube PM1 are respectively connected to the sources of the third PMOS tube PM2 and the fourth PMOS tube PM3; the first NMOS transistor NM0, the second NMOS transistor NM1, the third PMOS transistor PM2, and the fourth PMOS transistor PM3 are all high-voltage transistors, the rated withstand voltage of the drain electrode of the high-voltage transistor is higher than the voltage of the floating high-voltage power supply VB, and the rated withstand voltage of the drain electrode is greater than the rated withstand voltage of the gate electrode.
4. The high-voltage floating gate driving circuit according to claim 1 or 2, wherein the drains of the first PMOS tube PM0 and the second PMOS tube PM1 are respectively connected to the drains of the third PMOS tube PM2 and the fourth PMOS tube PM3; the first NMOS transistor NM0, the second NMOS transistor NM1, the first PMOS transistor PM0, the second PMOS transistor PM1, the third PMOS transistor PM2, and the fourth PMOS transistor PM3 are all high-voltage transistors, the rated withstand voltage of the drain electrode of the high-voltage transistor is higher than the voltage of the floating high-voltage power supply VB, and the rated withstand voltage of the drain electrode is greater than the rated withstand voltage of the gate electrode.
5. The high-voltage floating gate driving circuit according to claim 1 or 2, further comprising a first diode D0 and a second diode D1, wherein anodes of the first diode D0 and the second diode D1 are respectively connected to a floating ground, and cathodes of the first diode D0 and the second diode D1 are respectively connected to gates of the second PMOS tube PM1 and the first PMOS tube PM 0.
6. The high voltage floating gate driving circuit of claim 5, further comprising a resistor R0, wherein one end of the resistor R0 is connected to the gates of the third PMOS tube PM2 and the fourth PMOS tube PM3, and the other end is connected to the floating ground.
7. The high voltage floating gate drive circuit of claim 1 or 2, wherein the input of the gate drive circuit employs a schmitt trigger.
8. The high voltage floating gate driving circuit according to claim 1 or 2, wherein the inverter group comprises a first inverter and a second inverter, the PWM control signal input terminal is connected to the first inverter input terminal, the first inverter output terminal is connected to the second inverter input terminal, and the output terminal signal of the first inverter and the output terminal signal of the second inverter constitute the complementary signal.
9. A high voltage floating gate drive chip characterized by integrating a high voltage floating gate drive circuit according to any one of claims 1-8.
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| Application Number | Priority Date | Filing Date | Title |
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| CN202310050941.5A CN116131828A (en) | 2023-02-02 | 2023-02-02 | High-voltage floating gate driving circuit and driving chip thereof |
| CN2023100509415 | 2023-02-02 |
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| CN219611748U true CN219611748U (en) | 2023-08-29 |
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| CN202321370890.6U Active CN219611748U (en) | 2023-02-02 | 2023-06-01 | High-voltage floating gate driving circuit and driving chip thereof |
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2023
- 2023-02-02 CN CN202310050941.5A patent/CN116131828A/en not_active Withdrawn
- 2023-06-01 CN CN202321370890.6U patent/CN219611748U/en active Active
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|---|---|
| CN116131828A (en) | 2023-05-16 |
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