CN107786190B - Low-on-resistance flatness analog switch with leakage current elimination technology - Google Patents
Low-on-resistance flatness analog switch with leakage current elimination technology Download PDFInfo
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- CN107786190B CN107786190B CN201711108482.2A CN201711108482A CN107786190B CN 107786190 B CN107786190 B CN 107786190B CN 201711108482 A CN201711108482 A CN 201711108482A CN 107786190 B CN107786190 B CN 107786190B
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
- H03K17/16—Modifications for eliminating interference voltages or currents
- H03K17/161—Modifications for eliminating interference voltages or currents in field-effect transistor switches
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
- H03K17/51—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used
- H03K17/56—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices
- H03K17/687—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices the devices being field-effect transistors
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Abstract
The invention relates to a low-on-resistance flatness analog switch with a leakage current elimination technology, and belongs to the technical field of semiconductors. The method comprises the following steps: a first PMOS transistor, a first NMOS transistor; the source electrode and the drain electrode of the first PMOS transistor are respectively connected with the source electrode and the drain electrode of the first NMOS transistor and are used as the input end and the output end of the analog switch, and the grid electrodes of the first PMOS transistor and the first NMOS transistor are connected with control signals; the grid control circuit I can be composed of a third PMOS transistor and a third NMOS transistor, and the grid control circuit II can be composed of a fourth PMOS transistor and a fourth NMOS transistor. According to the invention, the grid end control circuit is added on the basis of the traditional design of the flatness of the on-resistance of the analog switch, so that the flatness of the on-resistance of the analog switch is optimized to a certain extent, and the transient leakage current generated at the output port at the switching moment of the analog switch is eliminated.
Description
Technical Field
The invention belongs to the technical field of semiconductors, and relates to a low-on-resistance flatness analog switch with a leakage current elimination technology.
Background
CMOS [ Complementary Metal Oxide Semiconductor in the prior art; complementary metal oxide semiconductor as shown in fig. 1, the analog switch is composed of two parts, a P-channel type MOS field effect transistor P1 and an N-channel type MOS field effect transistor N1. Normally, the potentials of the gates 2 and 3 of the P1 and N1 transistors are inverse signals, and the high and low of the gates 2 and 3 determine the on and off of the switch.
The structure adopts a single well process, namely, the NMOS transistor substrate 5 is Psub and is always connected with the lowest potential VSS; the PMOS transistor substrate 4 is an N-well, floating, and typically has two connections, either to the highest potential VDD or to the source terminal 6. If the transistor substrate 4 is connected with the source terminal 6, as shown in fig. 3, when the switch is turned off, the voltage of the source terminal 1 is higher than that of the source terminal 6 due to uncertain voltage of the source terminals 1 and 6, so that the diodes from the source terminal 1 to the source terminal 6 form a path, and the switch cannot be turned off; if the transistor substrate 4 is connected to VDD as shown in fig. 2, when the voltages at terminals 1 and 6 are changed from VSS to VDD, the threshold voltage Vth of the PMOS transistor is increased by the substrate bias effect, and the flatness of the on-resistance is deteriorated.
Disclosure of Invention
In view of the above, an object of the present invention is to provide a low on-resistance flatness analog switch with leakage current cancellation, which optimizes the on-resistance flatness of the analog switch to a certain extent through a reasonable design; and the leakage current of the analog switch flowing to the output port at the switching moment is eliminated through the leakage elimination technology.
In order to achieve the purpose, the invention provides the following technical scheme:
a low-on-resistance flatness analog switch with a leakage current elimination technology comprises a first PMOS transistor, a first NMOS transistor, a substrate control transistor and a grid control circuit;
the source electrode and the drain electrode of the first PMOS transistor are respectively connected with the source electrode and the drain electrode of the first NMOS transistor and are used as the input end and the output end of the analog switch, and the grid electrodes of the first PMOS transistor and the first NMOS transistor are connected with control signals;
the substrate control transistor comprises a second PMOS transistor and a second NMOS transistor, the drains of the second PMOS transistor and the second NMOS transistor are connected with each other, the source electrode of the second PMOS transistor is connected with a high level, and the source electrode of the second NMOS transistor is connected with the source electrode of the first PMOS transistor;
the substrate of the first PMOS transistor is connected to the drain of the second PMOS transistor;
the grid control circuit comprises a grid control circuit I and a grid control circuit II, one end of the grid control circuit I and one end of the grid control circuit II are respectively connected to the grids of the second PMOS transistor and the second NMOS transistor, and the grid control circuit is used for controlling the substrate control transistors to be turned on or turned off at the same time.
Further, the gate control circuit I comprises a third PMOS transistor and a third NMOS transistor, the drains of the third PMOS transistor and the third NMOS transistor are connected with each other, the source of the third PMOS transistor is connected with a high level, and the source of the third NMOS transistor is connected with the source of the first PMOS transistor;
the grid control circuit II comprises a fourth PMOS transistor and a fourth NMOS transistor, the drains of the fourth PMOS transistor and the fourth NMOS transistor are mutually connected, the source electrode of the fourth PMOS transistor is connected with a high level, and the source electrode of the fourth NMOS transistor is connected with the source electrode of the first PMOS transistor;
the gate of the second NMOS transistor is connected to the drain of the third NMOS transistor, and the gate of the second PMOS transistor is connected to the drain of the fourth NMOS transistor.
Further, the gates of the third PMOS transistor, the third NMOS transistor, the fourth PMOS transistor, and the fourth NMOS transistor are connected to each other and then connected to the gate of the first PMOS transistor.
Further, the gates of the third PMOS transistor, the third NMOS transistor, the fourth PMOS transistor, and the fourth NMOS transistor are connected to each other and then connected to the gate of the first NMOS transistor.
The invention has the beneficial effects that: the invention provides a method for optimizing the flatness of an on-resistance with a switch leakage current elimination technology, which optimizes the flatness of the on-resistance of an analog switch to a certain extent by reasonably designing the potential of a PMOS transistor substrate 4; and the leakage current of the analog switch flowing to the output port at the switching moment is eliminated through the leakage elimination technology.
Drawings
In order to make the object, technical scheme and beneficial effect of the invention more clear, the invention provides the following drawings for explanation:
FIG. 1 is a schematic diagram of a complementary analog switch;
FIG. 2 is a circuit diagram of an analog switch with the substrate of the PMOS switch tube connected to the highest potential;
FIG. 3 is a circuit diagram of an analog switch with the substrate end and the source end of a PMOS switch tube connected together;
FIG. 4 is a circuit diagram of an analog switch for optimizing the flatness of the on-resistance of the present embodiment;
FIG. 5 is a circuit diagram of a low on-resistance planarization analog switch with switch leakage current cancellation technique according to the present embodiment;
FIG. 6 is a diagram illustrating an implementation of a gate control circuit according to an embodiment of the present invention;
FIG. 7 is a schematic diagram of port logic relationship signals of the analog switch of the present invention.
Detailed Description
Preferred embodiments of the present invention will be described in detail below with reference to the accompanying drawings.
Fig. 1 is a schematic diagram of a complementary analog switch structure. The analog switch adopts P, N type double MOS transistor complementary switch, and comprises a first PMOS transistor P1 and a first NMOS transistor N1. The gate end 2 of P1 and the gate end 3 of N1 are used as gate control ports to be opposite signals with each other, and control the on and off of the switch; the source end of P1 is connected with the source end of N1 to be used as the input end 1 of the switch; the P1 drain is connected to the N1 drain as the switch input 6.
By utilizing the P, N type complementary double MOS transistor butt joint mode, the low on-resistance which is basically constant can be ensured in the dynamic range of analog signals.
FIG. 2 is a circuit diagram of an analog switch with the substrate of the PMOS switch tube connected to the highest potential. The invention adopts a single-well process, a substrate 5 of a first NMOS transistor N1 is Psub and is connected with a lowest potential VSS; the first PMOS transistor P1 has a substrate 4 of Nwell, floating potential, and in this diagram, the substrate 4 of P1 is connected to the highest potential VDD. In this connection, when the voltages at terminals 1 and 6 are changed from VSS to VDD, the threshold voltage Vth of the PMOS transistor increases due to the substrate bias effect, and the flatness of the on-resistance deteriorates.
Fig. 3 is a circuit diagram of an analog switch with a PMOS switch transistor substrate termination source. The first PMOS transistor P1 has Nwell as substrate 4 and floating potential, which is different from fig. 2 in that the source terminal of the transistor is connected to P1 as substrate 4 in the diagram. The disadvantage of this connection is that when the switch is turned off, the voltage at the 1-terminal is higher than that at the 6-terminal because the voltages at the 1-terminal and the 6-terminal are uncertain, so that the 1-terminal to 6-terminal diodes form a path and the switch cannot be turned off.
Fig. 4 is a circuit diagram of an analog switch with optimized on-resistance flatness. In order to optimize the resistance flatness of the analog switch, a substrate control circuit consisting of a second NMOS transistor N2 and a second PMOS transistor P2 is added to the switch circuit. The grids of N2 and P2 are connected with the grid end 3 of a switch transistor N1, the source end of N2 is connected with the input end 1 of the switch, the source end of P2 is connected with the highest potential VDD, and the drain ends of N2 and P2 are connected as the output of a substrate control circuit to control the substrate 4 of the switch transistor P1.
The resistance flatness optimization mode is as follows: when the switch is turned on, the potential 3 of the gate terminal of N1 is high, and the potential 2 of the gate terminal of P1 is low. In the substrate control circuit composed of N2 and P2, the N2 transistor is turned on, and the P2 transistor is turned off, so that the potential of the P1 substrate 4 is equal to the potential of the switch input end 1, the P1 substrate bias effect is eliminated, and the resistance flatness is optimized. When the switch is turned off, the potential 3 of the gate terminal of N1 is at low level, and the potential 2 of the gate terminal of P1 is at high level. In a substrate control circuit consisting of N2 and P2, an N2 transistor is turned off, a P2 transistor is turned on, so that the potential of a substrate 4 of a switch transistor P1 is equal to the potential of a source end 7 of P2, namely the highest potential VDD, PN junctions in the switch tube are reversely biased at the moment, and the leakage current is minimum.
The disadvantage of the resistor flatness optimization method shown in fig. 4 is that: transient current generated at the output terminal of the substrate control circuit composed of the switching moments N2 and P2 when the switch is turned on and off flows to the substrate of the switching transistor P1 directly. This transient current flows through the substrate to the switch output port 6 where it can be detected and affect the subsequent circuitry.
FIG. 5 is a circuit diagram of a low on-resistance planarization analog switch with switch leakage current cancellation. In order to eliminate the leakage current introduced into the switch output terminal at the switching moment, a grid control circuit 1 and a grid control circuit 2 are added at a grid terminal 8 of an N2 transistor and a grid terminal 9 of a P2 transistor relative to the circuit structure of the circuit shown in the figure 4. The input ports of the gate control circuit 1 and the gate control circuit 2 are connected with the gate terminal 3 of the switching transistor N1, the output port of the gate control circuit 1 is connected with the gate terminal N2, and the output port of the gate control circuit 2 is connected with the gate terminal P2. Under the action of the gate control circuit 1 and the gate control circuit 2, when the switch is switched, a certain dead time is generated between gate signals of N2 and P2, so that one transistor of N2 and P2 is turned off and then the other transistor is turned on, common-state conduction of N2 and P2 at the switching moment of the switch is avoided, and transient current generated at a drain terminal flows to the output port 6 through the P1 substrate 4.
Fig. 6 is an example of an implementation of the gate control circuit. The gate control circuit 1 is implemented by an inverter formed by a third NMOS transistor N3 and a third PMOS transistor P3, and the gate control circuit 2 is implemented by an inverter formed by a fourth NMOS transistor N4 and a fourth PMOS transistor P4. Since the gate terminal 3 control signal of the switch transistor N1 is inverted with respect to the gate terminal 2 control signal of the switch transistor P1, the gate control circuit input is connected to the gate terminal 2 of the switch transistor P1 for proper logic function.
When the switch is switched from off to on, the gate end 2 of the switch transistor P1 is switched from high level to low level, the size of the P4 transistor is far larger than that of the N4, the size of the P3 transistor is far smaller than that of the N3, so that the gate end 9 of P2 reaches high level firstly, the gate end 8 of N2 reaches high level later, the purposes of turning off the P2 firstly and turning on the N2 secondly are achieved, and the transient leakage current of the switch in the turning-on process is avoided. When the switch is switched from on to off, the gate end 2 of the switch transistor P1 is switched from low level to high level, and due to the fact that the size of the P4 transistor is far larger than that of the N4 and the size of the P3 transistor is far smaller than that of the N3, the gate end 8 of the P2 reaches low level first, the gate end 9 of the N2 reaches low level later, the purposes that the N2 is turned off first and the P2 is turned on again are achieved, and therefore transient leakage current in the switching-off process of the switch is avoided.
The gate control circuit shown in fig. 6 is merely an example, and various modifications can be made without departing from the scope of the present invention.
Fig. 7 is a schematic diagram showing the logical relationship signals of the ports of the analog switch of the present invention. The gate terminal 3 of the switching transistor N1 and the gate terminal 2 of the switching transistor P1 are opposite signals. The signal between the gate terminal 8 of the N2 transistor and the gate terminal 9 of the P2 transistor presents a certain dead time under the action of the gate control circuit 1 and the gate control circuit 2, namely, the gate terminal 8 of the N2 transistor reaches a high level after being compared with the gate terminal 9 of the P2 transistor; the gate terminal 8 of the N2 transistor goes low earlier than the gate terminal 9 of the P2 transistor. The creation of this dead time eliminates the generation of transient leakage current at the switching instant.
According to the invention, the grid end control circuit is added on the basis of the traditional design of the flatness of the on-resistance of the analog switch, so that the flatness of the on-resistance of the analog switch is optimized to a certain extent, and the transient leakage current generated at the switching moment of the analog switch is eliminated.
Finally, it is noted that the above-mentioned preferred embodiments illustrate rather than limit the invention, and that, although the invention has been described in detail with reference to the above-mentioned preferred embodiments, it will be understood by those skilled in the art that various changes in form and detail may be made therein without departing from the scope of the invention as defined by the appended claims.
Claims (3)
1. The utility model provides a take low on-resistance flatness analog switch of leakage current elimination technique which characterized in that: a first PMOS transistor, a first NMOS transistor, a substrate control transistor and a gate control circuit;
the source electrode and the drain electrode of the first PMOS transistor are respectively connected with the source electrode and the drain electrode of the first NMOS transistor and are used as the input end and the output end of the analog switch, and the grid electrodes of the first PMOS transistor and the first NMOS transistor are connected with control signals;
the substrate control transistor comprises a second PMOS transistor and a second NMOS transistor, the drains of the second PMOS transistor and the second NMOS transistor are connected with each other, the source electrode of the second PMOS transistor is connected with a high level, and the source electrode of the second NMOS transistor is connected with the source electrode of the first PMOS transistor;
the substrate of the first PMOS transistor is connected to the drain of the second PMOS transistor;
the grid control circuit comprises a grid control circuit I and a grid control circuit II, one end of the grid control circuit I and one end of the grid control circuit II are respectively connected to the grids of the second PMOS transistor and the second NMOS transistor, and the grid control circuit is used for controlling the substrate control transistors to be turned on or turned off at the same time;
the grid control circuit I comprises a third PMOS transistor and a third NMOS transistor, the drains of the third PMOS transistor and the third NMOS transistor are connected with each other, the source electrode of the third PMOS transistor is connected with a high level, and the source electrode of the third NMOS transistor is connected with the source electrode of the first PMOS transistor;
the grid control circuit II comprises a fourth PMOS transistor and a fourth NMOS transistor, the drains of the fourth PMOS transistor and the fourth NMOS transistor are mutually connected, the source electrode of the fourth PMOS transistor is connected with a high level, and the source electrode of the fourth NMOS transistor is connected with the source electrode of the first PMOS transistor;
the grid electrode of the second NMOS transistor is connected to the drain electrode of the third NMOS transistor, and the grid electrode of the second PMOS transistor is connected to the drain electrode of the fourth NMOS transistor;
the size of the fourth PMOS transistor is larger than that of the fourth NMOS transistor, and the size of the third PMOS transistor is smaller than that of the third NMOS transistor.
2. The low on-resistance flatness analog switch with leakage current cancellation technique of claim 1, wherein: and the grid electrodes of the third PMOS transistor, the third NMOS transistor, the fourth PMOS transistor and the fourth NMOS transistor are connected with each other and then are connected to the grid electrode of the first PMOS transistor.
3. The low on-resistance flatness analog switch with leakage current cancellation technique of claim 1, wherein: and the grids of the third PMOS transistor, the third NMOS transistor, the fourth PMOS transistor and the fourth NMOS transistor are connected with each other and then are connected to the grid of the first NMOS transistor.
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| CN201711108482.2A CN107786190B (en) | 2017-11-09 | 2017-11-09 | Low-on-resistance flatness analog switch with leakage current elimination technology |
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| CN201711108482.2A CN107786190B (en) | 2017-11-09 | 2017-11-09 | Low-on-resistance flatness analog switch with leakage current elimination technology |
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| CN107786190B true CN107786190B (en) | 2021-05-28 |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| WO2020155015A1 (en) * | 2019-01-31 | 2020-08-06 | 华为技术有限公司 | Cmos transistor, circuit for driving liquid crystal pixels, and cmos transmission gate |
| CN109787603B (en) * | 2019-03-05 | 2023-05-16 | 上海艾为电子技术股份有限公司 | Low-conduction flatness analog switch |
| CN112557935B (en) * | 2020-12-11 | 2024-06-14 | 重庆西南集成电路设计有限责任公司 | High-precision battery string single cell voltage detection system based on voltage moving |
| CN114050821B (en) * | 2021-11-16 | 2022-07-19 | 无锡力芯微电子股份有限公司 | Output circuit with function of inhibiting reverse electric leakage of port |
| CN114301458A (en) * | 2021-12-30 | 2022-04-08 | 合肥市芯海电子科技有限公司 | Switch circuit, multichannel sampling control circuit, analog-to-digital conversion circuit and chip |
| CN115085713B (en) * | 2022-07-28 | 2023-10-24 | 无锡众享科技有限公司 | Analog switch circuit |
| CN117811584B (en) * | 2024-02-29 | 2024-08-30 | 成都电科星拓科技有限公司 | Digital-to-analog converter |
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| US7760007B2 (en) * | 2008-12-11 | 2010-07-20 | Nuvoton Technology Corporation | Low voltage analog CMOS switch |
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| US5332916A (en) * | 1991-09-30 | 1994-07-26 | Rohm Co., Ltd. | Transmission gate |
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