CN107786190A - A kind of low on-resistance flatness analog switch with leakage current technology for eliminating - Google Patents
A kind of low on-resistance flatness analog switch with leakage current technology for eliminating Download PDFInfo
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- CN107786190A CN107786190A CN201711108482.2A CN201711108482A CN107786190A CN 107786190 A CN107786190 A CN 107786190A CN 201711108482 A CN201711108482 A CN 201711108482A CN 107786190 A CN107786190 A CN 107786190A
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- transistor
- grid
- nmos pass
- pmos transistor
- control circuit
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Classifications
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
- H03K17/16—Modifications for eliminating interference voltages or currents
- H03K17/161—Modifications for eliminating interference voltages or currents in field-effect transistor switches
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
- H03K17/51—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used
- H03K17/56—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices
- H03K17/687—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices the devices being field-effect transistors
Abstract
The present invention relates to a kind of low on-resistance flatness analog switch with leakage current technology for eliminating, belong to technical field of semiconductors.Including：First PMOS transistor, the first nmos pass transistor；The source electrode of first PMOS transistor and drain electrode are connected with the source electrode of the first nmos pass transistor and drain electrode respectively, and as the input and output end of analog switch, the grid connection control signal of the first PMOS transistor and the first nmos pass transistor；Also include substrate controlling transistor, grid control circuit I and grid control circuit II, grid control circuit I can be made up of the 3rd PMOS transistor, the 3rd nmos pass transistor, and grid control circuit II can be made up of the 4th PMOS transistor, the 4th nmos pass transistor.By increasing grid end control circuit in traditional analog switch conduction resistance flatness design basis in the present invention, while so that analog switch conducting resistance flatness is necessarily optimized, analog switch switching moment is also eliminated in transient state leakage current caused by output port.
Description
Technical field
The invention belongs to technical field of semiconductors, is related to a kind of low on-resistance flatness mould with leakage current technology for eliminating
Intend switch.
Background technology
CMOS [Complementary Metal Oxide Semiconductor in the prior art；CMOS
Semiconductor] as shown in figure 1, analog switch is made up of two parts, P-channel type MOS field-effect transistors P1 and N-channel type MOS fields
Effect transistor N1.Under normal circumstances, the current potential of P1, N1 transistor gate 2 and 3 is inversion signal, and the height of grid 2 and 3 determines
Switch on and turn off.
The structure uses single trap technique, i.e. nmos pass transistor substrate 5 is Psub, meets potential minimum VSS all the time；PMOS is brilliant
Body tube lining bottom 4 is N traps, is to float, generally has two kinds of connections, meet maximum potential VDD or connect source 6.If by transistor substrate 4
Source 6 is connect, such as Fig. 3, then in switch OFF because 1,6 terminal voltages are not known, 1 terminal voltage may be caused to be higher than 6 terminal voltages, made
Obtain 1 end and form paths to 6 end diodes, switch can not turn off；If transistor substrate 4 is connect into VDD, such as Fig. 2, then 1 end and 6 ends are electric
Pressure from VSS change to VDD when, PMOS transistor threshold voltage vt h can increase due to substrate bias effect, conducting resistance flatness
It is deteriorated.
The content of the invention
In view of this, it is an object of the invention to provide a kind of low on-resistance flatness mould with leakage current technology for eliminating
Intend switch, necessarily optimized by rationally designing analog switch conducting resistance flatness；And by the technology for eliminating that leaks electricity,
Eliminate the leakage current that analog switch flows to output port in switching moment.
To reach above-mentioned purpose, the present invention provides following technical scheme：
A kind of low on-resistance flatness analog switch with leakage current technology for eliminating, the first PMOS transistor, first
Nmos pass transistor, substrate controlling transistor and grid control circuit；
The source electrode of first PMOS transistor and the source electrode and drain electrode phase with first nmos pass transistor respectively that drain
Connection, and as the input and output end of analog switch, the grid of first PMOS transistor and the first nmos pass transistor
Connection control signal；
The substrate controlling transistor includes the second PMOS transistor and the second nmos pass transistor, the 2nd PMOS crystal
The drain electrode of pipe and the second nmos pass transistor is connected with each other, and the source electrode of second PMOS transistor connects high level, and described second
The source electrode of nmos pass transistor is connected with the source electrode of first PMOS transistor；
The substrate of first PMOS transistor is connected to the drain electrode of second PMOS transistor；
The grid control circuit includes grid control circuit I and grid control circuit II, the He of grid control circuit I
One end of grid control circuit II is respectively connecting to the grid of second PMOS transistor and the second nmos pass transistor, the grid
Pole control circuit is used to control the substrate controlling transistor is non-concurrent to be switched on or off.
Further, the grid control circuit I includes the 3rd PMOS transistor and the 3rd nmos pass transistor, and the described 3rd
The drain electrode of PMOS transistor and the 3rd nmos pass transistor is connected with each other, and the source electrode of the 3rd PMOS transistor connects high level, institute
The source electrode for stating the 3rd nmos pass transistor is connected with the source electrode of first PMOS transistor；
Grid control circuit II includes the 4th PMOS transistor and the 4th nmos pass transistor, the 4th PMOS transistor and
The drain electrode of 4th nmos pass transistor is connected with each other, and the source electrode of the 4th PMOS transistor connects high level, and the 4th NMOS is brilliant
The source electrode of body pipe is connected with the source electrode of first PMOS transistor；
The grid of second nmos pass transistor is connected to the drain electrode of the 3rd nmos pass transistor, and the 2nd PMOS is brilliant
The grid of body pipe is connected to the drain electrode of the 4th nmos pass transistor.
Further, the 3rd PMOS transistor, the 3rd nmos pass transistor, the 4th PMOS transistor and the 4th NMOS crystal
The grid of pipe is connected to the grid of first PMOS transistor after being connected with each other.
Further, the 3rd PMOS transistor, the 3rd nmos pass transistor, the 4th PMOS transistor and the 4th NMOS crystal
The grid of pipe is connected to the grid of first nmos pass transistor after being connected with each other.
The beneficial effects of the present invention are：It is flat that the present invention provides a kind of conducting resistance of belt switch leakage current technology for eliminating
Optimization method is spent, is obtained by the rational design analog switch conducting resistance flatness of the current potential of pair pmos transistor substrate 4
Certain optimization；And by the technology for eliminating that leaks electricity, eliminate the leakage current that analog switch flows to output port in switching moment.
Brief description of the drawings
In order that the purpose of the present invention, technical scheme and beneficial effect are clearer, the present invention provides drawings described below and carried out
Explanation：
Fig. 1 is complementary type analog switch structural representation；
Fig. 2 is the analog switching circuit figure that PMOS switch tube lining bottom connects maximum potential；
Fig. 3 is the analog switching circuit figure that PMOS switch tube lining bottom connects with source；
Fig. 4 is the analog switching circuit figure of the present embodiment conducting resistance flatness optimization；
Fig. 5 is the low on-resistance flatness analog switching circuit figure of the present embodiment belt switch leakage current technology for eliminating；
Fig. 6 is a kind of implementation of the present embodiment grid control circuit；
Fig. 7 is the port logic bearing signal schematic diagram of analog switch of the present invention.
Embodiment
Below in conjunction with accompanying drawing, the preferred embodiments of the present invention are described in detail.
Fig. 1 is complementary type analog switch structural representation.Analog switch is using P, the double MOS transistor complementary switch of N-type, bag
Containing the first PMOS transistor P1 and the first nmos pass transistor N1.P1 grid ends 2 and N1 grid ends 3 are reverse each other as grid control port
Signal, controlling switch are switched on and off；P1 sources connect as switch input terminal 1 with N1 sources；P1 drain terminals and N1 drain terminal phases
Connect as switch input terminal 6.
Using P, the complementary double MOS transistor docking modes of N-type, substantially constant can be ensured in analog signal dynamic range
Low on-resistance.
Fig. 2 is the analog switching circuit figure that PMOS switch tube lining bottom connects maximum potential.The present invention uses single trap technique, the
One nmos pass transistor N1 substrates 5 are Psub, meet potential minimum VSS；First PMOS transistor P1 substrates 4 are Nwell, for the electricity that floats
, in the schematic diagram, P1 substrates 4 meet maximum potential VDD.Under the connected mode, 1 end and 6 terminal voltages from VSS change to VDD when,
PMOS transistor threshold voltage vt h can increase due to substrate bias effect, and conducting resistance flatness is deteriorated.
Fig. 3 is the analog switching circuit figure that PMOS switch tube lining bottom connects source.First PMOS transistor P1 substrates 4 are
Nwell, it is floating potential, is with Fig. 2 differences, in the schematic diagram, P1 substrates 4 connects the transistor source.The connection side
The drawbacks of formula, is, in switch OFF because 1,6 terminal voltages are not known, 1 terminal voltage may be caused to be higher than 6 terminal voltages so that 1 end
Path is formed to 6 end diodes, switch can not turn off.
Fig. 4 is the analog switching circuit figure of conducting resistance flatness optimization.In order to Optimized Simulated switch resistance flatness,
Increase the substrate control circuit of the second nmos pass transistor N2 and the second PMOS transistor P2 compositions in on-off circuit.N2, P2 grid
It is connected and connects with switching transistor N1 grid ends 3, N2 sources connects switch input terminal 1, and P2 sources connect maximum potential VDD, N2, P2 drain terminal
Connect and exported as substrate control circuit, controlling switch transistor P1 substrates 4.
Resistance flatness optimal way is：When the switch is opened, N1 grid ends current potential 3 is high level, and P1 grid ends current potential 2 is low
Level.N2 transistors are opened in the substrate control circuit of N2, P2 composition, P2 transistors shut-off so that switching transistor P1 substrates 4
Current potential is equal with the current potential of switch input terminal 1, and switching tube P1 body bias effects eliminate, and resistance flatness is optimised.Work as switch OFF
When, N1 grid ends current potential 3 is low level, and P1 grid ends current potential 2 is high level.N2 transistors in the substrate control circuit of N2, P2 composition
Shut-off, P2 transistors are opened so that and the current potential of switching transistor P1 substrates 4 is equal with the current potential of P2 sources 7, as maximum potential VDD,
Now PN junction is reverse-biased inside switching tube, and leakage current is minimum.
The drawbacks of optimal way of resistance flatness shown in Fig. 4 is brought be：Switch is opened, shut-off switching moment N2, P2 composition
Substrate control circuit output end caused by transient current flow directly into switching transistor P1 substrate.The transient current passes through lining
To output switching terminal mouth 6, the transient current can detect in output port and influence late-class circuit for underflow.
Fig. 5 is the low on-resistance flatness analog switching circuit figure of belt switch leakage current technology for eliminating.Switched to eliminate
Switch the leakage current of moment insertion switch output end, relative to Fig. 4 circuit structures in N2 transistors grid end 8 and P2 transistor grid ends
9 increase grid control circuits 1 and grid control circuit 2.The input port of grid control circuit 1 and grid control circuit 2 is with opening
Close transistor N1 grid ends 3 to connect, the output port of grid control circuit 1 connection N2 grid ends, the connection of the output port of grid control circuit 2
P2 grid ends.In the presence of grid control circuit 1 and grid control circuit 2, switch in switching, between N2 and P2 signals
Produce certain dead time so that another transistor is just opened after mono- transistor shut-off of N2 and P2, avoids switch switching wink
Between N2, P2 common conduct so that drain terminal produce transient current output port 6 is flowed to by P1 substrates 4.
Fig. 6 is a kind of implementation citing of grid control circuit.Grid control circuit 1 is by the 3rd nmos pass transistor N3 and
The phase inverter that three PMOS transistor P3 are formed realizes that grid control circuit 2 is by the 4th nmos pass transistor N4 and the 4th PMOS crystal
The phase inverter that pipe P4 is formed is realized.Due to the control signal of switching transistor N1 grid ends 3 and the control signal of switching transistor P1 grid ends 2
Anti-phase, in order to realize that logic function is correct, grid control circuit input connects switching transistor P1 grid ends 2.
When switch is switched by shut-off to unlatching, switching transistor P1 grid ends 2 design P4 from high level to low transition
Transistor size is far longer than N4, and P3 transistor sizes are far smaller than N3 so that P2 grid ends 9 first reach high level, after N2 grid ends 8
Reach high level, reach P2 and be first turned off, the purpose that N2 is then turned on, so as to avoid the transient state leakage current of switch opening process.When
Switch is by opening to during shut-off switching, and switching transistor P1 grid ends 2 are changed from low level to high level, due to designing P4 transistors
Size is far longer than N4, and P3 transistor sizes are far smaller than N3 so that P2 grid ends 8 first reach low level, reach low after N2 grid ends 9
Level, reach N2 and be first turned off, the purpose that P2 is then turned on, so as to avoid the transient state leakage current of switch OFF process.
Grid control circuit shown in Fig. 6, only as a kind of example, it can be done in the creation main scope for do not depart from the technology
Various changes.
Fig. 7 gives port logic bearing signal schematic diagram shown in analog switch of the present invention.The He of switching transistor N1 grid ends 3
The reverse signal each other of P1 grid ends 2.In grid control circuit 1 and N2 transistors grid end 8 and P2 in the presence of grid control circuit 2
Certain dead time is presented in signal between transistor grid end 9, i.e. N2 transistors grid end 8 is electric compared with height is reached after P2 transistors grid end 9
It is flat；N2 transistors grid end 8 first reaches low level compared with P2 transistors grid end 9.The foundation of the dead time eliminates switch switching wink
Between transient state leakage current generation.
By increasing grid end control circuit in traditional analog switch conduction resistance flatness design basis in the present invention, make
Analog switch conducting resistance flatness while necessarily optimized, analog switch is in transient state leakage current caused by switching moment
Also it is eliminated.
Finally illustrate, preferred embodiment above only to illustrate invention technical scheme and it is unrestricted, although passing through
The present invention is described in detail for above preferred embodiment, it is to be understood by those skilled in the art that can be in shape
Various changes are made in formula and to it in details, without departing from claims of the present invention limited range.
Claims (4)
- A kind of 1. low on-resistance flatness analog switch with leakage current technology for eliminating, it is characterised in that：First PMOS crystal Pipe, the first nmos pass transistor, substrate controlling transistor and grid control circuit；The source electrode of first PMOS transistor and drain electrode are connected with the source electrode of first nmos pass transistor and drain electrode respectively, And connect control with the grid of the first nmos pass transistor as the input and output end of analog switch, first PMOS transistor Signal processed；The substrate controlling transistor includes the second PMOS transistor and the second nmos pass transistor, second PMOS transistor and The drain electrode of second nmos pass transistor is connected with each other, and the source electrode of second PMOS transistor connects high level, and the 2nd NMOS is brilliant The source electrode of body pipe is connected with the source electrode of first PMOS transistor；The substrate of first PMOS transistor is connected to the drain electrode of second PMOS transistor；The grid control circuit includes grid control circuit I and grid control circuit II, the grid control circuit I and grid One end of control circuit II is respectively connecting to the grid of second PMOS transistor and the second nmos pass transistor, the grid control Circuit processed is used to control the substrate controlling transistor is non-concurrent to be switched on or off.
- 2. a kind of low on-resistance flatness analog switch with leakage current technology for eliminating according to claim 1, it is special Sign is：The grid control circuit I includes the 3rd PMOS transistor and the 3rd nmos pass transistor, the 3rd PMOS transistor Drain electrode with the 3rd nmos pass transistor is connected with each other, and the source electrode of the 3rd PMOS transistor meets high level, the 3rd NMOS The source electrode of transistor is connected with the source electrode of first PMOS transistor；Grid control circuit II includes the 4th PMOS transistor and the 4th nmos pass transistor, the 4th PMOS transistor and the 4th The drain electrode of nmos pass transistor is connected with each other, and the source electrode of the 4th PMOS transistor connects high level, the 4th nmos pass transistor Source electrode be connected with the source electrode of first PMOS transistor；The grid of second nmos pass transistor is connected to the drain electrode of the 3rd nmos pass transistor, second PMOS transistor Grid be connected to the drain electrode of the 4th nmos pass transistor.
- 3. a kind of low on-resistance flatness analog switch with leakage current technology for eliminating according to claim 2, it is special Sign is：3rd PMOS transistor, the 3rd nmos pass transistor, the grid of the 4th PMOS transistor and the 4th nmos pass transistor The grid of first PMOS transistor is connected to after being connected with each other.
- 4. a kind of low on-resistance flatness analog switch with leakage current technology for eliminating according to claim 2, it is special Sign is：3rd PMOS transistor, the 3rd nmos pass transistor, the grid of the 4th PMOS transistor and the 4th nmos pass transistor The grid of first nmos pass transistor is connected to after being connected with each other.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201711108482.2A CN107786190B (en) | 2017-11-09 | 2017-11-09 | Low-on-resistance flatness analog switch with leakage current elimination technology |
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| CN201711108482.2A CN107786190B (en) | 2017-11-09 | 2017-11-09 | Low-on-resistance flatness analog switch with leakage current elimination technology |
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| CN107786190A true CN107786190A (en) | 2018-03-09 |
| CN107786190B CN107786190B (en) | 2021-05-28 |
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Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109787603A (en) * | 2019-03-05 | 2019-05-21 | 上海艾为电子技术股份有限公司 | A kind of low conducting flatness analog switch |
| WO2020155015A1 (en) * | 2019-01-31 | 2020-08-06 | 华为技术有限公司 | Cmos transistor, circuit for driving liquid crystal pixels, and cmos transmission gate |
| CN112557935A (en) * | 2020-12-11 | 2021-03-26 | 重庆西南集成电路设计有限责任公司 | High-precision battery string single cell voltage detection system based on voltage moving |
| CN114050821A (en) * | 2021-11-16 | 2022-02-15 | 无锡力芯微电子股份有限公司 | Output circuit with function of inhibiting reverse electric leakage of port |
| CN114301458A (en) * | 2021-12-30 | 2022-04-08 | 合肥市芯海电子科技有限公司 | Switch circuit, multichannel sampling control circuit, analog-to-digital conversion circuit and chip |
| CN115085713A (en) * | 2022-07-28 | 2022-09-20 | 无锡众享科技有限公司 | Analog switch circuit |
| CN117811584A (en) * | 2024-02-29 | 2024-04-02 | 成都电科星拓科技有限公司 | Digital-to-analog converter |
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