CN112823474A - CMOS transistor, circuit for driving liquid crystal pixel and CMOS transmission gate - Google Patents

CMOS transistor, circuit for driving liquid crystal pixel and CMOS transmission gate Download PDF

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CN112823474A
CN112823474A CN201980065706.7A CN201980065706A CN112823474A CN 112823474 A CN112823474 A CN 112823474A CN 201980065706 A CN201980065706 A CN 201980065706A CN 112823474 A CN112823474 A CN 112823474A
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coupled
nmos transistor
transmission gate
transistor
substrate
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余泳
李心智
代永平
关雪明
刘洪�
张秉华
毛崇昌
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Huawei Technologies Co Ltd
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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
    • H03K17/51—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used
    • H03K17/56—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices
    • H03K17/687—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices the devices being field-effect transistors

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  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Logic Circuits (AREA)

Abstract

Disclosed are a CMOS transistor, a circuit for driving a liquid crystal pixel, and a CMOS transfer gate, the CMOS transfer gate including: an NMOS transistor (300), a PMOS transistor (310), and a capacitor (320); the source of the NMOS transistor (300) and the source of the PMOS transistor (310) are coupled as an input (351), the drain of the NMOS transistor (300) and the drain of the PMOS transistor (310) are coupled as an output (362); one end of the capacitor (320) is grounded, and the other end is coupled with the output end (362); the voltage of the substrate (341) of the PMOS transistor (310) is equal to the voltage of the output (362). The CMOS transmission gate can effectively relieve the problem of electric leakage after the CMOS transmission gate is turned off so that the output signal of the CMOS transmission gate is basically kept unchanged for a long time.

Description

CMOS transistor, circuit for driving liquid crystal pixel and CMOS transmission gate Technical Field
The present disclosure relates to the field of electronic technologies, and in particular, to a CMOS transistor, a circuit for driving a liquid crystal pixel, and a CMOS transmission gate.
Background
The sample-and-hold circuit is capable of tracking or holding a level value of the input signal. Under an ideal condition, when the sample-hold circuit is in a sampling state, the output signal of the sample-hold circuit changes along with the change of the input signal; when the sample-and-hold circuit is in the hold state, the output signal of the sample-and-hold circuit is held at the level value of the input signal at the instant of receiving the hold command. When the sampling hold circuit is in a sampling state, the switch is switched on, the capacitor is charged, if the capacitance value is small, the capacitor can complete charging and discharging in a short time, and at the moment, the output signal of the output end changes along with the change of the input signal; when the circuit is in a holding state, the switch is switched off, the capacitor discharges slowly because the switch is switched off and the input end of the integrated operational amplifier is in a high-impedance state, and the output signal is basically kept at a signal level value at the moment of switching off because one end of the capacitor is connected with a signal following circuit formed by the integrated operational amplifier. The switches in the sample-and-hold circuit are typically Complementary Metal Oxide Semiconductor (CMOS) transfer gates.
The CMOS transmission gate comprises a CMOS transistor and a capacitor, wherein the output end of the CMOS transistor is coupled with one end of the capacitor, and the other end of the capacitor is grounded. A CMOS transistor includes a positive channel Metal Oxide Semiconductor (PMOS) transistor and a Negative channel Metal Oxide Semiconductor (NMOS) transistor, and the PMOS transistor and the NMOS transistor are connected in parallel. A CMOS Transmission Gate (Transmission Gate) is a controllable switching circuit that can transmit both digital and analog signals. The CMOS transfer gate can be used as a sample-and-hold circuit, the output signal of which changes with the input signal when the CMOS transfer gate is turned on, and the capacitor discharges slowly when the CMOS transfer gate is turned off, and the output signal is substantially maintained at the signal level value at the moment of turning off. However, as the size of MOS transistors goes into the submicron scale, the leakage of CMOS transistors becomes more and more severe. After the CMOS transmission gate is turned off, the capacitor will discharge slowly, and the leakage of the CMOS transistor will accelerate the discharge speed of the capacitor, so that the output signal of the CMOS transmission gate can only keep at the signal level value at the turn-off instant for a short time. Therefore, it is necessary to study how to alleviate the leakage problem after the CMOS transmission gate is turned off, so as to slow down the discharging speed of the capacitor in the CMOS transmission gate, and achieve the purpose of keeping the signal level value of the output signal substantially unchanged for a long time.
Disclosure of Invention
The embodiment of the application provides a CMOS transistor, a circuit for driving a liquid crystal pixel and a CMOS transmission gate, which can effectively reduce electric leakage after the CMOS transmission gate is turned off, so that the signal level value of an output signal of the CMOS transmission gate after the CMOS transmission gate is turned off is basically kept unchanged for a long time.
In a first aspect, an embodiment of the present application provides a CMOS transmission gate, which includes: an NMOS transistor, a PMOS transistor, and a capacitor; the source electrode of the NMOS transistor and the source electrode of the PMOS transistor are coupled to serve as input ends, and the drain electrode of the NMOS transistor and the drain electrode of the PMOS transistor are coupled to serve as output ends; one end of the capacitor is grounded, and the other end of the capacitor is coupled with the output end; the voltage of the substrate of the PMOS transistor is equal to the voltage of the output end. The coupling of the NMOS and PMOS transistors may be as follows: the drain electrode of the NMOS transistor and the drain electrode of the PMOS transistor are coupled to serve as input ends, and the source electrode of the NMOS transistor and the source electrode of the PMOS transistor are coupled to serve as output ends; the voltage of the substrate of the PMOS transistor is equal to the voltage of the output end.
In the application, the NMOS transistor, the PMOS transistor and the capacitor form a CMOS transmission gate, the voltage of the substrate of the PMOS transistor is equal to the voltage of the output end of the CMOS transistor, and the potential difference from the reverse bias drain/source in the PMOS transistor to the two ends of the diode of the substrate is zero after the CMOS transistor is turned off, so that the electric leakage of the PMOS transistor and the electric leakage of the CMOS transmission gate after the CMOS transmission gate is turned off can be effectively reduced.
In an alternative implementation, the substrate of the PMOS transistor is coupled to the output terminal; or, the CMOS transmission gate further comprises: a first voltage follower; the substrate of the NMOS transistor is coupled with the output end of the first voltage follower, the non-inverting input end of the first voltage follower is coupled with the output end, and the output end of the first voltage follower is coupled with the inverting input end of the first voltage follower. The output voltage of the voltage follower is approximately equal to the input voltage of the voltage follower, and the voltage follower is in a high-resistance state for a front-stage circuit and a low-resistance state for a rear-stage circuit, so that the voltage follower plays a role in isolating the front-stage circuit and the rear-stage circuit. In this implementation, the first voltage follower is used to configure the potential difference between the reverse bias drain/source in the PMOS transistor and the two ends of the diode of the substrate to be zero or close to zero, which can both alleviate the leakage problem of the CMOS transmission gate and "isolate" the front and back stage circuits.
In an alternative implementation, the substrate of the NMOS transistor is disposed on a deep N-well or a silicon SOI on an insulating substrate, and the voltage of the substrate of the NMOS transistor is equal to the voltage of the output terminal. SOI is short for Silicon-On-Insulator. The deep N-well is also known as deep N-well. In this implementation, the substrate of the NMOS transistor is disposed on the deep N-well or SOI so as to configure the potential difference across the diode reverse-biased drain/source to substrate in the NMOS transistor to zero, which may further alleviate the leakage problem of the CMOS transmission gate.
In an alternative implementation, the substrate of the NMOS transistor is coupled to the output terminal; or, the CMOS transmission gate further comprises: a second voltage follower; the substrate of the NMOS transistor is coupled with the output end of the second voltage follower, the non-inverting input end of the second voltage follower is coupled with the output end, and the output end of the second voltage follower is coupled with the inverting input end of the second voltage follower. In the implementation mode, the substrate of the NMOS transistor is directly coupled with the output end or the output end of the second voltage follower, so that the potential difference between two ends of a diode of the reverse bias drain/source to the substrate in the NMOS transistor is zero, and the implementation is simple.
In a second aspect, an embodiment of the present application provides a CMOS transmission gate, including: an NMOS transistor, a PMOS transistor, and a capacitor; the source electrode of the NMOS transistor and the source electrode of the PMOS transistor are coupled to serve as input ends, and the drain electrode of the NMOS transistor and the drain electrode of the PMOS transistor are coupled to serve as output ends; one end of the capacitor is grounded, and the other end of the capacitor is coupled with the output end; the substrate of the NMOS transistor is arranged on a deep N well or a silicon SOI on an insulating substrate, and the voltage of the substrate of the NMOS transistor is equal to that of the output end.
In the application, the voltage of the substrate of the NMOS transistor is equal to the voltage of the output end of the CMOS transistor, and because the potential difference between the reverse bias drain/source in the NMOS transistor and the two ends of the diode of the substrate is zero after the CMOS transistor is turned off, the electric leakage of the NMOS transistor and the electric leakage of the CMOS transmission gate after the CMOS transmission gate is turned off can be effectively reduced.
In an alternative implementation, the substrate of the NMOS transistor is coupled to the output terminal; or, the CMOS transmission gate further comprises: a voltage follower; the substrate of the NMOS transistor is coupled with the output end of the voltage follower, the non-inverting input end of the voltage follower is coupled with the output end, and the output end of the voltage follower is coupled with the inverting input end of the voltage follower. In the implementation mode, the substrate of the NMOS transistor is directly coupled with the output end or the output end of the voltage follower, so that the potential difference between the reverse bias drain/source in the NMOS transistor and two ends of the diode of the substrate is zero, and the implementation is simple.
In a third aspect, an embodiment of the present application provides a circuit for driving a liquid crystal pixel, including: the CMOS transfer gate, the amplifier circuit, and the liquid crystal pixel equivalent capacitance in the above first aspect or second aspect; the output end of the CMOS transistor is coupled with one end of the amplifier circuit, and the other end of the discharger circuit is coupled with the liquid crystal pixel equivalent capacitor; when the CMOS transmission gate is conducted, the output end of the CMOS transmission gate inputs a first signal level to the amplifier, and the amplifier circuit drives the liquid crystal pixel equivalent capacitor by using the first signal level; the first signal level is a signal level input by an input end of the CMOS transmission gate; under the condition that the CMOS transmission gate is turned off, a storage capacitor in the CMOS transmission gate discharges, the output end of the CMOS transmission gate inputs a second signal level to the amplifier, and the amplifier circuit drives the liquid crystal pixel equivalent capacitor by using the second signal level; the second signal level is the signal level of the output end of the CMOS transmission gate when the CMOS transmission gate is turned off.
In the embodiment of the application, the discharger circuit is controlled by the low-leakage CMOS transmission gate to drive the liquid crystal pixel equivalent capacitor, so that the voltage of the liquid crystal pixel equivalent capacitor can be basically kept unchanged for a long time.
In a fourth aspect, embodiments of the present application provide a CMOS transistor, including: a negative channel metal oxide semiconductor NMOS transistor and a positive channel metal oxide semiconductor PMOS transistor; the source electrode of the NMOS transistor and the source electrode of the PMOS transistor are coupled to serve as input ends, and the drain electrode of the NMOS transistor and the drain electrode of the PMOS transistor are coupled to serve as output ends; the voltage of the substrate of the PMOS transistor is equal to the voltage of the output end. The structure of the MOS transistor is symmetrical, and the Source (Source) and the Drain (Drain) do not have any difference in structure. Typically, the input terminal is defined as the source and the output terminal is defined as the drain. It is understood that the NMOS and PMOS transistors may be coupled as follows: the drain electrode of the NMOS transistor and the drain electrode of the PMOS transistor are coupled to serve as input ends, and the source electrode of the NMOS transistor and the source electrode of the PMOS transistor are coupled to serve as output ends; the voltage of the substrate of the PMOS transistor is equal to the voltage of the output end.
In the application, an NMOS transistor and a PMOS transistor are connected in parallel to form a CMOS transistor, the voltage of a substrate of the PMOS transistor is equal to the voltage of an output end of the CMOS transistor, namely the potential difference from a reverse bias drain/source in the PMOS transistor to two ends of a diode of the substrate is zero; the leakage of the PMOS transistor can be reduced.
In an alternative implementation, the substrate of the PMOS transistor is coupled to the output terminal. In this implementation, the substrate of the PMOS transistor is directly coupled to the output terminal, so that the potential difference between the reverse-biased drain/source in the PMOS transistor and the two ends of the diode of the substrate is zero, and the implementation is simple.
In an alternative implementation, the substrate of the NMOS transistor is disposed on a deep N-well or a silicon SOI on an insulating substrate, and the voltage of the substrate of the NMOS transistor is equal to the voltage of the output terminal. In this implementation, the substrate of the NMOS transistor is disposed on the deep N-well or the silicon SOI on the insulating substrate, so that the potential at both ends of the diode from the reverse bias drain/source in the NMOS transistor to the substrate is configured to be the same potential, which can further alleviate the leakage problem of the CMOS transmission gate.
In an alternative implementation, the substrate of the NMOS transistor is coupled to the output terminal. In the implementation mode, the substrate of the NMOS transistor is directly coupled with the output end, so that the potential difference between the reverse bias drain/source in the NMOS transistor and two ends of the diode of the substrate is zero, and the implementation is simple.
In a fifth aspect, an embodiment of the present application provides another CMOS transistor, including: an NMOS transistor and a PMOS transistor; the source electrode of the NMOS transistor and the source electrode of the PMOS transistor are coupled to serve as input ends, and the drain electrode of the NMOS transistor and the drain electrode of the PMOS transistor are coupled to serve as output ends; the substrate of the NMOS transistor is arranged on a deep N well or a silicon SOI on an insulating substrate, and the voltage of the substrate of the NMOS transistor is equal to that of the output end.
In the application, the voltage of the substrate of the NMOS transistor is equal to the voltage of the output end of the CMOS transistor, and because the potential difference between the reverse bias drain/source in the NMOS transistor and the two ends of the diode of the substrate is zero, the electric leakage of the NMOS transistor can be effectively reduced.
In an alternative implementation, the substrate of the NMOS transistor is coupled to the output terminal; alternatively, the CMOS transistor further comprises: a voltage follower; the substrate of the NMOS transistor is coupled with the output end of the voltage follower, the non-inverting input end of the voltage follower is coupled with the output end, and the output end of the voltage follower is coupled with the inverting input end of the voltage follower. In the implementation mode, the substrate of the NMOS transistor is directly coupled with the output end or the output end of the voltage follower, so that the potential difference between the reverse bias drain/source in the NMOS transistor and two ends of the diode of the substrate is zero, and the implementation is simple.
Drawings
FIG. 1 is a schematic diagram of leakage of a single MOS transistor and a CMOS transmission gate;
FIG. 2 is a circuit diagram of a conventional CMOS transmission gate;
fig. 3 is a schematic diagram of a CMOS transmission gate according to an embodiment of the present disclosure;
FIG. 4 is a schematic diagram of another CMOS transmission gate provided in the embodiments of the present application;
FIG. 5 is a schematic diagram of another CMOS transmission gate provided in the embodiment of the present application;
FIG. 6 is a schematic diagram of another CMOS transmission gate provided in the embodiment of the present application;
FIG. 7 is a schematic diagram of another CMOS transmission gate provided in the embodiment of the present application;
FIG. 8 is a schematic diagram of another CMOS transmission gate provided in the embodiments of the present application;
FIG. 9 is a schematic diagram of another CMOS transmission gate provided in the embodiments of the present application;
FIG. 10 is a schematic diagram of another CMOS transmission gate provided in the embodiment of the present application;
FIG. 11A is a schematic diagram of an input signal provided by an embodiment of the present application;
FIG. 11B is a diagram illustrating control signals provided in accordance with an embodiment of the present application;
FIG. 11C is a schematic diagram of an output signal provided by an embodiment of the present application;
fig. 12 is a schematic diagram of a circuit for driving a liquid crystal pixel according to an embodiment of the present disclosure;
FIG. 13 is a schematic diagram of a power supply voltage provided by an embodiment of the present application;
FIG. 14A is a schematic diagram illustrating leakage of a CMOS transmission gate according to the first embodiment;
fig. 14B is a schematic diagram of leakage of a conventional CMOS transmission gate.
Detailed Description
In order to make the embodiments of the present application better understood, the technical solutions in the embodiments of the present application will be clearly described below with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are only some embodiments of the present application, but not all embodiments.
The terms "first," "second," and "third," etc. in the description and claims of the present application and the above-described drawings are used for distinguishing between similar elements and not necessarily for describing a particular sequential or chronological order. Furthermore, the terms "comprises" and "comprising," as well as any variations thereof, are intended to cover a non-exclusive inclusion, such as a list of steps or elements. A method, system, article, or apparatus is not necessarily limited to those steps or elements explicitly listed, but may include other steps or elements not explicitly listed or inherent to such process, system, article, or apparatus.
As the size of MOS transistors goes into the submicron level, the leakage of MOS transistors becomes more and more severe. FIG. 1 is a schematic diagram of leakage of a single MOS transistor and a CMOS transmission gate. As shown in fig. 1, B, D, S, G denotes a substrate (body), a drain (also referred to as drain), respectivelyReferred to as the drain terminal), the source (also referred to as the source terminal), and the gate; vDDRepresents a power supply coupled to the drain (drain) of the MOS transistor; vSSRepresenting a power supply coupled to a source of a MOS transistor; vINRepresents an input signal, i.e. an input voltage; vOUTRepresenting the output signal, i.e. the output voltage. In FIG. 1, IPUN/I CHNRefers to leakage caused by penetration between drain and source, ISVTIs sub-threshold region leakage, IGRefers to leakage of the transistor gate, IG_PRefers to the gate leakage of PMOS transistor, IG_NRefers to gate leakage of NMOS transistor, IGIDLRefers to drain leakage caused by transistor gate, IREVRefers to the leakage of a diode with reverse biased drain/source to the substrate, IJC_PLeakage of a diode that reverse biases the drain/source to the substrate (bulk port) in a PMOS transistor, IJC_NRefers to the leakage of the diode in the NMOS transistor that reverse biases the drain/source to the substrate (bulk port). FIG. 1 shows the leakage pattern of NMOS and PMOS transistors in a CMOS transmission gate, where the reverse biased drain/source to substrate diode leakage accounts for the major portion of the CMOS transmission gate leakage, i.e., IJC_P、I JC_PAccounting for a major portion of the leakage of the CMOS transfer gate. The technical problem that this application mainly solved is to alleviate the electric leakage problem after CMOS transmission gate closes to slow down the discharge rate of condenser. The conventional CMOS pass gate will be described first, and the reason for the serious leakage will be further described.
Fig. 2 is a circuit diagram of a conventional CMOS transmission gate. As shown in fig. 2, 100 is an NMOS transistor, 130 is a P-well on the NMOS transistor, 180 is a bulk port (also referred to as a substrate) on the P-well 130, 101 is a gate of the NMOS transistor (as a switch control port, the turn-off of the NMOS transistor is controlled by a signal); 110 is a PMOS transistor, 140 is an N-type well on the PMOS transistor, 141 is a bulk port (also called substrate) on the N-type well 140, and 111 is a gate of the PMOS transistor (as a switch control port, which controls the turn-off of the PMOS transistor by a signal); the source of the NMOS transistor and the source of the PMOS transistor are coupled together to form a signal input 151; the drain of the NMOS transistor and the drain of the PMOS transistor are coupled together to form a signal output terminal 162; one end of the capacitor 120 is grounded, and the other end is coupled to the signal output terminal 162; the bulk port 180 is grounded; the bulk port 141 is coupled to VDD. VDD is a power supply. In a traditional CMOS transmission gate, a bulk port on an N-type well of a PMOS transistor is coupled with VDD, and a drain electrode of the PMOS transistor is coupled with a signal output end; the bulk port on the P-well of the NMOS transistor is coupled to ground (i.e., GND), and the drain of the NMOS transistor is coupled to the signal output terminal. In a conventional CMOS transmission gate, after a PMOS transistor is turned off, a potential difference between two ends of a diode from a drain to a substrate (bulk) in the PMOS transistor is not zero, so that the diode leaks electricity, and a discharge speed of a capacitor is increased. Similarly, in the conventional CMOS transmission gate, the discharge speed of the capacitor is also increased after the NMOS transistor is turned off. In practical application, after the CMOS transmission gate is turned off, the potential difference between the two ends of the diode between the drain of the PMOS transistor and the drain of the NMOS transistor and the substrate (bulk) tends to be high, which causes the capacitor to discharge at a fast speed, thereby greatly reducing the time period for the CMOS transmission gate to keep the level value of the output signal substantially unchanged. The potentials are also referred to as potentials. The electric potential of a certain point in the circuit refers to the difference between the point and the specified zero electric potential. Voltage refers to the difference in the potential between two points in the circuit. The equipotential means that the voltage difference across the conductors is zero.
It will be appreciated that the slower the capacitor is discharged, the longer the CMOS transfer gate will remain substantially constant at the voltage level of the output signal.
As can be seen from the above analysis, one reason for the faster discharge of the capacitor in the conventional CMOS transmission gate is the large potential difference between the drain or source of the PMOS transistor as the signal output terminal and the substrate (i.e., the N-type well). In order to slow down the discharge speed of the capacitor in the CMOS transmission gate, one solution provided by the present application is to make the drain or source of the PMOS transistor as the signal output end have the same potential as the substrate (bulk port).
Example one
Fig. 3 is a schematic diagram of a CMOS transmission gate according to an embodiment of the present disclosure. As shown in fig. 3, 300 is an NMOS transistor, 330 is a P-well on the NMOS transistor, 380 is a bulk port (also referred to as a substrate) on the P-well 330, and 301 is a gate of the NMOS transistor (as a switch control port, which controls the turn-off of the NMOS transistor by a signal); 310 is a PMOS transistor, 340 is an N-well on the PMOS transistor, 341 is a bulk port (also called substrate) on the N-well 340, 311 is a gate of the PMOS transistor (as a switch control port, the turn-off of the PMOS transistor is controlled by a signal); the source of the NMOS transistor 300 and the source of the PMOS transistor 310 are coupled together to form a signal input terminal 351; the drain of the NMOS transistor 300 and the drain of the PMOS transistor 310 are coupled together to form a signal output 362; one end of the capacitor 320 is grounded, and the other end is coupled to the signal output terminal 362; the bulk port 380 is connected to ground; the bulk port 341 is coupled to the signal output 362. As can be seen from comparing fig. 2 and fig. 3, the substrate 141 of the PMOS transistor in the conventional CMOS transmission gate is coupled to VDD, and the substrate of the PMOS transistor in the CMOS transmission gate in the present application is coupled to the signal output terminal 362. In this application, the substrate of the PMOS transistor is coupled to the signal output terminal 362, so that the potential difference between the two ends of the diode between the substrate (i.e., the bulk port 341) and the drain of the PMOS transistor is zero, thereby greatly reducing the leakage of the PMOS transistor, and the discharging speed of the capacitor is not accelerated.
In practical applications, the on and off of the CMOS transmission gate can be controlled by controlling the voltage of the gate of the PMOS transistor and the gate of the NMOS transistor. When the CMOS transmission gate is conducted, the output end of the CMOS transmission gate outputs the same signal as the input end of the CMOS transmission gate. That is, the output signal of the CMOS transmission gate changes following the input signal change, and the function of sampling the input signal is realized. With the CMOS transfer gate turned off, the capacitor in the CMOS transfer gate discharges slowly, and the voltage at the output of the CMOS transfer gate remains at the voltage at the output of the CMOS transfer gate when the CMOS transfer gate is turned off. That is, after the CMOS transmission gate is turned off, the voltage at the output of the CMOS transmission gate remains substantially constant for a certain time. Thus, the CMOS transmission gate realizes the function of keeping the output signal. It will be appreciated that by controlling the turn-on and turn-off of the CMOS transmission gates, the input signal can be sampled and the output signal can be held substantially constant for a period of time.
In the foregoing embodiment, the drain of the PMOS transistor as the signal output terminal is directly coupled to the substrate of the PMOS transistor, so that the drain of the PMOS transistor as the signal output terminal is at the same potential as the substrate (i.e. bulk port). It should be understood that the above embodiment is only an alternative way to make the drain of the PMOS transistor as the signal output terminal at the same potential as its substrate (i.e., bulk port). The scheme that the drain of the PMOS transistor as the signal output terminal is made to be at the same potential with the substrate (i.e. bulk port) thereof in other ways to reduce the leakage thereof is also claimed in the present application.
Another CMOS pass gate provided by the present application is described below, in which a voltage follower is used to make the drain of the PMOS transistor, which is the signal output terminal, the same potential as its substrate (i.e., bulk port).
Example two
Fig. 4 is a schematic diagram of another CMOS transmission gate according to an embodiment of the present disclosure. As shown in fig. 4, 400 is an NMOS transistor, 430 is a P-well on the NMOS transistor, 480 is a bulk port (also referred to as a substrate) on the P-well 430, and 401 is a gate of the NMOS transistor (as a switch control port, which controls the turn-off of the NMOS transistor by a signal); 410 is a PMOS transistor, 440 is an N-well on the PMOS transistor, 441 is a bulk port (also called substrate) on the N-well 440, 411 is a gate of the PMOS transistor (as a switch control port, the turn-off of the PMOS transistor is controlled by a signal); 470 is a voltage follower (also referred to as a buffer), 471 is the non-inverting input of voltage follower 470, 472 is the inverting input of voltage follower 470, 473 is the output of voltage follower 470; the source of the NMOS transistor 400 and the source of the PMOS transistor 410 are coupled together to form a signal input 451; the drain of the NMOS transistor 400 and the drain of the PMOS transistor 410 are coupled together to form a signal output 462; one end of the capacitor 420 is grounded, and the other end is coupled to the signal output terminal 462; bulk port 480 is coupled to ground; bulk port 441 is coupled to output 473 of voltage follower 470, non-inverting input 471 of voltage follower 470 is coupled to signal output 462, and inverting input 472 of voltage follower 470 is coupled to output 473 of voltage follower 470. The output voltage of the voltage follower 470 is equal to the voltage inputted from the non-inverting input terminal 471, i.e. the voltage inputted from the non-inverting input terminal 471 is equal to the voltage outputted from the output terminal 473. Since the non-inverting input 471 of the voltage follower 470 is coupled to the signal output 462, the bulk port 441 is coupled to the output 473 of the voltage follower 470. Therefore, the voltage of the signal output terminal 462 is equal to the voltage of the bulk port 441, i.e., the drain of the PMOS transistor as the signal output terminal is at the same potential as the substrate (i.e., the bulk port). The voltage follower 470 not only makes the drain of the PMOS transistor as the signal output end be at the same potential as the substrate (i.e., bulk port), but also has other functions. One of the functions of the voltage follower is buffering, so that signal loss generated when the input impedance of the next stage is smaller due to higher output impedance can be avoided to a certain extent, and the effect of starting and stopping is achieved. The second function of the voltage follower is isolation, and the voltage follower has the characteristics of high input impedance and low output impedance, so that the voltage follower presents a high-impedance state for a previous-stage circuit and presents a low-impedance state for a next-stage circuit, and the voltage follower is commonly used in an intermediate stage to isolate the previous-stage circuit and the next-stage circuit and eliminate mutual influence between the previous-stage circuit and the next-stage circuit. The third function of the voltage follower is impedance matching and improvement of loading capacity. The voltage follower has the characteristics of high input impedance and low output impedance, so that the voltage follower can complete the function of impedance matching in a circuit, and the next-stage amplifying circuit works in a better state. It can be seen that the voltage follower can also improve the performance of the CMOS pass gate.
The foregoing embodiments describe a scheme for slowing the discharge rate of a capacitor by reducing the leakage of PMOS transistors in CMOS transmission gates. The leakage of the NMOS transistor in the CMOS pass gate also accelerates the discharge rate of the capacitor. The leakage of an NMOS transistor in a CMOS pass gate is primarily the leakage of the diode in that NMOS transistor that reverse biases the drain/source to the substrate (i.e., bulk port). As can be seen from fig. 1, in the conventional CMOS transmission gate, the substrate of the NMOS transistor is grounded, and the drain of the NMOS transistor serves as a signal output terminal. In practical application, after the CMOS transmission gate is turned off, the potential difference between the two ends of the diode between the drain of the NMOS transistor and the substrate (bulk port) tends to be high, which causes the capacitor to discharge at a fast speed, thereby greatly reducing the time period for the CMOS transmission gate to keep the voltage value of the output signal substantially unchanged. In order to slow down the discharge speed of the capacitor in the CMOS transmission gate, another solution provided by the present application is to make the drain or source of the NMOS transistor as the signal output end be at the same potential as its substrate (i.e., bulk port). In conventional circuits comprising a plurality of NMOS transistors, each NMOS transistor is formed directly on a large substrate p-sub (p-well), which is always at zero potential. Therefore, in a conventional circuit including a plurality of NMOS transistors, the substrate potentials of the respective NMOS transistors are uniform, and the substrate potential of any one NMOS transistor cannot be individually configured. In the present application, the substrate of at least one NMOS transistor in the CMOS transmission gate is disposed On Silicon-On-Insulator (SOI) On a deep N-well or an insulating substrate, i.e., the at least one NMOS transistor is isolated from other NMOS transistors, so that the potential of the substrate of the at least one NMOS transistor can be configured as desired.
The following describes yet another CMOS pass gate provided by the present application. In the CMOS transmission gate, the drain of the NMOS transistor as the signal output end is at the same potential as the substrate (i.e. bulk port) of the NMOS transistor.
EXAMPLE III
Fig. 5 is a schematic diagram of a CMOS transmission gate according to an embodiment of the present disclosure, as shown in fig. 5, 500 is an NMOS transistor, 530 is a P-well on the NMOS transistor, 580 is a bulk port (also referred to as a substrate) on the P-well 530, 501 is a gate of the NMOS transistor (serving as a switch control port, and controlling the NMOS transistor to be turned off by a signal); 510 is a PMOS transistor, 540 is an N-well on the PMOS transistor, 541 is a bulk port (also called substrate) on the N-well 540, 511 is a gate of the PMOS transistor (as a switch control port, the turn-off of the PMOS transistor is controlled by a signal); the source of the NMOS transistor 500 and the source of the PMOS transistor 510 are coupled together to form a signal input 551; the drain of the NMOS transistor 500 and the drain of the PMOS transistor 510 are coupled together to form a signal output 562; one end of the capacitor 520 is grounded, and the other end is coupled to the signal output end 562; the bulk port 541 is coupled to VDD (i.e., power supply); the bulk port 580 is coupled to the signal output 562. It is understood that the NMOS transistor 500 is fabricated on a deep N-well or SOI, i.e., the substrate of the NMOS transistor is disposed on the deep N-well or SOI, the NMOS transistor 500 is isolated from other NMOS transistors, and the bulk port 580 thereof may be coupled to the signal output 562. In this application, the substrate of the NMOS transistor is coupled to the signal output end 562, so that the potential difference between the two ends of the diode between the substrate (i.e., bulk port) and the drain of the NMOS transistor is zero, thereby greatly alleviating the leakage condition of the NMOS transistor, and the discharging speed of the capacitor is not accelerated.
Another CMOS pass gate provided by the present application is described below, in which a voltage follower is used to make the drain of the NMOS transistor as the signal output end be at the same potential as its substrate (i.e., bulk port) to slow down the discharging speed of the capacitor.
Example four
Fig. 6 is a schematic diagram of another CMOS transmission gate according to an embodiment of the present disclosure. As shown in fig. 6, 600 is an NMOS transistor, 630 is a P-well on the NMOS transistor, 680 is a bulk port (also referred to as a substrate) on the P-well 630, 601 is a gate of the NMOS transistor (as a switch control port, the turn-off of the NMOS transistor is controlled by a signal); 610 is a PMOS transistor, 640 is an N-type well on the PMOS transistor, 641 is a bulk port (also called a substrate) on the N-type well 640, and 611 is a gate of the PMOS transistor (as a switch control port, which controls the turn-off of the PMOS transistor by a signal); 670 is a voltage follower (also referred to as a buffer), 671 is a non-inverting input terminal of the voltage follower 670, 672 is an inverting input terminal of the voltage follower 670, 673 is an output terminal of the voltage follower 670; the source of the NMOS transistor 600 and the source of the PMOS transistor 610 are coupled together to form a signal input terminal 651; the drain of the NMOS transistor 600 and the drain of the PMOS transistor 610 are coupled together to form a signal output 662; one end of the capacitor 620 is grounded, and the other end is coupled to the signal output terminal 662; bulk port 641 is coupled to VDD; the bulk port 680 is coupled to the output terminal 673 of the voltage follower 670, the non-inverting input 671 of the voltage follower 670 is coupled to the signal output terminal 662, and the inverting input 672 of the voltage follower 670 is coupled to the output terminal 673 of the voltage follower 670. The output voltage of the voltage follower 670 is equal to the voltage input by the non-inverting input 671, i.e., the voltage input by the non-inverting input 671 is equal to the voltage output by the output 673. Since the non-inverting input 671 of the voltage follower 670 is coupled to the signal output 662, the bulk port 680 is coupled to the output 673 of the voltage follower 670. Therefore, the voltage of the signal output terminal 662 is equal to the voltage of the bulk port 680, i.e., the drain of the NMOS transistor as the signal output terminal is at the same potential as the substrate (i.e., the bulk port). The NMOS transistor 600 is fabricated on a deep N-well or SOI, i.e., the substrate of the NMOS transistor is disposed on the deep N-well or SOI, the NMOS transistor 600 is isolated from other NMOS transistors, i.e., the bulk port 680 can be coupled to the signal output 662.
Compared with the traditional CMOS transmission gate, the CMOS transmission gate in the first embodiment and the second embodiment has the advantages that the NMOS transistor is kept unchanged; the CMOS pass gates in example three and example four remain unchanged from the conventional CMOS pass gates. It is understood that in the foregoing embodiment, the leakage of only one of the NMOS transistor and the PMOS transistor can be reduced. In order to slow down the discharge speed of the capacitor in the CMOS transmission gate as much as possible, the above four embodiments can be combined to obtain the CMOS transmission gate which can reduce the leakage of the PMOS transistor and the leakage of the NMOS transistor.
Several CMOS transmission gates that reduce both the leakage of PMOS transistors and the leakage of NMOS transistors are described below.
EXAMPLE five
Fig. 7 is a schematic diagram of another CMOS transmission gate according to an embodiment of the present disclosure. As shown in fig. 7, 700 is an NMOS transistor, 730 is a P-well on the NMOS transistor, 780 is a bulk port (also referred to as a substrate) on the P-well 730, 701 is a gate of the NMOS transistor (as a switch control port, the turn-off of the NMOS transistor is controlled by a signal); 710 is a PMOS transistor, 740 is an N-type well on the PMOS transistor, 741 is a bulk port (also called a substrate) on the N- type well 740, and 711 is a gate of the PMOS transistor (as a switch control port, the turn-off of the PMOS transistor is controlled by a signal); the source of the NMOS transistor 700 and the source of the PMOS transistor 710 are coupled together to form a signal input 751; the drain of the NMOS transistor 700 and the drain of the PMOS transistor 710 are coupled together to form a signal output 762; one end of the capacitor 720 is grounded, and the other end is coupled to the signal output terminal 762; bulk port 780 is coupled signal output 762; the bulk port 741 is coupled to the signal output 762. The NMOS transistor 700 is formed on a deep N-well or SOI, i.e., the substrate of the NMOS transistor is disposed on the deep N-well or SOI, and the NMOS transistor 700 is isolated from other NMOS transistors, i.e., the bulk port 780 can be coupled to the signal output port 762. In the CMOS pass gate of fig. 7, since the bulk port 780 and the bulk port 741 are both coupled to the signal output port 762, the leakage of the NMOS transistor and the leakage of the PMOS transistor are both reduced, thereby slowing down the discharging speed of the capacitor.
EXAMPLE six
Fig. 8 is a schematic diagram of another CMOS transmission gate according to an embodiment of the present disclosure. As shown in fig. 8, 800 is an NMOS transistor, 830 is a P-well on the NMOS transistor, 880 is a bulk port (also referred to as a substrate) on the P-well 830, 801 is a gate of the NMOS transistor (as a switch control port, which controls the turn-off of the NMOS transistor by a signal); 810 is a PMOS transistor, 840 is an N-type well on the PMOS transistor, 841 is a bulk port (also called substrate) on the N-type well 840, 811 is a gate of the PMOS transistor (as a switch control port, the turn-off of the PMOS transistor is controlled by a signal); 870 is a voltage follower (also referred to as a buffer), 871 is a non-inverting input terminal of the voltage follower 870, 872 is an inverting input terminal of the voltage follower 870, and 873 is an output terminal of the voltage follower 870; the source of the NMOS transistor 800 and the source of the PMOS transistor 810 are coupled together to form a signal input terminal 851; the drain of the NMOS transistor 800 and the drain of the PMOS transistor 810 are coupled together to form a signal output 862; one end of the capacitor 820 is grounded, and the other end is coupled to the signal output end 862; the bulk port 880 is coupled with the signal output end 862; the bulk port 841 is coupled to the output terminal 873 of the voltage follower 870, the non-inverting input terminal 871 of the voltage follower 870 is coupled to the signal output terminal 862, and the inverting input terminal 872 of the voltage follower 870 is coupled to the output terminal 873 of the voltage follower 870. 862 and 861 are both signal outputs. Referring to the second and third embodiments, the leakage of the NMOS transistor and the leakage of the PMOS transistor in the CMOS transmission gate are both reduced, thereby slowing down the discharging speed of the capacitor.
EXAMPLE seven
Fig. 9 is a schematic diagram of another CMOS transmission gate according to an embodiment of the present application. As shown in fig. 9, 900 is an NMOS transistor, 930 is a P-well on the NMOS transistor, 980 is a bulk port (also referred to as a substrate) on the P-well 930, 901 is a gate of the NMOS transistor (as a switch control port, the turn-off of the NMOS transistor is controlled by a signal); 910 is a PMOS transistor, 940 is an N-type well on the PMOS transistor, 941 is a bulk port (also called substrate) on the N-type well 940, and 911 is a gate of the PMOS transistor (as a switch control port, which controls the turn-off of the PMOS transistor by a signal); 970 is a voltage follower (also referred to as a buffer), 971 is a non-inverting input terminal of the voltage follower 970, 972 is an inverting input terminal of the voltage follower 970, and 973 is an output terminal of the voltage follower 970; the source of NMOS transistor 900 is coupled to the source of PMOS transistor 910 to form a signal input 951; the drain of the NMOS transistor 900 is coupled to the drain of the PMOS transistor 910 to form a signal output 962; one end of the capacitor 920 is grounded, and the other end is coupled to the signal output end 962; the bulk port 941 is coupled to the signal output terminal 962; bulk port 980 is coupled to output 973 of voltage follower 970, non-inverting input 971 of voltage follower 970 is coupled to signal output 962, and inverting input 972 of voltage follower 970 is coupled to output 973 of voltage follower 970. Referring to the first and fourth embodiments, the leakage of the NMOS transistor and the leakage of the PMOS transistor in the CMOS transmission gate are both reduced, thereby slowing down the discharging speed of the capacitor.
Example eight
Fig. 10 is a schematic diagram of another CMOS transmission gate according to an embodiment of the present application. As shown in fig. 10, 1000 is an NMOS transistor, 1030 is a P-well on the NMOS transistor, 1080 is a bulk port (also called a substrate) on the P-well 1030, 1001 is a gate of the NMOS transistor (as a switch control port, the turn-off of the NMOS transistor is controlled by a signal); 1010 is a PMOS transistor, 1040 is an N-type well on the PMOS transistor, 1041 is a bulk port (also called substrate) on the N-type well 1040, 1011 is a gate of the PMOS transistor (as a switch control port, the turn-off of the PMOS transistor is controlled by a signal); 1070 is a first voltage follower, 1071 is the non-inverting input of the first voltage follower 1070, 1072 is the inverting input of the first voltage follower 1070, 1073 is the output of the first voltage follower 1070; 1090 is a second voltage follower, 1091 is a non-inverting input terminal of the second voltage follower 1090, 1092 is an inverting input terminal of the second voltage follower 1090, and 1093 is an output terminal of the second voltage follower 1090; the source of the NMOS transistor 1000 and the source of the PMOS transistor 1010 are coupled together to form a signal input 1051; the drain of the NMOS transistor 1000 and the drain of the PMOS transistor 1010 are coupled together to form a signal output 1062; one end of the capacitor 1020 is grounded, and the other end is coupled to the signal output port 1062; the bulk port 1041 is coupled to the output end 1073 of the first voltage follower 1070, the non-inverting input end 1071 of the first voltage follower 1070 is coupled to the signal output end 1062, and the inverting input end 1072 of the first voltage follower 1070 is coupled to the output end 1073 of the first voltage follower 1070; the bulk port 1080 is coupled to the output 1093 of the second voltage follower 1090, the non-inverting input 1091 of the second voltage follower 1090 is coupled to the signal output 1062, and the inverting input 1092 of the second voltage follower 1090 is coupled to the output 1093 of the second voltage follower 1090. The NMOS transistor 1000 is formed on a deep N-well or SOI, i.e., the substrate of the NMOS transistor is disposed on the deep N-well or SOI, and the NMOS transistor 1000 is isolated from other NMOS transistors, i.e., the bulk port 1080 thereof can be coupled to the signal output port 1062. Referring to the second and fourth embodiments, the leakage of the NMOS transistor and the leakage of the PMOS transistor in the CMOS transmission gate are both reduced, thereby slowing down the discharging speed of the capacitor.
The foregoing embodiments describe a variety of CMOS transfer gates, each of which may be used as a sample-and-hold circuit. How the CMOS transmission gate in the foregoing embodiment operates as a sample-and-hold circuit will be described.
In the CMOS transmission gate of the foregoing embodiment, the control signal of the gate of the NMOS transistor and the control signal of the gate of the PMOS transistor can be obtained from the front-stage driving circuit and are at opposite high and low levels, that is, the control signal of the gate of the PMOS transistor is at a low level when the control signal of the gate of the NMOS transistor is at a high level, and the control signal of the gate of the PMOS transistor is at a high level when the control signal of the gate of the NMOS transistor is at a low level. The pre-driver circuit may be a pulse generator or other circuits, and the present application is not limited thereto. The NMOS transistor is switched on at a high level and switched off at a low level; the PMOS transistor is turned on at a low level and turned off at a high level. The NMOS transistor and the PMOS transistor are turned on or off simultaneously. That is, when the CMOS transmission gate is turned off, both the NMOS transistor and the PMOS transistor are turned off; when the CMOS transmission gate is conducted, the NMOS transistor and the PMOS transistor are conducted. When the CMOS transmission gate is conducted (namely, the sampling hold circuit is in a sampling state), the output signal of the CMOS transmission gate changes along with the change of the input signal; when the CMOS transmission gate is turned off (i.e., the sample and hold circuit is in the hold state), the capacitor slowly discharges and the output signal of the CMOS transmission gate remains substantially at the signal level value at the moment of the turn-off. The input signal of the CMOS transmission gate in any of the foregoing embodiments may be 1101 shown in fig. 11A, the control signal of the gate of the PMOS transistor in the CMOS transmission gate may be 1102 in fig. 11B, the control signal of the gate of the NMOS transistor may be 1103 in fig. 11B, and the output signal of the CMOS transmission gate may be 1104 shown in fig. 11C. The bulk port (i.e., substrate) of the PMOS, which is at the same potential as the signal output port, is coupled to the signal output of the CMOS transmission gate, and has a voltage 1104 shown at 11C.
The CMOS transmission gate in the present application is composed of a switch circuit, and can be applied to a circuit for driving a liquid crystal pixel, a Dynamic Random Access Memory (DRAM), a flash Memory (flash), and other circuits.
An embodiment in which the CMOS transfer gate in the present application is applied to a circuit for driving a liquid crystal pixel is described below.
Example nine
Fig. 12 is a schematic diagram of a circuit for driving a liquid crystal pixel according to an embodiment of the present disclosure. As shown in fig. 12, 1 denotes an analog level input line; 2 denotes a gate control line of the PMOS transistor; 3 a PMOS transistor constituting a CMOS transmission gate; 4 an NMOS transistor constituting a CMOS transfer gate; 5 denotes a gate control line of the NMOS transistor; 6 denotes a storage capacitor; 7 denotes an amplifier circuit; and 8 denotes a liquid crystal pixel equivalent capacitance. In the circuit for driving the liquid crystal pixel, the analog signal on the analog level input line (1) is sampled to realize the drive of the liquid crystal pixel equivalent capacitor (8), thereby realizing the function of a sampling and holding circuit. As shown in fig. 12, a pair of clock pulses (e.g., 1102 and 1103 in fig. 11B) which do not overlap each other are respectively introduced into the gate control line (2) of the PMOS transistor and the gate control line (5) of the NMOS transistor to control on/off of the PMOS transistor (3) and NMOS transistor (4) which constitute the CMOS transfer gate, and thus the process of storing an analog signal into the storage capacitor (6) through the analog level input line (1) and the selection of the analog signal level value are controlled, and the analog signal level of the storage capacitor (6) drives the liquid crystal pixel equivalent capacitance (8) through the amplifier circuit (7).
To verify that the CMOS pass gate in the previous embodiment can slow down the discharging speed of the capacitor, i.e. the leakage of the CMOS pass gate is less. The leakage of the conventional CMOS transmission gate and the CMOS transmission gate in the first embodiment will be compared.
The input signal of the CMOS transmission gate in the first embodiment may be 1101 shown in fig. 11A, the control signal of the gate of the PMOS transistor in the CMOS transmission gate may be 1102 shown in fig. 11B, the control signal of the gate of the NMOS transistor may be 1103 shown in fig. 11B, and the output signal of the CMOS transmission gate is 1104 shown in fig. 11C. The bulk port (i.e., substrate) of the PMOS, which is at the same potential as the signal output port, is coupled to the signal output of the CMOS transmission gate, and has a voltage 1104 shown at 11C.
The input signal of a conventional CMOS transmission gate may be 1101 shown in fig. 11A, the control signal of the gate of the PMOS transistor in the CMOS transmission gate may be 1102 shown in fig. 11B, and the control signal of the gate of the NMOS transistor may be 1103 shown in fig. 11B. The bulk port (i.e., substrate) of the PMOS is coupled to VDD, the supply voltage. In fig. 13, reference numeral 1105 denotes VDD, and reference numeral 1104 denotes a voltage at the signal output terminal. That is, 1104 is the voltage at the bulk port of the PMOS transistor in the conventional CMOS transmission gate, and 1105 is the voltage at the bulk port of the PMOS transistor in the CMOS transmission gate in the first embodiment.
Fig. 14A is a schematic diagram of leakage of a CMOS transmission gate in the first embodiment, and fig. 14B is a schematic diagram of leakage of a conventional CMOS transmission gate. In fig. 14A and 14B, the axis of ordinate is leakage current in pico amperes; the abscissa axis is the voltage of the input signal in volts. As can be seen by comparing fig. 14A and 14B, the CMOS transmission gate in the first embodiment leaks less power than the conventional CMOS transmission gate. Since the leakage of the CMOS transfer gate is reduced, the discharge rate of the capacitor is slowed down after the CMOS transfer gate is turned off. Therefore, in the present application, the leakage of the CMOS transistor after the CMOS transmission gate is turned off is reduced, so that the output signal thereof is substantially constant for a long time.
The foregoing embodiments describe various CMOS transmission gates in which a parallel structure of NMOS transistors and PMOS transistors (i.e., CMOS transistors) can be applied to other circuits as a separate structure without coupling a capacitor to obtain the CMOS transmission gates in the foregoing embodiments. The parallel connection of the NMOS transistor and the PMOS transistor can form a low-leakage switch circuit. It is understood that the parallel connection structure of the NMOS transistor and the PMOS transistor in the foregoing embodiments is a low leakage switch circuit.
It should be noted that the term "coupled" as used herein to express the intercommunication or interaction between different components may include direct connection or indirect connection through other components. Coupling one component to another component may be the presence of a physical connection between the two components, the electrical connection of the two components, or the interaction of the two components through other means.
While the invention has been described with reference to specific embodiments, the scope of the invention is not limited thereto, and those skilled in the art can easily conceive various equivalent modifications or substitutions within the technical scope of the invention. Therefore, the protection scope of the present application shall be subject to the protection scope of the claims.

Claims (9)

  1. A CMOS transmission gate, comprising: a negative channel metal oxide semiconductor NMOS transistor, a positive channel metal oxide semiconductor PMOS transistor and a capacitor;
    the source electrode of the NMOS transistor and the source electrode of the PMOS transistor are coupled to serve as input ends, and the drain electrode of the NMOS transistor and the drain electrode of the PMOS transistor are coupled to serve as output ends; one end of the capacitor is grounded, and the other end of the capacitor is coupled with the output end; the voltage of the substrate of the PMOS transistor is equal to the voltage of the output end.
  2. The CMOS transmission gate of claim 1, wherein the substrate of the PMOS transistor couples the output;
    alternatively, the first and second electrodes may be,
    the CMOS transmission gate further comprises: a first voltage follower; the substrate of the NMOS transistor is coupled with the output end of the first voltage follower, the non-inverting input end of the first voltage follower is coupled with the output end, and the output end of the first voltage follower is coupled with the inverting input end of the first voltage follower.
  3. The CMOS transmission gate of claim 1 or 2, wherein the substrate of the NMOS transistor is disposed on a silicon SOI on a deep N-well or an insulating substrate, and the voltage of the substrate of the NMOS transistor is equal to the voltage of the output terminal.
  4. The CMOS transmission gate of claim 3, wherein the substrate of said NMOS transistor is coupled to said output terminal;
    alternatively, the first and second electrodes may be,
    the CMOS transmission gate further comprises: a second voltage follower; the substrate of the NMOS transistor is coupled with the output end of the second voltage follower, the non-inverting input end of the second voltage follower is coupled with the output end, and the output end of the second voltage follower is coupled with the inverting input end of the second voltage follower.
  5. A circuit for driving a liquid crystal pixel, comprising: the CMOS transfer gate, amplifier circuit, and liquid crystal pixel equivalent capacitance of any of claims 1 to 4;
    the output end of the CMOS transistor is coupled with one end of the amplifier circuit, and the other end of the discharger circuit is coupled with the liquid crystal pixel equivalent capacitor;
    when the CMOS transmission gate is conducted, the output end of the CMOS transmission gate inputs a first signal level to the amplifier, and the amplifier circuit drives the liquid crystal pixel equivalent capacitor by using the first signal level; the first signal level is a signal level input by an input end of the CMOS transmission gate;
    under the condition that the CMOS transmission gate is turned off, a storage capacitor in the CMOS transmission gate discharges, the output end of the CMOS transmission gate inputs a second signal level to the amplifier, and the amplifier circuit drives the liquid crystal pixel equivalent capacitor by using the second signal level; the second signal level is the signal level of the output end of the CMOS transmission gate when the CMOS transmission gate is turned off.
  6. A complementary metal oxide semiconductor, CMOS, transistor, comprising: a negative channel metal oxide semiconductor NMOS transistor and a positive channel metal oxide semiconductor PMOS transistor;
    the source electrode of the NMOS transistor and the source electrode of the PMOS transistor are coupled to serve as input ends, and the drain electrode of the NMOS transistor and the drain electrode of the PMOS transistor are coupled to serve as output ends; the voltage of the substrate of the PMOS transistor is equal to the voltage of the output end.
  7. The CMOS transistor of claim 6 wherein the substrate of said PMOS transistor is coupled to said output terminal.
  8. The CMOS transistor of claim 6 or 7 wherein the substrate of the NMOS transistor is disposed on a deep N-well or silicon SOI on an insulating substrate, the substrate of the NMOS transistor having a voltage equal to the voltage of the output terminal.
  9. The CMOS transistor of claim 8, wherein the substrate of the NMOS transistor couples the output.
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CN106656132A (en) * 2016-12-31 2017-05-10 唯捷创芯(天津)电子技术股份有限公司 Extremely low current leakage analog switch, chip and communication terminal
CN107094013A (en) * 2017-04-17 2017-08-25 电子科技大学 A kind of transmission gate circuit
CN107786190A (en) * 2017-11-09 2018-03-09 中电科技集团重庆声光电有限公司 A kind of low on-resistance flatness analog switch with leakage current technology for eliminating

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