CN114301458A - Switch circuit, multichannel sampling control circuit, analog-to-digital conversion circuit and chip - Google Patents

Switch circuit, multichannel sampling control circuit, analog-to-digital conversion circuit and chip Download PDF

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Publication number
CN114301458A
CN114301458A CN202111666722.7A CN202111666722A CN114301458A CN 114301458 A CN114301458 A CN 114301458A CN 202111666722 A CN202111666722 A CN 202111666722A CN 114301458 A CN114301458 A CN 114301458A
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Prior art keywords
circuit
switch
field effect
effect transistor
switching
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Inventor
袁超
刘帅锋
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Hefei Chipsea Electronics Technology Co Ltd
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Hefei Chipsea Electronics Technology Co Ltd
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Priority to CN202111666722.7A priority Critical patent/CN114301458A/en
Publication of CN114301458A publication Critical patent/CN114301458A/en
Priority to PCT/CN2022/138405 priority patent/WO2023124941A1/en
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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M1/00—Analogue/digital conversion; Digital/analogue conversion
    • H03M1/06—Continuously compensating for, or preventing, undesired influence of physical parameters
    • H03M1/08—Continuously compensating for, or preventing, undesired influence of physical parameters of noise
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M1/00—Analogue/digital conversion; Digital/analogue conversion
    • H03M1/12—Analogue/digital converters
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M1/00—Analogue/digital conversion; Digital/analogue conversion
    • H03M1/12—Analogue/digital converters
    • H03M1/34—Analogue value compared with reference values
    • H03M1/38—Analogue value compared with reference values sequentially only, e.g. successive approximation type

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Electronic Switches (AREA)
  • Analogue/Digital Conversion (AREA)

Abstract

The utility model relates to a switch circuit, multichannel sampling control circuit, analog-to-digital conversion circuit and chip, wherein, switch circuit includes: the ESD protection circuit comprises a plurality of switch branches connected in parallel, wherein each switch branch in the switch branches comprises an ESD resistor and a switch module, and the ESD resistor and the switch module are connected between the input end and the output end of the switch circuit in series. The multichannel sampling control circuit includes: a multi-channel multiplexing circuit comprising a plurality of first switch circuits, wherein an input terminal of each first switch circuit is configured to receive an input signal, an output terminal of each first switch circuit is connected with an output terminal of the multi-channel multiplexing circuit, and an output terminal of the multi-channel multiplexing circuit is used for connecting with an input terminal of the ADC circuit; wherein each first switching circuit comprises the switching circuit. According to the present disclosure, the circuit area can be reduced, and the influence of the ESD resistance on the signal transmission of the switch circuit can be reduced.

Description

Switch circuit, multichannel sampling control circuit, analog-to-digital conversion circuit and chip
Technical Field
The disclosure relates to the technical field of circuits, in particular to a switch circuit, a multi-channel sampling control circuit, an analog-to-digital conversion circuit and a chip.
Background
In a switching circuit such as an input channel of an Analog to Digital Converter (ADC), there is a problem of Electrostatic discharge (ESD). In the related art, an ESD device or an ESD resistor is used to solve the electrostatic discharge problem. However, the ESD device requires a large area, and the ESD resistance affects the accuracy of signal transmission of the switching circuit to some extent, and particularly, the influence of the ESD resistance is significant under a low voltage condition in a wide power domain.
Disclosure of Invention
In view of this, the embodiments of the present disclosure provide a switch circuit, a multi-channel sampling control circuit, an analog-to-digital conversion circuit and a chip, so as to at least reduce the influence of ESD resistance.
According to an aspect of the present disclosure, there is provided a switching circuit including: the ESD protection circuit comprises a plurality of switch branches connected in parallel, wherein each switch branch in the switch branches comprises an ESD resistor and a first switch module, and the ESD resistor and the first switch module are connected between the input end and the output end of the switch circuit in series.
According to another aspect of the present disclosure, there is provided a multi-channel sampling control circuit including: a multi-channel multiplexing circuit comprising a plurality of first switch circuits, wherein an input terminal of each first switch circuit in the plurality of first switch circuits is configured to receive an input signal, an output terminal of each first switch circuit is connected with an output terminal of the multi-channel multiplexing circuit, and an output terminal of the multi-channel multiplexing circuit is used for connecting with an input terminal of the ADC circuit; the first switch circuit is the switch circuit of the embodiment of the disclosure.
According to still another aspect of the present disclosure, there is provided an analog-to-digital conversion circuit including: the switch circuit of the embodiment of this disclosure, or the multichannel sampling control circuit of the embodiment of this disclosure.
According to still another aspect of the present disclosure, a chip is provided, which includes the switch circuit of the embodiment of the present disclosure, or the multi-channel sampling control circuit of the embodiment of the present disclosure.
According to still another aspect of the present disclosure, there is provided an electronic apparatus, comprising: the switching circuit of the embodiment of the present disclosure, the multi-channel sampling control circuit of the embodiment of the present disclosure, the analog-to-digital conversion circuit of the embodiment of the present disclosure, or the chip of the embodiment of the present disclosure.
According to one or more technical schemes provided in the embodiments of the present disclosure, the switch circuit includes a plurality of switch branches connected in parallel, each switch branch includes an ESD resistor and a switch module connected in series, and when the ESD resistor is used, the equivalent resistance of the switch circuit is small, the accuracy of signal transmission of the switch circuit can be improved, and the circuit area can be smaller compared with the circuit area using an ESD device.
Drawings
Further details, features and advantages of the disclosure are disclosed in the following description of exemplary embodiments, taken in conjunction with the accompanying drawings, in which:
FIG. 1 shows a schematic block diagram of a switching circuit of an exemplary embodiment of the present disclosure;
FIG. 2 illustrates a schematic structural diagram of a switch module of a dynamic substrate MOS field effect transistor of an exemplary embodiment of the present disclosure;
FIG. 3 illustrates a schematic structural diagram of a switch module of a dynamic substrate PMOS field effect transistor of an exemplary embodiment of the present disclosure;
FIG. 4 illustrates a schematic structural diagram of a switch module of an NMOS field effect transistor of a dynamic substrate of an exemplary embodiment of the present disclosure;
FIG. 5 shows a schematic structural diagram of a switch module of a CMOS transmission gate of a dynamic substrate of an exemplary embodiment of the present disclosure;
FIG. 6 shows a schematic diagram of a pull-down circuit of an exemplary embodiment of the present disclosure;
FIG. 7 shows a schematic diagram of a multi-channel sampling control circuit of an exemplary embodiment of the present disclosure;
FIG. 8 shows another schematic diagram of a multi-channel sampling control circuit according to an exemplary embodiment of the present disclosure; and
fig. 9 shows a structural schematic diagram of a multi-channel sar adc according to an exemplary embodiment of the present disclosure.
Detailed Description
Embodiments of the present disclosure will be described in more detail below with reference to the accompanying drawings. While certain embodiments of the present disclosure are shown in the drawings, it is to be understood that the present disclosure may be embodied in various forms and should not be construed as limited to the embodiments set forth herein, but rather are provided for a more thorough and complete understanding of the present disclosure. It should be understood that the drawings and embodiments of the disclosure are for illustration purposes only and are not intended to limit the scope of the disclosure.
It should be understood that the various steps recited in the method embodiments of the present disclosure may be performed in a different order, and/or performed in parallel. Moreover, method embodiments may include additional steps and/or omit performing the illustrated steps. The scope of the present disclosure is not limited in this respect.
The term "include" and variations thereof as used herein are open-ended, i.e., "including but not limited to". The term "based on" is "based, at least in part, on". The term "one embodiment" means "at least one embodiment"; the term "another embodiment" means "at least one additional embodiment"; the term "some embodiments" means "at least some embodiments". Relevant definitions for other terms will be given in the following description. It should be noted that the terms "first", "second", and the like in the present disclosure are only used for distinguishing different devices, modules or units, and are not used for limiting the order or interdependence relationship of the functions performed by the devices, modules or units.
It is noted that references to "a", "an", and "the" modifications in this disclosure are intended to be illustrative rather than limiting, and that those skilled in the art will recognize that "one or more" may be used unless the context clearly dictates otherwise.
The disclosed exemplary embodiments provide a switching circuit including a plurality of switching legs connected in parallel, each of the plurality of switching legs including an ESD resistance and a switching module, the ESD resistance and the switching module being connected in series between an input and an output of the switching circuit. Under the condition of using the ESD resistor, the equivalent resistance of the switch circuit is smaller, the signal transmission precision of the switch circuit can be improved, and the circuit area can be smaller compared with the circuit area using an ESD device.
Fig. 1 illustrates a schematic structural diagram of a switching circuit according to an exemplary embodiment of the present disclosure, and referring to fig. 1, the switching circuit 100 includes: an input terminal 101, an output terminal 102, and switching legs 110-1 to 110-n connected in parallel. It should be understood that any number of switching legs may be included in the present embodiment, and the number of switching legs is not limited in the present embodiment.
The input 101 may be configured to receive an input signal (e.g., an analog input signal) and the output 102 may be configured to output a corresponding input signal. Each of the switching legs 110-1 to 110-n comprises an ESD resistance 111 and a switching module 112, the ESD resistance 111 and the switching module 112 of each switching leg being connected in series between the input terminal 101 and the output terminal 102 of the switching circuit 100. The switch circuit 100 has a small equivalent resistance between the input terminal 101 and the output terminal 102, so that the influence of the ESD resistance in the low-voltage condition in the wide power domain can be at least reduced, and each switch branch can be protected by the ESD resistance.
In some embodiments, the control terminal of each switch module 112 is configured to receive a control signal, wherein the switch modules in the plurality of switch branches are turned on or off together under the driving of the control signal. In one embodiment, the control signal is simultaneously provided to the switch modules 112 of the switch branches 110-1 to 110-n, and when the control signal is of a first electrical characteristic (e.g., high level), the switch modules 112 of the switch branches 110-1 to 110-n are turned on together, and when the control signal is of a second electrical characteristic (e.g., low level), the switch modules 112 of the switch branches 110-1 to 110-n are turned off together.
For one embodiment, the switch module 112 may include one or more MOS field effect transistors. The gate of the MOS field effect transistor is configured to receive a control signal, and the MOS field effect transistor is gated or switched off under the driving of the control signal.
As an example, the switch module 112 may be a PMOS field effect transistor, a source (or drain) of which is connected in series with the ESD resistor 111, and a drain (or source) of which is connected to the output terminal 102 of the switch circuit 100. The gate of the PMOS field effect transistor is configured to receive a control signal, the PMOS field effect transistor is turned on when the control signal is at a low level, and the PMOS field effect transistor is turned off when the control signal is at a high level.
As another example, the switch module 112 may be an NMOS field effect transistor, a source (or drain) of which is connected in series with the ESD resistor 111, and a drain (or source) of which is connected with the output terminal 102 of the switch circuit 100. The gate of the NMOS field effect transistor is configured to receive a control signal, the NMOS field effect transistor is turned on when the control signal is high, and the NMOS field effect transistor is turned off when the control signal is low.
As another embodiment, the switch module 112 may be a CMOS transmission gate, for example, a CMOS transmission gate in which a PMOS field effect transistor and an NMOS field effect transistor are connected in parallel, and the sources and drains of the PMOS field effect transistor and the NMOS field effect transistor are connected to each other. The control signals include a pair of complementary control signals (which may be denoted as C and C)、) When one control signal (C) is high, the other control signal (C) is high、) Is low, whereas one control signal (C) is low and the other control signal (C) is low、) Is high. The grid electrode of the PMOS field effect transistor is configured to receive one control signal of the complementary control signals, and the grid electrode of the NMOS field effect transistor is configured to receive the other control signal of the complementary control signals. When the control signal of the grid of the PMOS field effect transistor is at a low level, the control signal of the grid of the NMOS field effect transistor is at a high level, and the PMOS field effect transistor and the NMOS field effect transistor are gated at the moment; when the control signal of the grid of the PMOS field effect transistor is at a high level, the control signal of the grid of the NMOS field effect transistor is at a low level, and at the moment, the PMOS field effect transistor and the NMOS field effect transistor are turned off.
In some embodiments, to reduce the on-resistance of the switch module 112, a non-biased MOS field effect transistor or CMOS transmission gate may be used. Although the unlined biased MOS field effect transistor or CMOS transfer gate has a small on-resistance, there may be a problem of leakage. Further, in some embodiments, a dynamic substrate approach may be used to reduce the leakage problem.
The dynamic substrate approach is exemplarily described below.
As an embodiment, the switch module 112 may include one or more MOS field effect transistors, wherein, when the MOS field effect transistor is turned on, the substrate terminal of the MOS field effect transistor is connected to the output terminal 102 (whose potential is expressed as VI) of the switch circuit 100, so that the voltage at the substrate terminal follows VI to form a non-substrate bias form; when the MOS field effect transistor is turned off, the substrate end of the MOS field effect transistor is connected with the preset power supply node, so that the MOS field effect transistor has larger resistance to reduce the problem of electric leakage.
As an embodiment, as shown in fig. 2, a switch is connected to the substrate terminal of each MOS field effect transistor, wherein the switch S1 is connected between the substrate terminal of the MOS field effect transistor and the output terminal 102 (the voltage of the output terminal 102 is denoted as VI) of the switch circuit 100; and a switch S2 connected between the substrate terminal of the MOS FET and a predetermined power supply node (e.g., VDD/GND). When the corresponding switch module 112 is turned on, the switch S2 is turned off and the switch S1 is turned on to connect the substrate terminal of the MOS field effect transistor to the output terminal 102 of the switch circuit 100; when the switching module 112 is turned off, the switch S1 is turned off, and the switch S2 is turned on to connect the substrate terminal of the MOS field effect transistor to the preset power supply node.
In one embodiment, control signals are provided to both switch module 112 and switch S1 such that when switch module 112 is gated, switch S1 is also gated. As an example, the control signal is provided to the switch module 112 and the switch S1 simultaneously, and when the control signal is of the first electrical characteristic (e.g., high level), the switch module 112 and the switch S1 are turned on simultaneously, forming a linerless form, so that when the switch circuit 100 transmits the input signal, the on-resistance thereof is small.
In another embodiment, one control signal is provided to the switch module 112 and the other control signal is provided to the switch S1, and the electrical characteristics of the two control signals are adapted so that when the switch module 112 is turned on, the switch S1 is also turned on.
As an example, as shown in fig. 3, the switch module 112 may be a PMOS field effect transistor, and the switch S1 is connected between the substrate terminal of the PMOS field effect transistor and the output terminal 102 of the switch circuit 100; switch S2 is connected between the substrate terminal of the PMOS field effect transistor and VDD. When the PMOS field effect transistor is turned on, the switch S2 is turned off, and the switch S1 is turned on to connect the substrate terminal of the PMOS field effect transistor to the output terminal 102 (whose potential is denoted as VI) of the switch circuit 100; when the PMOS field effect transistor is turned off, the switch S1 is turned off and the switch S2 is gated to connect the substrate terminal of the PMOS field effect transistor to VDD.
As another example, as shown in fig. 4, the switch module 112 may be an NMOS field effect transistor, and the switch S1 is connected between the substrate terminal of the NMOS field effect transistor and the output terminal 102 of the switch circuit 100; the switch S2 is connected between the substrate terminal of the NMOS field effect transistor and GND. When the NMOS field effect transistor is turned on, the switch S2 is turned off, and the switch S1 is turned on to connect the substrate terminal of the NMOS field effect transistor to the output terminal 102 of the switching circuit 100; when the NMOS field effect transistor is turned off, the switch S1 is turned off, and the switch S2 is turned on to connect the substrate terminal of the NMOS field effect transistor to GND.
As another embodiment, as shown in FIG. 5, the switch module 112 may include CMOS transmission gates, such as a CMOS transmission gate having a PMOS field effect transistor connected in parallel with an NMOS field effect transistor, when the CMOS transmission gate is turned on, the switches S1-1 and S1-2 are turned on, and the substrate terminals of the PMOS and NMOS field effect transistors are connected to the output terminal 102 (whose potential is denoted as VI) of the switch circuit 100 to form a non-biased form; when the CMOS transmission gate is turned off, the switches S2-1 and S2-2 are turned on, the substrate terminal of the PMOS field effect transistor is connected with a power supply node (such as VDD), and the substrate terminal of the NMOS field effect transistor is connected with another power supply node (such as GND), so that the CMOS transmission gate has larger resistance to reduce the problem of current leakage.
In some embodiments, as shown in fig. 6, the switching circuit 100 may further include a pull-down circuit 120. The pull-down circuit 120 is connected between the output terminal 102 of the switching circuit 100 and the load terminal. When the switch circuit 100 is turned on, the pull-down circuit 120 is turned off, and when the switch circuit 100 is turned off, the pull-down circuit 120 pulls the voltage of the output terminal 102 to a potential (e.g., GND) to prevent the voltage of the output terminal 102 from floating when the switch circuit 100 is turned off. As an embodiment, the pull-down circuit 120 includes a pull-down switch 121, and the pull-down switch 121 is connected between the output terminal 102 and GND. When the switching circuit 100 is turned on, the pull-down switch 121 is turned off, and when the switching circuit 100 is turned off, the pull-down switch 121 is turned on to pull the voltage of the output terminal 102 to GND.
It should be understood that each of the switching legs 110-1 through 110-n may employ the same ESD resistance or different ESD resistances. The switching legs of the switching legs 110-1 to 110-n may use the same switching module or may use different switching modules. This embodiment is not limited to this.
The disclosed exemplary embodiments provide a multi-channel sampling control circuit for receiving an analog input signal and transmitting the corresponding analog input signal to an ADC circuit, sampling the corresponding analog input signal by the ADC circuit and outputting a corresponding digital output signal, wherein the multi-channel sampling control circuit includes the switch circuit of the disclosed embodiments.
Fig. 7 shows a schematic structural diagram of a multi-channel sampling control circuit according to an exemplary embodiment of the present disclosure, and referring to fig. 7, the multi-channel sampling control circuit 200 includes: multichannel multiplexing circuit 210 includes first switching circuits 220-1 to 220-m, wherein an input of each of first switching circuits 220-1 to 220-m is configured to receive an input signal (e.g., an analog input signal), an output of each of the first switching circuits is connected to output 201 of multichannel multiplexing circuit 210, and output 201 of multichannel multiplexing circuit 210 is connected to an input of ADC circuit 300. It should be understood that the term "coupled" may mean either a direct electrical connection or an indirect electrical connection, and that, for example, an indirect electrical connection may include components or circuits coupled via amplifiers, filters, and the like.
Referring to fig. 7, each of the first switching circuits 220-1 to 220-m includes: switching legs 221-1 to 221-n connected in parallel, each switching leg may include: an ESD resistor 2211 and a switch module 2212, wherein the ESD resistor 2211 and the switch module 2212 are connected in series between the input and the output of the first switch circuit. In practical application, 2 or more switching branches can be arranged, the more switching branches are connected in parallel, the smaller the equivalent resistance of the first switching circuit is, and meanwhile, the area of the circuit is correspondingly increased. It should be appreciated that each of the switching legs 221-1 through 221-n may employ the same ESD resistance or may employ different ESD resistances. The switching legs of the switching legs 221-1 to 221-n may use the same switching module, or may use different switching modules. This embodiment is not limited to this.
In some embodiments, the control terminal of each switch module 2212 of the first switch circuit is configured to receive a control signal, wherein the switch modules 2212 of each first switch circuit are turned on or off together under the driving of the control signal. In one embodiment, the control signals are from a multi-channel configuration that defines selected first switch circuits through which corresponding input signals are transmitted to the ADC circuit 300. In one embodiment, when the control signal is of a first electrical characteristic (e.g., high), the switch module 2212 is gated; when the control signal is of a second electrical characteristic (e.g., low), the switch module 2212 is turned on.
As an embodiment, the switch module 2212 of the first switch circuit may include one or more MOS field effect transistors.
As an example, the switch module 2212 is a PMOS field effect transistor, the gate of which is configured to receive the control signal, the PMOS field effect transistor being turned on when the control signal is low, and the PMOS field effect transistor being turned off when the control signal is high.
As another example, the switch module 2212 is an NMOS field effect transistor, the gate of which is configured to receive a control signal, the NMOS field effect transistor being turned on when the control signal is high, and the NMOS field effect transistor being turned off when the control signal is low.
As another example, the switch module 2212 of the first switch circuit may be a CMOS transmission gate, such as a CMOS with PMOS field effect transistors connected in parallel with NMOS field effect transistors. As an example, the gates of the PMOS and NMOS field effect transistors are configured to receive control signals, which are a pair of complementary control signals (which may be denoted as C and C)、) When one control signal (C) is high, the other control signal (C) is high、) Is low. When the control signal corresponding to the PMOS field effect transistor is in a low level, the PMOS field effect transistor is gated, and at the moment, the control signal corresponding to the NMOS field effect transistor is in a high level, the NMOS field effect transistor is gated, so that the CMOS transmission gate is gated. On the contrary, when the control signal corresponding to the PMOS field effect transistor is at a high level, the PMOS field effect transistor is turned off, and at this time, the control signal corresponding to the NMOS field effect transistor is at a low level, the NMOS field effect transistor is turned off, so that the CMOS transmission gate is turned off.
To reduce the on-resistance of the switch module 2212, a non-biased MOS field effect transistor or CMOS transmission gate may be used. However, the unbiased MOS field effect transistor or CMOS transmission gate may cause channel leakage of the multi-channel multiplexing circuit 210, thereby affecting the sampling accuracy. For example, while one channel is gated, other channels may leak current, thereby affecting signal transmission of the gated channel. Therefore, in some embodiments, a dynamic substrate approach may be used to reduce the leakage problem.
The dynamic substrate approach is exemplified below.
As an embodiment, the switch module 2212 of the first switch circuit may include one or more MOS field effect transistors. When each MOS field effect transistor is gated, the substrate end of the MOS field effect transistor is connected with the output end (the potential of the MOS field effect transistor can be represented as VI) of the first switch circuit to form a lining-bias-free form, so that the on-resistance of the MOS field effect transistor is smaller; when the MOS field effect transistor is turned off, the substrate end of the MOS field effect transistor is connected with the preset power supply node, so that the resistance of the MOS field effect transistor is larger, and the problem of electric leakage possibly existing in the corresponding first switch circuit is solved. For the MOS field effect transistor, reference may be made to fig. 2 and the description thereof in the present disclosure, which are not described in detail in this embodiment.
As an example, the switch module 2212 is a PMOS field effect transistor, and when the PMOS field effect transistor is turned on, the substrate terminal of the PMOS field effect transistor is connected to the output terminal of the first switch circuit, and when the PMOS field effect transistor is turned off, the substrate terminal of the PMOS field effect transistor is connected to a power supply node (e.g., VDD). For the switch module 2212 of the PMOS fet, reference may be made to fig. 3 and the description thereof in the present disclosure, which will not be described in detail in this embodiment.
As another example, the switch module 2212 is an NMOS field effect transistor, and when the NMOS field effect transistor is turned on, a substrate end of the NMOS field effect transistor is connected to an output terminal of the first switch circuit, and when the NMOS field effect transistor is turned off, a substrate end of the NMOS field effect transistor is connected to another power supply node (e.g., GND). For the switch module 2212 of the NMOS fet, reference may be made to fig. 4 and its description in the present disclosure, which is not described in detail in this embodiment.
As another embodiment, the switch module 2212 of the first switch circuit may be a CMOS transmission gate, for example, a CMOS transmission gate in which a PMOS field effect transistor and an NMOS field effect transistor are connected in parallel, and when the CMOS transmission gate is gated, the substrate ends of the PMOS field effect transistor and the NMOS field effect transistor are connected to the output end of the first switch circuit to form a substrate-bias-free form; when the CMOS transmission gate is turned off, the substrate end of the PMOS field effect transistor is connected with one power supply node (such as VDD), and the substrate end of the NMOS field effect transistor is connected with the other power supply node (such as GND). The switch module 2212 of the CMOS transmission gate can refer to fig. 5 and the description thereof in the present disclosure, which are not described in detail in this embodiment.
In some embodiments, referring to fig. 8, the multi-channel sampling control circuit 200 further comprises: second switch circuits 230-1 to 230-m, wherein each of the second switch circuits 230-1 to 230-m is connected between an output of a respective first switch circuit (220-1 to 220-m) and an output 201 of the multi-channel multiplexing circuit 210.
Each of the second switching circuits 230-1 to 230-m is configured to transmit a corresponding input signal to the output terminal 201 of the multichannel multiplexing circuit 210 during a sampling phase of the ADC circuit 300 when the corresponding first switching circuit is gated. As an example, when the first switch circuit 220-1 is turned on, the corresponding second switch circuit 230-1 is turned on during the sampling phase of the ADC circuit 300, and the input signal transmitted through the first switch circuit 220-1 is transmitted to the output terminal 201 of the multi-channel multiplexing circuit 210 through the second switch circuit 230-1, and then enters the ADC circuit 300, and the ADC circuit 300 samples the input signal. During the conversion phase of the ADC circuit 300, a corresponding digital output signal is generated by the ADC circuit 300.
In some embodiments, each of the second switching circuits 230-1 to 230-m may include a switching module of an embodiment of the present disclosure. It should be understood that each of the second switch circuits 230-1 to 230-m may use the same switch module, or may use different switch modules, which is not limited in this embodiment.
As an embodiment, each of the second switching circuits 230-1 to 230-m may include one or more MOS field effect transistors, wherein, when the MOS field effect transistor is turned on, a substrate end of the MOS field effect transistor is connected with an output end of the second switching circuit to form a substrate-less bias form; when the MOS field effect transistor is turned off, the substrate terminal of the MOS field effect transistor is connected to the power supply node. Reference is made to the aforementioned fig. 2 of the present disclosure, which is not described herein again.
As an example, each of the second switching circuits 230-1 to 230-m includes a PMOS field effect transistor, a substrate terminal of which is connected to an output terminal of the second switching circuit when the PMOS field effect transistor is turned on, and a substrate terminal of which is connected to a power supply node (e.g., VDD) when the PMOS field effect transistor is turned off. Reference is made to the aforementioned fig. 3 of the present disclosure, which is not described herein again.
As another example, the second switch circuit includes an NMOS field-effect transistor, and a substrate terminal of the NMOS field-effect transistor is connected to the output terminal of the second switch circuit when the NMOS field-effect transistor is turned on, and the substrate terminal of the NMOS field-effect transistor is connected to the power supply node (e.g., GND) when the NMOS field-effect transistor is turned off. Reference may be made to fig. 4 of the present disclosure, which is not described herein again.
As another embodiment, each of the second switching circuits 230-1 to 230-m may include: a CMOS transmission gate, for example, a CMOS transmission gate in which a PMOS field effect transistor and an NMOS field effect transistor are connected in parallel, when the CMOS transmission gate is gated, the substrate end of the PMOS field effect transistor is connected to the output end of the second switch circuit, and the substrate end of the NMOS field effect transistor is connected to the input end of the second switch circuit (i.e., the output end of the first switch circuit, whose voltage is denoted by VI), so as to form a lining-bias-free form; when the CMOS transmission gate is turned off, the substrate end of the PMOS field effect transistor is connected with VDD, and the substrate end of the NMOS field effect transistor is connected with GND, so that the influence caused by asynchronous switching between the substrate end and the CMOS transmission gate can be reduced. As previously described with reference to fig. 5 of the present disclosure, the difference is that the substrate terminal of the NMOS field effect transistor is connected to the input terminal of the second switch circuit (i.e., the output terminal of the first switch circuit, whose voltage is denoted as VI), and the substrate terminal of the PMOS field effect transistor is connected to the output terminal of the second switch circuit.
In some embodiments, referring to FIG. 8, the output 201 of the multi-channel multiplexing circuit 210 includes: a first output 2011 and a second output 2012.
As an example, the first output 2011 may correspond to the positive (+) terminal of the ADC circuit 300 and the second output 2012 may correspond to the negative (-) terminal of the ADC circuit 300.
In some embodiments, as shown with reference to fig. 8, each of the second switching circuits 230-1 to 230-m may include: the switch module 231 is connected between the output end of the corresponding first switch circuit and the first output end 2011 of the multi-channel multiplexing circuit 210; the switch module 232 is connected between the output terminal of the corresponding first switch circuit and the second output terminal 2012 of the multi-channel multiplexing circuit 210.
In some embodiments, when the switching module 231 is gated, the switching module 232 is turned off to deliver the corresponding input signal to the first output 2011 of the multi-channel multiplexing circuit 210; when the switching module 232 is gated, the switching module 231 is turned off to transmit the corresponding input signal to the second output terminal 2012 of the multichannel multiplexing circuit 210.
As an embodiment, the switch module 231 and/or the switch module 232 may include: a CMOS transmission gate, for example, a CMOS transmission gate in which a PMOS field effect transistor and an NMOS field effect transistor are connected in parallel, when the CMOS transmission gate is gated, the substrate end of the PMOS field effect transistor is connected to the output end of the second switch circuit, and the substrate end of the NMOS field effect transistor is connected to the input end of the second switch circuit (i.e., the output end of the first switch circuit, whose voltage is denoted by VI), so as to form a lining-bias-free form; when the CMOS transmission gate is turned off, the substrate end of the PMOS field effect transistor is connected with VDD, and the substrate end of the NMOS field effect transistor is connected with GND, so that the influence caused by asynchronous switching between the substrate end and the CMOS transmission gate can be reduced. As previously described with reference to fig. 5 of the present disclosure, the difference is that the substrate terminal of the NMOS field effect transistor is connected to the input terminal of the second switch circuit (i.e., the output terminal of the first switch circuit, whose voltage is denoted as VI), and the substrate terminal of the PMOS field effect transistor is connected to the output terminal of the second switch circuit.
As an embodiment, the multi-channel multiplexing circuit 210 is configured to receive and output two-way signals through two channels. Wherein a first switch circuit (e.g., 220-1) receives a first input signal, the first input signal is transmitted to a corresponding second switch circuit (e.g., 230-1), the switch module 231 of the second switch circuit is turned on, and the switch module 232 is turned off, so as to transmit the first input signal to the first output 2011 of the multi-channel multiplexing circuit 210. Another first switching circuit (e.g., 220-n) receives the second input signal, which is transmitted to a corresponding second switching circuit (e.g., 230-n), whose switching module 232 is turned on while the switching module 231 is turned off, thereby transmitting the second input signal to the second output 2012 of the multi-channel multiplexing circuit 210. As an example, the first input signal and the second input signal correspond to a pseudo-differential signal or a fully-differential signal. As another example, the first input signal and the second input signal are fully differential signals into which the single-ended input signal is converted.
As an embodiment, one (e.g., 220-m) of the first switch circuits 220-1 to 220-m of the multi-channel multiplexing circuit 210 is configured as a COM channel (Common Input), and the remaining first switch circuits are configured to receive an Input signal. As an example, a first switch circuit as a COM channel may be output to the first output 2011 (e.g., corresponding to the negative terminal of the ADC circuit 300) and the remaining first switch circuits may be output to the second output 2012 (e.g., corresponding to the positive terminal of the ADC circuit 300), but is not limited thereto.
In some embodiments, as shown with reference to FIG. 8, each of the first switching circuits 220-1 to 220-m may further include a pull-down circuit 240-1 to 240-m. Each of the pull-down circuits 240-1 to 240-m is connected to an output terminal of the first switching circuit. When the first switch circuit is turned on, the corresponding pull-down circuit is turned off, and when the first switch circuit is turned off, the corresponding pull-down circuit pulls the voltage of the output terminal (whose potential is represented as VI) of the first switch circuit to a potential (e.g., GND) so as to prevent the voltage of the output terminal of the first switch circuit from being in a floating state when the first switch circuit is turned off. As an embodiment, each pull-down circuit includes a pull-down switch 241, and the pull-down switch 241 is connected between the output terminal of the first switch circuit and GND. When the first switching circuit is turned on, the corresponding pull-down switch 241 is turned off, and when the first switching circuit is turned off, the corresponding pull-down switch 241 is turned on to pull the voltage of the output terminal of the first switching circuit to GND.
The exemplary embodiments of the present disclosure also provide a multi-channel Successive Approximation-Approximation register (SAR) ADC to at least reduce the problems of excessive on-resistance and ESD resistance of a multi-channel sampling switch. The sar adc may be configured to process one or more types of input signals, e.g., single-ended input signals, fully differential input signals, pseudo-differential unipolar input signals, pseudo-differential bipolar input signals, differential inputs with wide input common mode. The multichannel SARADC can be suitable for wide power domains, is lower in circuit complexity and higher in reliability compared with a bootstrap mode, and meanwhile, the defect that the area of an ESD device is large due to the fact that an ESD resistor is adopted and the influence of the ESD resistor on sampling precision is avoided.
Fig. 9 illustrates a structural schematic diagram of a multi-channel sar adc according to an exemplary embodiment of the present disclosure, and referring to fig. 9, the multi-channel sar adc 400 includes: input channels CH 0-CH 3, multi-channel multiplexing circuit 410 and SAR ADC circuit 420. For one embodiment, the sar adc circuit 420 may be configured to control the multi-channel multiplexing circuit 410 to select a corresponding channel, and may sample and convert an input signal transmitted by the selected channel to output a corresponding digital output signal.
With continued reference to FIG. 9, the multi-channel multiplexing circuit 410 includes first switching circuits 411-0 through 411-3 corresponding to one of the input channels CH0 through CH3, respectively. The multi-channel multiplexing circuit 410 may include a first output terminal 412 and a second output terminal 413, the sar adc circuit 420 may include a first input terminal 421 and a second input terminal 422, the first output terminal 412 may be directly or indirectly connected to the first input terminal 421, and the second output terminal 412 may be directly or indirectly connected to the second input terminal 422. As an example, the first output terminal 412 may be configured as a positive (+) terminal of the multi-channel multiplexing circuit 410, and accordingly, the first input terminal 421 may be configured as a positive (+) terminal of the SAR ADC circuit 420; the second output 413 is configured as the negative (-) terminal of the multi-channel multiplexing circuit 410 and correspondingly the second input 422 is configured as the negative (-) terminal of the SRAADC circuit 420.
In some embodiments, an input channel may be selected among the input channels CH 0-CH 3 based on the channel configuration. As an embodiment, the channel configuration may be configured to select one of the input channels CH 0-CH 3 to receive and transmit the input signal. As another embodiment, the channel configuration may be configured to select two input channels among the input channels CH0 to CH3 to receive and transmit input signals, wherein the input signal received by one input channel is transmitted to the first input terminal 421 through the first output terminal 412, and the input signal received by the other input channel is transmitted to the second input terminal 422 through the second output terminal 413. In one embodiment, the control signals are generated based on the channel configuration, the control signals are provided to the first switch circuits 411-0 to 411-3, one channel of the control signals corresponding to the selected channel is set to a first electrical characteristic (e.g., high level), and the control signals corresponding to the unselected channels are set to a second electrical characteristic (e.g., low level).
In some embodiments, as shown with reference to FIG. 9, second switch circuits 415-0 to 415-3 may also be included, connected in series with the first switch circuits 411-0 to 411-3, respectively. Each of the second switch circuits 415-0 to 415-3 may include a switch module 4151 and a switch module 4152, the switch module 4151 having one end connected to the output terminal of the corresponding first switch circuit and the other end connected to the first output terminal 412 of the multiplexing circuit 410, and the switch module 4152 having one end connected to the output terminal of the corresponding first switch circuit and the other end connected to the second output terminal 413 of the multiplexing circuit 410. One of the switch module 4151 and the switch module 4152 of the corresponding second switch circuit is gated to transmit the input signal to the corresponding output terminal during the sampling phase of the SRAADC circuit 420 when the first switch circuit is gated, e.g., the switch module 4152 is turned off and the input signal of the path is transmitted to the first output terminal 412 when the switch module 4151 is gated; when the switching module 4152 is turned on, the switching module 4151 is turned off, and the input signal of the path is transmitted to the second output terminal 413.
In some embodiments, as shown with reference to fig. 9, each of the first switching circuits 411-0 to 411-3 may include a plurality of switching legs connected in parallel, each switching leg including: ESD resistance RESDAnd CMOS transmission gate TG1, RESDWas connected in series with TG 1.
As an implementation, TG1 uses a dynamic substrate approach to reduce on-resistance and reduce channel leakage problems. The substrate terminal of the TG1 is connectable to the output terminal of the first switch circuit (whose potential is denoted as VI) or the corresponding power supply node (VDD, GND) through control of a switch. Wherein the substrate terminal of the TG1 is connected to the output terminal (VI) of the first switch circuit by control of the switch when the first switch circuit is turned on; when the first switch circuit is turned off, the substrate terminal of TG1 is connected to the corresponding power supply node (VDD/GND) by control of the switch. The TG1 can be referred to the aforementioned fig. 5 and description of the present disclosure, and will not be described herein.
In some embodiments, referring to fig. 9, the switch module 4151 and the switch module 4152 of the second switch circuit are CMOS transmission gates TG2 and TG3, respectively.
As an implementation, TG2 and TG3 reduce on-resistance and reduce channel leakage problems in a dynamic substrate approach. The substrate terminals of the PMOS field effect transistors of TG2 and TG3 may be connected to the output terminals of the second switch circuit (whose potentials are represented as V1, V2) or the corresponding power supply node (e.g., VDD) by control of switches, and the substrate terminals of the NMOS field effect transistors of TG2 and TG3 may be connected to the output terminals of the first switch circuit (whose potentials are represented as VI) or the corresponding power supply node (e.g., GND) by control of switches. As previously described with reference to fig. 5 of the present disclosure, the difference is that the substrate terminal of the NMOS field effect transistor is connected to the input terminal of the second switch circuit (i.e., the output terminal of the first switch circuit, whose voltage is denoted as VI), and the substrate terminal of the PMOS field effect transistor is connected to the output terminal of the second switch circuit.
In some examples, as shown with reference to fig. 9, each of the first switch circuits 411-0 to 411-3 may include a pull-down circuit including a switch P connected between GND and the corresponding first switch circuit. When the first switching circuit is turned on, the corresponding switch P is turned off; when the first switch circuit is turned off, the corresponding switch P is turned on to connect the output terminal of the corresponding first switch circuit to GND.
An exemplary embodiment of the present disclosure also provides an analog-to-digital conversion circuit, which may include: the switch circuit of the embodiment of this disclosure, or the multichannel sampling control circuit of the embodiment of this disclosure.
The exemplary embodiment of the present disclosure also provides a chip, which may include the switch circuit of the embodiment of the present disclosure, or the multi-channel sampling control circuit of the embodiment of the present disclosure, or the analog-to-digital conversion circuit of the embodiment of the present disclosure.
Aspects of the present disclosure may be integrated into an electronic device selected from the group consisting of: a set-top box; an entertainment unit; a navigation device; a communication device; a fixed location data unit; a mobile location data unit; a Global Positioning System (GPS) device; a mobile phone; a cellular telephone; a smart phone; session Initiation Protocol (SIP) phones; a tablet computer; a tablet phone; a server; a computer; a portable computer; a mobile computing device; a wearable computing device; a desktop computer; personal Digital Assistants (PDAs); a monitor; a computer monitor; a television set; a tuner; a radio; satellite radio; a music player; a digital music player; a portable music player; a digital video player; a video player; digital Video Disc (DVD) players; a portable digital video player; a motor vehicle; a vehicle component; an avionics system; an unmanned aerial vehicle; and multi-rotor aircraft.
The above description is only exemplary of the present disclosure and should not be taken as limiting the disclosure, and any modifications, equivalents, and simple improvements made in the spirit of the present disclosure should be included in the scope of the present disclosure.

Claims (18)

1. A switching circuit, comprising: the ESD protection circuit comprises a plurality of switch branches connected in parallel, wherein each switch branch in the switch branches comprises an ESD resistor and a first switch module, and the ESD resistor and the first switch module are connected between the input end and the output end of the switch circuit in series.
2. The switching circuit of claim 1, wherein the control terminal of each first switching module is configured to receive a control signal, wherein the first switching modules in the plurality of switching legs are driven by the control signal to be turned on or off together.
3. The switching circuit according to claim 1 or 2, wherein the first switching module comprises: one or more first MOS field effect transistors, each of the one or more first MOS field effect transistors having a substrate terminal connected thereto:
a first switch connected between the substrate terminal of the first MOS field effect transistor and the output terminal;
and the second switch is connected between the substrate end of the first MOS field effect transistor and a preset power supply node.
4. The switching circuit of claim 3, wherein the second switch is turned off and the first switch is turned on to connect the substrate terminal of the first MOS field effect transistor to the output terminal of the switching circuit when the first switching module is turned on;
when the first switch module is turned off, the first switch is turned off, and the second switch is turned on to connect the substrate terminal of the first MOS field effect transistor to a preset power supply node.
5. The switch circuit of claim 3, wherein the one or more first MOS field effect transistors comprise one or more PMOS field effect transistors and/or one or more NMOS field effect transistors.
6. The switching circuit of claim 3, wherein the first switching module is a first CMOS transmission gate.
7. The switch circuit of claim 6, wherein the first CMOS transmission gate comprises a first PMOS field effect transistor and a first NMOS field effect transistor connected in parallel.
8. A multi-channel sampling control circuit, comprising:
a multi-channel multiplexing circuit comprising a plurality of first switch circuits, wherein an input of each first switch circuit of the plurality of first switch circuits is configured to receive an input signal, an output of each first switch circuit is connected with an output of the multi-channel multiplexing circuit, and an output of the multi-channel multiplexing circuit is used for connecting an input of an ADC circuit;
wherein the first switching circuit is a switching circuit as claimed in any one of claims 1 to 7.
9. The multi-channel sampling control circuit of claim 8, further comprising:
a plurality of second switch circuits, wherein each of the plurality of second switch circuits is connected between an output of a corresponding first switch circuit and an output of the multi-channel multiplexing circuit.
10. The multi-channel sampling control circuit of claim 9, wherein each of the plurality of second switch circuits is configured to pass a respective input signal to the output of the multi-channel multiplexing circuit during a sampling phase of the ADC circuit when the respective first switch circuit is gated.
11. The multi-channel sampling control circuit of claim 9 or 10, wherein the output of the multi-channel multiplexing circuit comprises: a first output terminal and a second output terminal.
12. The multi-channel sampling control circuit of claim 11, wherein each of the plurality of second switch circuits comprises:
the second switch module is connected between the output end of the corresponding first switch circuit and the first output end of the multichannel multiplexing circuit;
and the third switch module is connected between the output end of the corresponding first switch circuit and the second output end of the multichannel multiplexing circuit.
13. The multi-channel sampling control circuit of claim 12, wherein the second and/or third switch module comprises: one or more second MOS field effect transistors.
14. The multi-channel sampling control circuit of claim 12, wherein the second and/or third switch module comprises: a second CMOS transmission gate comprising a second PMOS field effect transistor and a second NMOS field effect transistor in parallel, wherein,
the substrate end of the second PMOS field effect transistor is connected with: a third switch connected between the substrate end of the second PMOS field effect transistor and the output end of the second switch circuit; the fourth switch is connected between the substrate end of the second PMOS field effect transistor and the first preset power supply node;
the substrate end of the second NMOS field effect transistor is connected with: the fifth switch is connected between the substrate end of the second NMOS field effect transistor and the output end of the corresponding first switch circuit; and the sixth switch is connected between the substrate end of the second NMOS field effect transistor and a second preset power supply node.
15. The multi-channel sampling control circuit of any one of claims 8 to 10, wherein at least one of the first switch circuits further comprises: a pull-down circuit configured to connect an output terminal of the first switching circuit to a preset potential when the first switching circuit is turned off.
16. An analog-to-digital conversion circuit, comprising: a switching circuit according to any one of claims 1 to 7, or a multi-channel sampling control circuit according to any one of claims 8 to 15.
17. A chip comprising a switching circuit according to any one of claims 1 to 7, or a multi-channel sampling control circuit according to any one of claims 8 to 15, or an analog-to-digital conversion circuit according to claim 16.
18. An electronic device, comprising: a switching circuit according to any one of claims 1 to 7, a multi-channel sampling control circuit according to any one of claims 8 to 15, an analogue-to-digital conversion circuit according to claim 16, or a chip according to claim 17.
CN202111666722.7A 2021-12-30 2021-12-30 Switch circuit, multichannel sampling control circuit, analog-to-digital conversion circuit and chip Pending CN114301458A (en)

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