CN117526913A - Multi-channel switch circuit and chip - Google Patents
Multi-channel switch circuit and chip Download PDFInfo
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- CN117526913A CN117526913A CN202311550732.3A CN202311550732A CN117526913A CN 117526913 A CN117526913 A CN 117526913A CN 202311550732 A CN202311550732 A CN 202311550732A CN 117526913 A CN117526913 A CN 117526913A
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- 238000002955 isolation Methods 0.000 claims abstract description 45
- 239000000758 substrate Substances 0.000 claims description 25
- 230000003071 parasitic effect Effects 0.000 description 4
- 101100112673 Rattus norvegicus Ccnd2 gene Proteins 0.000 description 3
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 239000000463 material Substances 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
Classifications
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
- H03K17/16—Modifications for eliminating interference voltages or currents
- H03K17/161—Modifications for eliminating interference voltages or currents in field-effect transistor switches
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
- H03K17/51—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used
- H03K17/56—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices
- H03K17/687—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices the devices being field-effect transistors
- H03K17/6871—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices the devices being field-effect transistors the output circuit comprising more than one controlled field-effect transistor
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
- H03K17/51—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used
- H03K17/56—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices
- H03K17/687—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices the devices being field-effect transistors
- H03K17/693—Switching arrangements with several input- or output-terminals, e.g. multiplexers, distributors
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- Electronic Switches (AREA)
Abstract
The invention discloses a multichannel switch circuit and a chip, wherein the switch circuit comprises: a plurality of switching units, switching isolation units and voltage follower units; the first end of at least one switch unit is connected with the second end of the switch isolation unit, the first end of the switch isolation unit is connected with the input voltage, the second end of the switch unit is used for generating output voltage and transmitting the output voltage to the input end of the voltage following unit, the output end of the voltage following unit generates a voltage signal which follows the input voltage or the change of the output voltage, and the output end of the voltage following unit is connected with the first end of the switch unit. According to the multi-channel switch circuit and the chip, the influence of the body diode leakage and the channel leakage of the switch units of other non-gating channels in the multi-channel switch circuit on the signal on the current gating channel is eliminated, the linearity of the input signal is improved, and the crosstalk between channels is reduced.
Description
Technical Field
The present invention relates to the field of integrated circuits, and more particularly, to a multi-channel switching circuit and a chip.
Background
In chips with multiple channels of input, a Multiplexer (MUX) is often required to switch input signals of different channels and transmit the signals to a later stage AFE module or an ADC module for processing.
Fig. 1 shows a common multi-channel switch gate circuit, in which each switch uses a CMOS switch structure to implement rail-to-rail (rail-to-rail) input signal range. When a channel is selected during normal operation, the CMOS switch corresponding to the channel is turned on, and the CMOS switches corresponding to all other channels are turned off.
Because the input voltages Vin1 and Vin2 of the channels have no magnitude relation, the voltage at the two ends of the source electrode and the drain electrode of each CMOS switch cannot be determined, in order to avoid electric leakage caused by forward conduction of the body diode, the substrate of the P-channel MOS tube in the CMOS switch can only be connected with the highest power supply voltage AVDD, and the substrate bulk of the N-channel MOS tube can only be connected with the lowest potential GND.
However, under high temperature conditions, reverse leakage from the substrate to the parasitic diode of the drain and source increases exponentially with temperature. Under the condition that a certain switch is on, the leakage current of the other switches which are turned off can flow into the gating channel, the leakage current is increased along with the increase of the channel number, and for the condition that the equivalent output impedance of the previous stage is larger, the leakage current flows through the equivalent resistor of the input end of the current gating channel, so that the error of the output voltage can be caused. This error is related to the magnitude of the input signal of the current gating channel and is therefore a nonlinear error that is difficult to eliminate by subsequent processing.
On the other hand, because the input signal range is rail-to-rail, when the input signal is close to the power supply voltage AVDD or close to GND, the corresponding CMOS switch cannot be completely turned off, and the channel leakage of the corresponding MOS transistor also flows into the current gating channel, so that an error is generated. This error is related to the input signal size of the other ungated channels and is therefore inter-channel crosstalk, which is also difficult to eliminate in subsequent processing.
The information disclosed in this background section is only for enhancement of understanding of the general background of the invention and should not be taken as an acknowledgement or any form of suggestion that this information forms the prior art already known to a person of ordinary skill in the art.
Disclosure of Invention
The invention aims to provide a multichannel switch circuit and a multichannel switch chip, which can eliminate nonlinear errors caused by multichannel switch parasitic diode leakage and channel crosstalk caused by channel leakage to the greatest extent and improve the precision.
To achieve the above object, an embodiment of the present invention provides a multi-channel switching circuit including: a plurality of switching units, switching isolation units and voltage follower units;
the first end of at least one switch unit is connected with the second end of the switch isolation unit, the first end of the switch isolation unit is connected with the input voltage, the second end of the switch unit is used for generating output voltage and transmitting the output voltage to the input end of the voltage following unit, the output end of the voltage following unit generates a voltage signal which follows the input voltage or the change of the output voltage, and the output end of the voltage following unit is connected with the first end of the switch unit.
In one or more embodiments of the present invention, the switching unit is composed of one or more MOS transistors, and a substrate of at least one of the MOS transistors is connected to an output terminal of the voltage follower unit to receive the voltage signal.
In one or more embodiments of the present invention, the switching unit includes a first MOS transistor and a second MOS transistor, a first end of the first MOS transistor and a first end of the second MOS transistor are connected to form a first end of the switching unit, and a second end of the first MOS transistor and a second end of the second MOS transistor are connected to form a second end of the switching unit.
In one or more embodiments of the present invention, the substrate of the first MOS transistor and/or the substrate of the second MOS transistor is connected to an output terminal of the voltage follower unit to receive the voltage signal.
In one or more embodiments of the present invention, at least two switch units are provided, at least two switch isolation units are provided, and a first end of each switch unit is connected to a second end of a corresponding switch isolation unit.
In one or more embodiments of the present invention, the first terminal of the switching unit is connected to the second terminal of the corresponding switching isolation unit and is simultaneously connected to the output terminal of the voltage follower unit through the switching module.
In one or more embodiments of the present invention, the first terminal of the voltage follower unit is connected to the second terminal of the switching unit or the first terminal of the voltage follower unit is connected to a plurality of input voltages through a switching selector.
In one or more embodiments of the present invention, the voltage follower units are provided in plurality, a first end of each of the voltage follower units is connected to a second end of a corresponding switch unit or a first end of each of the voltage follower units is connected to each of the input voltages, and each of the voltage follower units is configured to generate a corresponding voltage signal.
In one or more embodiments of the present invention, the switch isolation unit includes a CMOS switch, a P-channel MOS transistor, or an N-channel MOS transistor.
The invention also discloses a chip comprising the multi-channel switch circuit.
Compared with the prior art, the multi-channel switch circuit and the chip of the embodiment of the invention eliminate the influence of the body diode leakage and the channel leakage of the switch units of other ungate channels in the multi-channel switch circuit on the signal on the current gating channel, improve the linearity of the input signal and reduce the crosstalk between channels.
Drawings
Fig. 1 is a circuit schematic of a multi-channel switching circuit according to the prior art.
Fig. 2 is a circuit schematic of a multi-channel switching circuit according to an embodiment of the present invention.
Detailed Description
Specific embodiments of the invention will be described in detail below with reference to the drawings, but it should be understood that the scope of the invention is not limited to the specific embodiments.
Throughout the specification and claims, unless explicitly stated otherwise, the term "comprise" or variations thereof such as "comprises" or "comprising", etc. will be understood to include the stated element or component without excluding other elements or components.
The term "coupled" or "connected" in this specification includes both direct and indirect connections. An indirect connection is a connection made through an intermediary, such as an electrically conductive medium, which may have parasitic inductance or parasitic capacitance; indirect connections may also include connections through other active or passive devices, such as through circuits or components such as switches, follower circuits, and the like, that accomplish the same or similar functional objectives. Furthermore, in the present invention, terms such as "first," "second," and the like, are used primarily to distinguish one technical feature from another, and do not necessarily require or imply a certain actual relationship, number or order between the technical features.
As shown in fig. 2, a multi-channel switching circuit includes: a plurality of switching units for delivering or disconnecting the respective input voltages, a switching isolation unit, and a voltage follower unit 30.
The first end of at least one switch unit is connected with the second end of the switch isolation unit, the first end of the switch isolation unit is connected with the input voltage, the second end of the switch unit is used for generating output voltage, the output end of the voltage following unit 30 generates a voltage signal which follows the input voltage or changes of the output voltage, and the output end of the voltage following unit 30 is connected with the first end of the switch unit.
The number of the switching units, the switching isolation units and the voltage follower units 30 can be set as required.
Each switch unit is composed of one or more MOS tubes, and the substrate of at least one MOS tube is connected with the output end of the voltage following unit 30 to receive the voltage signal. If the switch unit is composed of one MOS tube, the MOS tube can be an N-channel MOS tube or a P-channel MOS tube, and the substrate of the MOS tube is connected with the output end Bulk of the voltage follower unit 30. The switch isolation unit also comprises one or more MOS (metal oxide semiconductor) tubes, wherein the MOS tubes can be N-channel MOS tubes or P-channel MOS tubes.
In other embodiments, the number of the switch isolation units may be equal to or less than the number of the switch units as required.
The following description will be given of an example in which two switching units are provided, and each switching unit is composed of two MOS transistors.
As shown in fig. 2, the two switching units are a first switching unit 11 and a second switching unit 12, respectively. The switch isolation units are correspondingly provided with two switch isolation units, namely a first switch isolation unit 21 and a second switch isolation unit 22. The voltage follower unit 30 is provided with one.
As shown in fig. 2, a first end of the first switching unit 11 is connected to a second end of the first switching isolation unit 21 and is simultaneously connected to an output terminal Bulk of the voltage follower unit 30 through the first switching module 41, and the first end of the first switching isolation unit 21 is configured to receive the first input voltage Vin1. The first end of the second switching unit 12 is connected to the second end of the second switching isolation unit 22 and is simultaneously connected to the output terminal Bulk of the voltage follower unit 30 through the second switching module 42, and the first end of the second switching isolation unit 22 is configured to receive the second input voltage Vin2. The first terminal of the voltage follower unit 30 is connected to the second terminal of the first switch unit 11 and the second terminal of the second switch unit 12.
The first switch module 41, the second switch module 42, and other switch modules may be formed by a single MOS transistor, or may be formed by two MOS transistors that form a CMOS switch. In other embodiments, the number of switch modules may be equal to or less than the number of switch units as desired.
Specifically, the first switch unit 11 includes a first MOS transistor M1 and a second MOS transistor M2, where the first MOS transistor M1 and the second MOS transistor M2 form a CMOS switch, a first end of the first MOS transistor M1 and a first end of the second MOS transistor M2 are connected to form a first end of the first switch unit 11, and a second end of the first MOS transistor M1 and a second end of the second MOS transistor M2 are connected to form a second end of the first switch unit 11.
The second switch unit 12 includes a third MOS transistor M3 and a fourth MOS transistor M4, where the third MOS transistor M3 and the fourth MOS transistor M4 form a CMOS switch, a first end of the third MOS transistor M3 and a first end of the fourth MOS transistor M4 are connected to form a first end of the second switch unit 12, and a second end of the third MOS transistor M3 and a second end of the fourth MOS transistor M4 are connected to form a second end of the second switch unit 12.
In an embodiment, the first MOS transistor M1 and the third MOS transistor M3 are N-channel MOS transistors, the first end of the first MOS transistor M1 and the first end of the third MOS transistor M3 are drain electrodes, the second end of the first MOS transistor M1 and the second end of the third MOS transistor M3 are source electrodes, and the control end of the first MOS transistor M1 and the control end of the third MOS transistor M3 are gate electrodes. The second MOS tube M2 and the fourth MOS tube M4 are P-channel MOS tubes, the first end of the second MOS tube M2 and the first end of the fourth MOS tube M4 are drain electrodes, the second end of the second MOS tube M2 and the second end of the fourth MOS tube M4 are source electrodes, and the control end of the second MOS tube M2 and the control end of the fourth MOS tube M4 are grid electrodes.
The substrate of the second MOS transistor M2 and the substrate of the fourth MOS transistor M4 are connected to the output terminal Bulk of the voltage follower unit 30 to receive the voltage signal, and the substrate of the first MOS transistor M1 and the substrate of the third MOS transistor M3 are connected to the ground voltage GND. In other embodiments, the substrate of the first MOS transistor M1 and the substrate of the third MOS transistor M3 may also be connected to the output terminal Bulk of the voltage follower unit 30; or the substrate of the second MOS tube M2 and the substrate of the fourth MOS tube M4 are connected with the power supply voltage AVDD, and the substrate of the first MOS tube M1 and the substrate of the third MOS tube M3 are also connected with the output end Bulk of the voltage following unit 30.
As shown in fig. 2, the first switch isolation unit 21 includes a fifth MOS transistor and a sixth MOS transistor, which form CMOS switches. The first end of the fifth MOS tube is connected with the second end of the sixth MOS tube to form the first end of the first switch isolation unit 21, and the second end of the fifth MOS tube is connected with the first end of the sixth MOS tube to form the second end of the first switch isolation unit 21. In other embodiments, the first end and the second end of the fifth MOS transistor may be interchanged, and the first end and the second end of the sixth MOS transistor may also be interchanged, so as to implement multiple different connection manners of the fifth MOS transistor and the sixth MOS transistor.
The second switch isolation unit 22 includes a seventh MOS transistor and an eighth MOS transistor, which constitute CMOS switches. The first end of the seventh MOS tube is connected with the second end of the eighth MOS tube to form the first end of the second switch isolation unit 22, and the second end of the seventh MOS tube is connected with the first end of the eighth MOS tube to form the second end of the second switch isolation unit 22. In other embodiments, the first end and the second end of the seventh MOS transistor may be interchanged, and the first end and the second end of the eighth MOS transistor may be interchanged, so as to implement a plurality of different connection manners of the seventh MOS transistor and the eighth MOS transistor.
In an embodiment, the fifth MOS transistor and the seventh MOS transistor are N-channel MOS transistors, the first end of the fifth MOS transistor and the first end of the seventh MOS transistor are drain electrodes, the second end of the fifth MOS transistor and the second end of the seventh MOS transistor are source electrodes, and the control end of the fifth MOS transistor and the control end of the seventh MOS transistor are gate electrodes. The sixth MOS tube and the eighth MOS tube are P-channel MOS tubes, the first end of the sixth MOS tube and the first end of the eighth MOS tube are drain electrodes, the second end of the sixth MOS tube and the second end of the eighth MOS tube are source electrodes, and the control end of the sixth MOS tube and the control end of the eighth MOS tube are grid electrodes.
In other embodiments, the first switch isolation unit 21 and the second switch isolation unit 22 may be composed of a single P-channel MOS transistor or a single N-channel MOS transistor.
As shown in fig. 2, the voltage follower unit 30 is a buffer composed of an amplifier, a first input end of which forms a first end of the voltage follower unit 30, and a second input end of which is connected to an output end of the amplifier to form an output end Bulk of the voltage follower unit 30. In other embodiments, the voltage follower unit 30 may be other circuits.
In other embodiments, the first end of the voltage follower unit 30 may be connected to a plurality of input voltages through a switch selector, so that when the switch isolation unit and the switch unit on a certain channel operate, the switch selector communicates the input voltage corresponding to the branch with the first end of the voltage follower unit 30; if the first switch unit 11 and the second switch isolation unit 21 are turned on, the switch selector switches to operate to communicate the first input voltage Vin1 with the first end of the voltage follower unit 30, so that the voltages at the two ends of the first switch unit 11 are equal.
In other embodiments, a plurality of voltage follower units 30 may be provided, each voltage follower unit 30 corresponds to one switch unit 11, and the first end of each voltage follower unit 30 may be directly connected to each input voltage, and each voltage follower unit 30 generates a corresponding voltage signal.
As shown in fig. 2, in an embodiment, the substrate of the switch isolation unit may still be selectively connected to the power supply voltage AVDD or the ground voltage GND to avoid forward bias of the body diode, and the substrates of the P-channel MOS transistors of the switch unit are all connected to the output terminal of the voltage follower unit 30, i.e. to a potential, so that the voltage difference between the substrate of the P-channel MOS transistor and the two ends of the body diode at the second end is close to 0V, thereby minimizing the leakage current of the body diode.
Meanwhile, the intermediate node of the series connection of the switch isolation unit and the switch unit on one channel is also connected to the output terminal Bulk of the voltage follower unit 30 through one switch module. The voltage signal at the output end of the voltage follower unit 30 is generated by a buffer with a unit gain, and the input of the buffer is the output voltage Vo of the current gating channel of the multi-channel switch circuit, so that the voltages at the first end and the second end of the switch unit are basically the same, the channel leakage current of the switch unit is reduced to the greatest extent, meanwhile, the output end Bulk of the buffer is a low-resistance node, and the channel leakage current of the switch isolation unit is absorbed by the low-resistance node.
For an ungated channel, the first end and the second end of the switch unit of the channel can follow the current output voltage Vo to change, so that the current channel leakage and substrate leakage of the gating channel can not occur, and the phenomenon of forward bias of the body diode can not occur; the leakage current of the switch isolation unit flows into the low-resistance node of the output end Bulk of the voltage follower unit 30, is absorbed by the low-resistance output of the buffer, and does not flow into the current gating channel, so that errors are not introduced.
In one embodiment, a low-resistance path is provided for the body diode leakage and the channel leakage of the switch unit through the low-resistance output of the buffer, so that each leakage is prevented from flowing into the current signal path, the influence of the body diode leakage and the channel leakage of the switch units of other channels in the multi-channel switch circuit on the signal of the current gating channel is eliminated, the linearity of the input signal is improved, and the inter-channel crosstalk is reduced.
The invention also discloses a chip comprising the multi-channel switch circuit.
The foregoing descriptions of specific exemplary embodiments of the present invention are presented for purposes of illustration and description. It is not intended to limit the invention to the precise form disclosed, and obviously many modifications and variations are possible in light of the above teachings or may be acquired from other forms, structures, arrangements, proportions, and with other components, materials and parts. The exemplary embodiments were chosen and described in order to explain the principles of the invention and its practical application to thereby enable others skilled in the art to make and utilize the invention in various exemplary embodiments and with various modifications as are suited to the particular use contemplated. It is intended that the scope of the invention be defined by the claims and their equivalents.
Claims (10)
1. A multi-channel switching circuit, comprising: a plurality of switching units, switching isolation units and voltage follower units;
the first end of at least one switch unit is connected with the second end of the switch isolation unit, the first end of the switch isolation unit is connected with the input voltage, the second end of the switch unit is used for generating output voltage and transmitting the output voltage to the input end of the voltage following unit, the output end of the voltage following unit generates a voltage signal which follows the input voltage or the change of the output voltage, and the output end of the voltage following unit is connected with the first end of the switch unit.
2. The multi-channel switching circuit of claim 1, wherein the switching unit is comprised of one or more MOS transistors, the substrate of at least one of the MOS transistors being coupled to the output of the voltage follower unit to receive the voltage signal.
3. The multi-channel switching circuit of claim 1, wherein the switching unit comprises a first MOS transistor and a second MOS transistor, the first end of the first MOS transistor and the first end of the second MOS transistor are connected to form a first end of the switching unit, and the second end of the first MOS transistor and the second end of the second MOS transistor are connected to form a second end of the switching unit.
4. A multi-channel switching circuit as claimed in claim 3, wherein the substrate of the first MOS transistor and/or the substrate of the second MOS transistor is connected to the output of the voltage follower unit for receiving the voltage signal.
5. The multi-channel switching circuit according to claim 1, wherein at least two switching units are provided, at least two switching isolation units are provided, and a first end of each switching unit is connected to a second end of a corresponding switching isolation unit.
6. A multi-channel switching circuit as claimed in claim 1 or 5, characterized in that the first terminal of the switching unit is connected to the second terminal of the corresponding switching isolation unit and is simultaneously connected to the output terminal of the voltage follower unit via a switching module.
7. The multi-channel switching circuit of claim 1, wherein the first terminal of the voltage follower unit is connected to the second terminal of the switching unit or the first terminal of the voltage follower unit is connected to a plurality of input voltages through a switching selector.
8. The multi-channel switching circuit according to claim 1, wherein a plurality of voltage follower units are provided, a first terminal of each of the voltage follower units being connected to a second terminal of a corresponding switching unit or a first terminal of each of the voltage follower units being connected to each of the input voltages, each of the voltage follower units being adapted to generate a corresponding voltage signal.
9. The multi-channel switching circuit of claim 1, wherein the switching isolation unit comprises a CMOS switch, a P-channel MOS transistor, or an N-channel MOS transistor.
10. A chip comprising a multi-channel switching circuit as claimed in any one of claims 1 to 9.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202311550732.3A CN117526913A (en) | 2023-11-20 | 2023-11-20 | Multi-channel switch circuit and chip |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202311550732.3A CN117526913A (en) | 2023-11-20 | 2023-11-20 | Multi-channel switch circuit and chip |
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| Publication Number | Publication Date |
|---|---|
| CN117526913A true CN117526913A (en) | 2024-02-06 |
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| Application Number | Title | Priority Date | Filing Date |
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| CN202311550732.3A Pending CN117526913A (en) | 2023-11-20 | 2023-11-20 | Multi-channel switch circuit and chip |
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| CN (1) | CN117526913A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN117811371A (en) * | 2024-02-28 | 2024-04-02 | 杰华特微电子股份有限公司 | Maximum input voltage selection output circuit, method and chip using same |
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2023
- 2023-11-20 CN CN202311550732.3A patent/CN117526913A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN117811371A (en) * | 2024-02-28 | 2024-04-02 | 杰华特微电子股份有限公司 | Maximum input voltage selection output circuit, method and chip using same |
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