CN103762969B - A kind of high-voltage side gate drive circuit of anti-noise jamming - Google Patents
A kind of high-voltage side gate drive circuit of anti-noise jamming Download PDFInfo
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Abstract
A kind of high-voltage side gate drive circuit of anti-noise jamming, including high-pressure level shift circuit, RS latch and driver, the two-way low voltage pulse signal of input is converted to the output of two-way high-voltage pulse signal by high-pressure level shift circuit, two-way high-voltage pulse signal enters RS latch respectively after treatment, the output of RS latch is to driver, and driver output drive signal controls the switch of external power pipe。High-pressure level shift circuit has been improved by the present invention, and the high-pressure level shift circuit after improvement comprises two identical independent sectors, and each independent part all includes two LDMOS pipes, one delay unit, one Zener stabilivolt, an electric capacity, a resistance and pressure PMOS in。The present invention can eliminate d<i>v</i>/ dt interference noise and differential mode noise, and while eliminating noise jamming, can not affect the transmission of normal signal, also increase the negative VS voltage of permission simultaneously。
Description
Technical field
The present invention relates to high-voltage power mos gate actuation techniques, particularly to the high pressure floating boom drive circuit of a kind of anti-noise jamming, belong to Analogous Integrated Electronic Circuits technical field。
Background technology
In power electronic chips a lot of currently on the market or integrated circuit driving chip system, all there is high-voltage grid drive circuit, this circuit adopt high voltage level shifting technique, it is achieved low pressure to the conversion of high pressure to drive high side power pipe。High-voltage grid drive circuit belongs to one of typical circuit of high voltage integrated circuit (HVIC)。This kind of HVIC has a wide range of applications in motor driving, flat pannel display and other consumer electronics field, it is all adopt HLV compatible IC technique, utilize high-voltage LDMOS device that low-voltage control signal is converted to high voltage control signal, thus driving high side circuitry to work, the system of general this kind of HVIC all adopts half-bridge topology。
Half-bridge driven chip is mainly used to drive the power tube of external half-bridge topological structure, internal drive circuit is divided into high-pressure side driving circuit and low-pressure side drive circuit according to the difference of working power voltage, along with opening of half-bridge topology power tube turns off output point voltage power supply in quick condition, therefore on high-tension side drive circuit voltage also should be operated in quick condition along with the change of output point voltage, and this function mainly can be realized by outside boostrap circuit。
High-voltage side gate drive circuit has high-pressure level shift circuit, the LDMOS pipe drain terminal of traditional high-pressure level shift circuit has bigger parasitic capacitance, owing to high side circuitry adopts floating power supply to power, so opening and shutting off of external power pipe can make VS node produce dv/dt interference noise, and be combined with floating power supply VB by bootstrap capacitor, make VB line also has dv/dt interference noise, plus the impact of LDMOS drain terminal parasitic capacitance in high-pressure level shift circuit, fast-changing voltage can form displacement current and parasitic capacitance is charged, this displacement current all causes very big voltage drop on two LDMOS drain terminal resistance of traditional level shift circuit, make the output signal of high-pressure level shift circuit with bigger common mode dv/dt interference noise, circuit also has the differential mode burst pulse noise that process deviation causes simultaneously。These noise jamming are all likely to cause drive circuit false triggering, thus causing the fault of system。
Summary of the invention
For the noise jamming problem existed in above-mentioned prior art, the present invention provides the high-voltage side gate drive circuit of a kind of anti-noise jamming, it is possible to eliminate dV/ dt interference noise and differential mode noise, and while eliminating noise jamming, can not affect the transmission of normal signal, also increase the negative VS voltage of permission simultaneously。
For achieving the above object, the technical solution used in the present invention is:
A kind of high-voltage side gate drive circuit of anti-noise jamming, including high-pressure level shift circuit, RS latch and driver, two-way low voltage pulse signal Vin1 and the Vin2 of input is converted to the output of two-way high-voltage pulse signal by high-pressure level shift circuit, two-way high-voltage pulse signal enters RS latch after processing respectively through two-way filter circuit, the output of RS latch is to driver, and driver output VOUT drives signal to control the switch of external power pipe；It is characterized in that: carried out high-pressure level shift circuit improving and substituting two-way filter circuit with two-way pulse shaper；
High-pressure level shift circuit after improvement comprises two identical independent sectors, each independent part all includes two LDMOS pipes, a delay unit, a Zener stabilivolt, one electric capacity, pressure PMOS in one resistance and one, wherein, LDMOS pipe MN1, MN2, first delay unit, Zener stabilivolt D1, electric capacity C1, middle pressure PMOS MP1 and resistance R1 constitute a part of the high-pressure level shift circuit after improving；LDMOS pipe MN3, MN4, the second delay unit, Zener stabilivolt D2, electric capacity C2, middle pressure PMOS MP2 and resistance R2 constitute the another one part of the high-pressure level shift circuit after improving；The input Von of the high-pressure level shift circuit after improvement connects the grid of LDMOS pipe MN1 and the input of the first delay unit, the source ground of LDMOS pipe MN1, the drain electrode of LDMOS pipe MN1 and the anode of Zener D1, one end of electric capacity C1 and the drain electrode of middle pressure PMOS MP1 links together and is connected to the input of a road pulse shaper as a road high-voltage pulse signal outfan, the negative electrode of Zener D1, the other end of electric capacity C1, the source electrode of middle pressure PMOS MP1 and one end of resistance R1 link together and are connected with floating voltage VB, the grid of LDMOS pipe MN2 connects the outfan of the first delay unit, the grid of middle pressure PMOS MP1 connects the other end of resistance R1 and the drain electrode of LDMOS pipe MN2, the source ground of LDMOS pipe MN2；Another input Voff of the high-pressure level shift circuit after improvement connects the grid of LDMOS pipe MN3 and the input of the second delay unit, the source ground of LDMOS pipe MN3, the drain electrode of LDMOS pipe MN3 and the anode of Zener D2, one end of electric capacity C2 and the drain electrode of middle pressure PMOS MP2 links together and is connected to the input of another road pulse shaper as another road high-voltage pulse signal outfan, the negative electrode of Zener D2, the other end of electric capacity C2, the source electrode of middle pressure PMOS MP2 and one end of resistance R2 link together and are connected with floating voltage VB, the grid of LDMOS pipe MN4 connects the outfan of the second delay unit, the grid of middle pressure PMOS MP2 connects the other end of resistance R2 and the drain electrode of LDMOS pipe MN4, the source ground of LDMOS pipe MN4。
Described first, the second two delay unit structures are identical, can adopt and be equipped with low pressure PMOS MPD1, MPD2, NMOS tube MND1, MND2, resistance RD1, RD2, electric capacity CD1, CD2 and Schmidt trigger SMTD1, the grid of PMOS MPD1 is connected with the grid of NMOS tube MND1, input input as delay unit, the drain electrode of the PMOS MPD1 drain electrode by resistance RD1 Yu NMOS tube MND1, the grid of one end of electric capacity CD1 and the grid of PMOS MPD2 and NMOS tube MND2 links together, one end of the drain electrode of PMOS MPD2 and resistance RD2, one end of electric capacity CD2 and the input of Schmidt trigger SMTD1 connect, the other end of resistance RD2 connects the drain electrode of NMOS tube MND2, the source electrode of NMOS tube MND2, the other end of electric capacity CD2 and the source electrode of NMOS tube MND1, the other end of electric capacity CD1 links together and is connected to the logically GND of chip with the ground end of Schmidt trigger SMTD1, PMOS MPD1, the power end of the source electrode of MPD2 and Schmidt trigger SMTD1 is connected to chip power VDD, the outfan output of Schmidt trigger SMTD1 is as the outfan of delay unit；
The structure of described two-way pulse shaper is identical, can adopt and be equipped with buffer stage Buffer, PMOS MPS1, MPS2, NMOS tube MNS1, MNS2, electric capacity CS1 and Schmidt trigger SMTS1, the two-way high-voltage pulse signal of the high-pressure level shift circuit after improvement exports respectively through connecting the grid of respective PMOS MPS1 and the grid of NMOS tube MNS1 after two-way buffer stage Buffer, the drain electrode of PMOS MPS1 is connected with the drain interconnection of NMOS tube MNS1 and with one end of electric capacity CS1 and the input of Schmidt trigger SMTS1, the outfan of Schmidt trigger SMTS1 connects the grid of PMOS MPS2 and the grid of NMOS tube MNS2, the source electrode of PMOS MPS1 and PMOS MPS2, the power end of buffer stage Buffer and the power end of Schmidt trigger SMTS1 are all connected with floating voltage VB, the source electrode of NMOS tube MNS1 and NMOS tube MNS2, the ground end of the other end of electric capacity CS1 and the ground end of buffer stage Buffer and Schmidt trigger SMTS1 is all connected with floating reference ground VS, the drain electrode of PMOS MPS2 and the drain interconnection of NMOS tube MNS2 the outfan as pulse shaper, the outfan of two-way pulse shaper exports set signal Vset and reset signal Vrst respectively to the S of RS latch, R input, the power end of RS latch connects floating power supply VB, the ground end of RS latch connects floating reference ground VS, the input of driver connects the outfan of RS latch, the outfan output signal VOUT of driver drives outside high side power pipe, the power end of driver connects floating power supply VB, the ground end of driver connects floating reference ground VS。
LDMOS pipe MN1, MN2 and PMOS MP1, MP2 in high-pressure level shift circuit after described improvement can substitute with high voltage bearing IGBT pipe respectively。
The present invention compared with prior art has the advantage that and remarkable result:
(1) can effectively eliminate the impact on circuit working state of common mode dv/dt interference noise and differential mode noise, not affect the transmission of normal signal simultaneously。Antimierophonic level shift circuit can eliminate the common mode dv/dt interference noise of various situation, differential mode noise is not mated by technique and causes, the pulsewidth of differential mode noise is only small, it is possible to be shaped in device arrange filtering link eliminate, thus differential mode noise is without the transmission affecting normal signal。
(2) the antimierophonic level shift circuit that the present invention proposes, can strengthen the negative VS voltage allowed。In common high-voltage side gate drive circuit, the output voltage signal of high-pressure level shift circuit be VB to ground COM the extent of supply within transfer, it is allowed to negative VS limits value come from the threshold voltage that after high-pressure level shift circuit, first order phase inverter is presetting。The output voltage signal of high-pressure level shift circuit is become shifting within VB to the VS extent of supply by the antimierophonic level shift circuit of the present invention, the negative VS voltage allowed no longer is controlled by the threshold level of rear class phase inverter, thus considerably increasing the ability worked under negative VS of circuit。
(3) power consumption can effectively be reduced。It is big or little that antimierophonic level shift circuit in the present invention can eliminate various amplitude, pulsewidth width or narrow common mode dv/dt interference noise, therefore can pass through to reduce the narrow pulse width of front stage circuits output, shorten the ON time of LDMOS pipe in high-pressure level shift circuit, thus effectively reducing power consumption。
Accompanying drawing explanation
Fig. 1 is the structure chart of traditional high-voltage side gate drive circuit；
Fig. 2 is that the present invention is a kind of can the structure chart of high-voltage side gate drive circuit of anti-noise jamming；
Fig. 3 is the circuit diagram of a part in two same sections of level shift circuit in the present invention；
Fig. 4 is one the implementing circuit figure of delay circuit in level shift circuit of the present invention；
Fig. 5 is an implementing circuit figure of pulse shaper of the present invention；
Fig. 6 illustrates the working waveform figure of level shift circuit of anti-dv/dt noise；
Fig. 7 is working waveform figure when not having a noise jamming in the present invention；
Fig. 8 is working waveform figure when having a noise jamming in the present invention；
Fig. 9 is the negative overshoot ability schematic diagram of VS of common high-voltage grid drive circuit；
Figure 10 be the present invention can the negative overshoot ability schematic diagram of VS of high-voltage side gate drive circuit of anti-noise jamming。
Detailed description of the invention
Such as Fig. 1, traditional high-voltage side gate drive circuit includes high-pressure level shift circuit 001, filter circuit 002, RS latch 003, driver 004。The two-way low voltage pulse signal of input is converted to high-voltage pulse signal output by high-pressure level shift circuit, RS latch is entered after this high-voltage pulse signal circuit after filtering, driver is received in the output of RS latch, and driver output OUT drives signal to control the switch of external power pipe。In order to reduce power consumption and improve the reliability of circuit, adopt the working method of two-way burst pulse to drive high voltage level shift circuit, and reduce narrow pulse width as far as possible to reduce power consumption under guaranteeing the premise driving the conducting of LDMOS pipe。Wherein high-pressure level shift circuit is mainly used to convert low voltage pulse signal to high-voltage pulse signal, Zener diode reversely pressure for 15-18V, Zener diode D3, Zener diode D4 they the maximum pressure drop on resistance R3, resistance R4 is limited in 15-18V, it is to avoid in high basin, mesolow metal-oxide-semiconductor grid oxygen punctures。The pulse signal of normal operation is reduced to the square-wave signal of fixed cycle by driver drives high-side switch tube by rest-set flip-flop。
Such as Fig. 2, the present invention can the high-voltage side gate drive circuit of anti-noise jamming, including the high-pressure level shift circuit 005,007 improved, two-way pulse shaper 008,009, RS latch 010, driver 011。The two-way low voltage pulse signal of input is converted to high-voltage pulse signal output by high-pressure level shift circuit, this high-voltage pulse signal enters RS latch after pulse shaper, driver is received in the output of RS latch, and driving stage circuit output VOUT drives signal to control the switch of external power pipe。
Improve high-pressure level shift circuit comprise two identical parts 005 and 007, wherein each independent part manage by two LDMOS, a delay unit, a Zener stabilivolt, an electric capacity, a resistance and in one press PMOS composition。I.e. LDMOS pipe MN1, MN2, the first delay unit 006, Zener stabilivolt D1, electric capacity C1, middle pressure PMOS MP1 and resistance R1 constitute a part 005 for level shift circuit；LDMOS pipe MN3, MN4, the second delay unit (structure is identical with the first delay unit 006, non-label in figure), Zener stabilivolt D2, electric capacity C2, middle pressure PMOS MP2 and resistance R2 constitutes the another part 007 of level shift circuit。Level shift circuit has two input Von and Voff, input Von to connect grid and first delay unit of LDMOS pipe MN1, and the output of the first delay unit is connected to the grid of LDMOS pipe MN2。The negative electrode of Zener D1, the lower end of electric capacity C1, middle pressure PMOS MP1 drain terminal be connected and be jointly connected to the drain electrode of LDMOS pipe MN1。The grid end of middle pressure PMOS is connected with the lower end of resistance R1 and is jointly connected to the drain electrode of LDMOS pipe MN2, and the source electrode of LDMOS pipe MN1, MN2 is all connected to ground。The anode of Zener D1, the upper end of electric capacity C1, the source of middle pressure PMOS MP1 and the upper end of resistance R1 are all connected to floating voltage VB。Equally, input Voff connects grid and second delay unit of LDMOS pipe MN3, and the output of the second delay unit is connected to the grid of LDMOS pipe MN4。The negative electrode of Zener D2, the lower end of electric capacity C2, middle pressure PMOS MP2 drain terminal be connected and be jointly connected to the drain electrode of LDMOS pipe MN3。The grid end of middle pressure PMOS is connected with the lower end of resistance R2 and is jointly connected to the drain electrode of LDMOS pipe MN3, and the source electrode of LDMOS pipe MN3, MN4 is all connected to ground。The anode of Zener D2, the upper end of electric capacity C2, the source of middle pressure PMOS MP2 and the upper end of resistance R2 are all connected to floating voltage VB。
The drain terminal of the LDMOS pipe MN1 in the input termination high-pressure level shift circuit of pulse shaper 008, the drain terminal of the LDMOS pipe MN3 in the input termination high-pressure level shift circuit of pulse shaper 009, the power end of reshaper is connected to floating power supply VB, and the ground of reshaper is connected to floating reference ground VS。Reshaper 008 is output as set signal Vset_ to the S input of RS latch 010, and the output of reshaper 009 connects as the reset signal Vrst_ R input to RS latch。The power end of RS latch is connected to the ground of floating power supply VB, RS latch and is connected to floating reference ground VS。
Driver 011 can be made up of chain of inverters, for providing enough current driving ability to drive opening and closedown of power tube。The input of driver device is connected to the outfan of RS latch, and the outfan output signal VOUT of driver drives outside high side power pipe。The power end of driver is connected to floating power supply VB, and the ground of driver is connected to floating reference ground VS。
Such as Fig. 3, for a part 005 for level shift circuit, the narrow pulse signal of two LDMOS pipe MN1, MN2 grids is delayed by unit increases time delay。Owing to pulse is processed by delay unit by designing different turn thresholds so that Von signal becomes the pulse signal V ' on that pulsewidth is narrower after delay unit, thus decreasing LDMOS ON time to reduce power consumption。The Zener D1 of the antimierophonic LDMOS drain terminal of energy can also be the form of multiple Zener series connection。
V ' on signal controls LDMOS pipe MN2 conducting, thus producing pressure drop on resistance R1, so that low pressure PMOS MP1 conducting。Now Von is already at low level, and LDMOS pipe MN1 ends。Discharge loop is provided for the electric capacity C1 that LDMOS pipe drain terminal is in parallel with Zener after low pressure PMOS MP1 conducting。The electric capacity C1 of LDMOS pipe drain terminal can be the electric capacity of artificial design, it is also possible to be the parasitic capacitance of the interpolar of certain device。
Such as Fig. 4, two delay unit structures are identical, can adopt and be equipped with low pressure PMOS MPD1, MPD2, NMOS tube MND1, MND2, resistance RD1, RD2, electric capacity CD1, CD2 and Schmidt trigger SMTD1, the grid of PMOS MPD1 is connected with the grid of NMOS tube MND1, input input as delay unit, the drain electrode of the PMOS MPD1 drain electrode by resistance RD1 Yu NMOS tube MND1, the grid of one end of electric capacity CD1 and the grid of PMOS MPD2 and NMOS tube MND2 links together, one end of the drain electrode of PMOS MPD2 and resistance RD2, one end of electric capacity CD2 and the input of Schmidt trigger SMTD1 connect, the other end of resistance RD2 connects the drain electrode of NMOS tube MND2, the source electrode of NMOS tube MND2, the other end of electric capacity CD2 and the source electrode of NMOS tube MND1, the other end of electric capacity CD1 links together and is connected to the logically GND of chip with the ground end of Schmidt trigger SMTD1, PMOS MPD1, the power end of the source electrode of MPD2 and Schmidt trigger SMTD1 is connected to chip power VDD, the outfan output of Schmidt trigger SMTD1 is as the outfan of delay unit。By designing MND1, MPD1, the breadth length ratio of MND2, MPD2 and the turn threshold of SMTD1, it is possible to the width that the pulse width after time delay is rushed is configured。Signal obtains output output from input input end reshaping after twice RC time delay network of delay unit, and pulse width has narrowed to reduce power consumption reality simultaneously delay function。
Such as Fig. 5, the input input_s of each road pulse shaper is linked into the grid of NMOS tube MNS1 and PMOS MPS1 after buffer stage Buffer, and the drain electrode of NMOS tube MNS1 and PMOS MPS1 is connected with the upper end of electric capacity CS1 and is jointly connected to the input of Schmidt trigger SMTS1。The lower end of electric capacity CS1 connects ginseng of floating with reference to ground VS。The outfan of Schmidt trigger SMTS1 is connected to the grid of NMOS tube MNS2 and PMOS MPS2, the connected outfan output_s as Shaping Module of leakage of NMOS tube MNS2 and MPS2。NMOS tube MNS1, MNS2 source electrode, the ground of Buffer, the ground of SMTS1 be all connected to high side floating reference ground VS on；PMOS MPS1, MPS2 source electrode, the power supply of Buffer, SMTS1 power supply be connected to high side floating power supply VB。The input waveform of Input, through shaping pulse, becomes desirable pulse at Output end。
Such as Fig. 6, it it is the working waveform figure of the level shift circuit of anti-dv/dt noise。When burst pulse Von arrives, pulse amplitude is that VDD is more than LDMOS pipe MN1 turn-on threshold voltage, LDMOS pipe MN1 turn-on threshold voltage。Owing to there is time delay first module, V ' on or low level, because face LDMOS pipe MN2 still turns off, now Zener D1 punctures, and the voltage at Zener two ends charges to electric capacity C1。Owing to charge circuit time constant is very little, the voltage at the two ends of electric capacity is charged to rapidly 15V。Namely, in Fig. 6, the trailing edge of the VC1 waveform that Von waveform rising edge is corresponding is very precipitous。When burst pulse Von becomes low level again from high level, electric capacity C1 is without discharge loop, and owing to the voltage at electric capacity two ends does not suddenly change, electric capacity both end voltage maintains 15V voltage。If now, the V ' after the time delay of the first delay unitonHigh level arrive, burst pulse amplitude be VDD more than LDMOS pipe MN2 turn-on threshold voltage, make LDMOS pipe MN2 turn on。Electric current forms pressure drop on resistance R1 makes terminal voltage under resistance R1 produce low voltage pulse, in Fig. 6 shown in VR1 waveform。Under resistance R1, terminal voltage generation low voltage pulse reaches the unlatching threshold value of PMOS MNP1, then low pressure PMOS MP1 opens thus providing a discharge loop for electric capacity C1, now electric capacity C1 is discharged by PMOS MP1 with constant current, the voltage linear of electric capacity C1 lower end rises, between the high period that V ' on waveform is corresponding in Fig. 6, shown in the linear rise of VC1 waveform。
Such as Fig. 7, it it is working waveform figure when not having a noise jamming in the present invention。Output waveform in conjunction with Fig. 6 level shift circuit analyzed。The present work wave signal by whole level shift circuit when not having noise jamming, burst pulse Von is after level shift circuit and reshaper, form the ideal pulse that edge is precipitous, the floating voltage VB-VS that supply voltage is high side due to reshaper, so the pulse Vset amplitude after reshaper processes is VB-VS, in Fig. 7 shown in VSET waveform。This pulse accesses the set end of RS latch；In like manner burst pulse Voff is after level shift circuit and reshaper, and forming the precipitous amplitude in edge is the ideal pulse of VB-VS, in Fig. 7 shown in VRESET waveform, accesses the reset terminal of RS latch。Through the latch effect of RS latch, Von and Voff two-way burst pulse being reduced into the wide pulse signal of correspondence, the amplitude of pulse is VB-VS。Obtaining amplitude after driver is VB-VS, and has the pulse of current driving ability, in Fig. 7 shown in the output waveform of Vout。
Such as Fig. 8, for working waveform figure when having a noise jamming in the present invention。When chip is normal, Von, V ' on, Voff, V ' off is low level, it is assumed that now owing to load changing makes floating reference VS current potential transition, form the dv/dt common-mode noise on VB under the effect of bootstrap capacitor, in Fig. 8, shown in the waveform of VB。As it is shown on figure 3, the dv/dt on high side power supply VB forms displacement current through the drain source capacitance of resistance R1 and LDMOS pipe MN2, this displacement current makes the current potential of resistance R1 lower end form downward noise negative pulse, in Fig. 8 shown in VR1 waveform。In like manner the dv/dt on high side power supply VB can form noise negative pulse through resistance R2 in the lower end of resistance R2。In Fig. 8 shown in VR2 waveform。Owing to the input signal of reshaper takes from the lower end of electric capacity C1 and C2, and the dv/dt noise on power supply VB will not produce noise pulse in the lower end of electric capacity C1 and C2, in Fig. 8 shown in Vc1 and Vc2 waveform。Owing to the protection of Vc1 and Vc2 waveform is constant, so the waveform accessing RS latch after reshaper also remains unchanged。Thus the set end of RS latch and reset terminal are all without by dV/dt effect of noise so that final output signal VOUT is not by due to the dv/dt common mode noise effects on VB, and namely output signal VOUT is without dV/dt effect of noise。The waveform of Vset, Vset, VOUT in Fig. 8。
As shown in Figure 9, VS negative voltage ability schematic diagram for common high-voltage grid drive circuit, Vin1 is the normal burst pulse input signal of high-pressure level shift circuit, Vd_1 node is relative to the normal output signal that the voltage waveform on ground is after tradition level shift circuit, this signal amplitude is to be affected by the supply voltage VB that high side is floating, and filter circuit is also operated under VB-VS supply voltage。In Fig. 9, dashed pulse is the pulse potential of Vd_1 node under normal circumstances, and the amplitude of this pulse potential is more than the turn threshold VT of filter circuit。This pulse under normal circumstances can by filter circuit identification the normal signal processed；The solid line pulse signal of Vd_1 node is the voltage signal at Vd_1 node place after VS adds negative voltage。Owing to VS is negative voltage, thus VB declines relative to the voltage on ground, causing that Vd_1 node place potential pulse amplitude relatively does not reach the threshold value VT of filter circuit below, filter circuit can not normally overturn and process input signal, ultimately results in export and drives signal normally。So, the VS negative voltage that conventional high-tension grid drive circuit allows is determined by the total threshold value VT of the upset of filter circuit。
As shown in Figure 10, for the present invention can the VS negative voltage overshoot ability schematic diagram of high-voltage side gate drive circuit of anti-noise jamming。When the input narrow pulse signal at Von node place is after the level shift circuit of antinoise pulse in this paper, the output signal swing after displacement is the breakdown voltage 15V of Zener, and namely the pulsion phase after level shift is 15V for the amplitude of VB。Generally arranging the floating power supply VB-VS of high side is 15V, so the pulse after level shift necessarily disclosure satisfy that the threshold V T of high side logic module, and namely the high-voltage side gate drive circuit of the present invention is capable of identification and the process of signal too under VS negative voltage。Therefore the negative overshoot ability of the VS of high-voltage side gate drive circuit in this paper is greatly improved。
The above; it it is only presently preferred embodiments of the present invention; not the present invention is imposed any restrictions, every any simple modification, change and equivalent structure transformation above example made according to the technology of the present invention essence, all still fall within the protection domain of technical solution of the present invention。
Claims (4)
1. the high-voltage side gate drive circuit of an anti-noise jamming, including high-pressure level shift circuit, RS latch and driver, two-way low voltage pulse signal Vin1 and the Vin2 of input is converted to the output of two-way high-voltage pulse signal by high-pressure level shift circuit, two-way high-voltage pulse signal enters RS latch after processing respectively through two-way filter circuit, the output of RS latch connects the input of driver, and driver output VOUT drives signal to control the switch of external power pipe；It is characterized in that: carried out high-pressure level shift circuit improving and substituting two-way filter circuit with two-way pulse shaper；
High-pressure level shift circuit after improvement comprises two identical independent sectors, each independent part all includes two LDMOS pipes, a delay unit, a Zener stabilivolt, one electric capacity, pressure PMOS in one resistance and one, wherein, LDMOS pipe MN1, MN2, first delay unit, Zener stabilivolt D1, electric capacity C1, middle pressure PMOS MP1 and resistance R1 constitute a part of the high-pressure level shift circuit after improving；LDMOS pipe MN3, MN4, the second delay unit, Zener stabilivolt D2, electric capacity C2, middle pressure PMOS MP2 and resistance R2 constitute the another one part of the high-pressure level shift circuit after improving；The input Von of the high-pressure level shift circuit after improvement connects the grid of LDMOS pipe MN1 and the input of the first delay unit, the source ground of LDMOS pipe MN1, the anode of the drain electrode of LDMOS pipe MN1 and Zener stabilivolt D1, one end of electric capacity C1 and the drain electrode of middle pressure PMOS MP1 links together and is connected to the input of a road pulse shaper as a road high-voltage pulse signal outfan, the negative electrode of Zener stabilivolt D1, the other end of electric capacity C1, the source electrode of middle pressure PMOS MP1 and one end of resistance R1 link together and are connected with floating voltage VB, the grid of LDMOS pipe MN2 connects the outfan of the first delay unit, the grid of middle pressure PMOS MP1 connects the other end of resistance R1 and the drain electrode of LDMOS pipe MN2, the source ground of LDMOS pipe MN2；Another input Voff of the high-pressure level shift circuit after improvement connects the grid of LDMOS pipe MN3 and the input of the second delay unit, the source ground of LDMOS pipe MN3, the anode of the drain electrode of LDMOS pipe MN3 and Zener stabilivolt D2, one end of electric capacity C2 and the drain electrode of middle pressure PMOS MP2 links together and is connected to the input of another road pulse shaper as another road high-voltage pulse signal outfan, the negative electrode of Zener stabilivolt D2, the other end of electric capacity C2, the source electrode of middle pressure PMOS MP2 and one end of resistance R2 link together and are connected with floating voltage VB, the grid of LDMOS pipe MN4 connects the outfan of the second delay unit, the grid of middle pressure PMOS MP2 connects the other end of resistance R2 and the drain electrode of LDMOS pipe MN4, the source ground of LDMOS pipe MN4。
2. the high-voltage side gate drive circuit of anti-noise jamming according to claim 1, it is characterized in that: described first, the second two delay unit structures are identical, it is equipped with low pressure PMOS MPD1, MPD2, NMOS tube MND1, MND2, resistance RD1, RD2, electric capacity CD1, CD2 and Schmidt trigger SMTD1, the grid of PMOS MPD1 is connected with the grid of NMOS tube MND1, input input as delay unit, the drain electrode of the PMOS MPD1 drain electrode by resistance RD1 Yu NMOS tube MND1, the grid of one end of electric capacity CD1 and the grid of PMOS MPD2 and NMOS tube MND2 links together, one end of the drain electrode of PMOS MPD2 and resistance RD2, one end of electric capacity CD2 and the input of Schmidt trigger SMTD1 connect, the other end of resistance RD2 connects the drain electrode of NMOS tube MND2, the source electrode of NMOS tube MND2, the other end of electric capacity CD2 and the source electrode of NMOS tube MND1, the other end of electric capacity CD1 links together and is connected to the logically GND of chip with the ground end of Schmidt trigger SMTD1, PMOS MPD1, the power end of the source electrode of MPD2 and Schmidt trigger SMTD1 is connected to chip power VDD, the outfan output of Schmidt trigger SMTD1 is as the outfan of delay unit。
3. the high-voltage side gate drive circuit of anti-noise jamming according to claim 1, it is characterized in that: the structure of described two-way pulse shaper is identical, it is equipped with buffer stage Buffer, PMOS MPS1, MPS2, NMOS tube MNS1, MNS2, electric capacity CS1 and Schmidt trigger SMTS1, the two-way high-voltage pulse signal of the high-pressure level shift circuit after improvement exports respectively through connecting the grid of respective PMOS MPS1 and the grid of NMOS tube MNS1 after two-way buffer stage Buffer, the drain electrode of PMOS MPS1 is connected with the drain interconnection of NMOS tube MNS1 and with one end of electric capacity CS1 and the input of Schmidt trigger SMTS1, the outfan of Schmidt trigger SMTS1 connects the grid of PMOS MPS2 and the grid of NMOS tube MNS2, the source electrode of PMOS MPS1 and PMOS MPS2, the power end of buffer stage Buffer and the power end of Schmidt trigger SMTS1 are all connected with floating voltage VB, the source electrode of NMOS tube MNS1 and NMOS tube MNS2, the ground end of the other end of electric capacity CS1 and the ground end of buffer stage Buffer and Schmidt trigger SMTS1 is all connected with floating reference ground VS, the drain electrode of PMOS MPS2 and the drain interconnection of NMOS tube MNS2 the outfan as pulse shaper, in two-way pulse shaper, in input termination high-pressure level shift circuit, the outfan output set signal Vset of a road pulse shaper of LDMOS pipe MN1 drain terminal is to the S input of RS latch, in input termination high-pressure level shift circuit, the outfan output reset signal Vrst of another road pulse shaper of LDMOS pipe MN3 drain terminal is to the R input of RS latch, the power end of RS latch connects floating power supply VB, the ground end of RS latch connects floating reference ground VS, the input of driver connects the outfan of RS latch, the outfan output signal VOUT of driver drives outside high side power pipe, the power end of driver connects floating power supply VB, the ground end of driver connects floating reference ground VS。
4. the high-voltage side gate drive circuit of anti-noise jamming according to claim 1, it is characterised in that: LDMOS pipe MN1, MN2 and PMOS MP1, MP2 in the high-pressure level shift circuit after described improvement can substitute with high voltage bearing IGBT pipe respectively。
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