CN112234975B

CN112234975B - High-voltage-resistant input/output circuit

Info

Publication number: CN112234975B
Application number: CN202011484260.2A
Authority: CN
Inventors: 朱仁波
Original assignee: Shanghai Lichi Semiconductor Co ltd
Current assignee: Shanghai Lichi Semiconductor Co ltd
Priority date: 2020-12-16
Filing date: 2020-12-16
Publication date: 2021-03-12
Anticipated expiration: 2040-12-16
Also published as: CN112234975A

Abstract

The invention discloses a high-voltage-resistant input/output circuit, and belongs to the technical field of chip safety. The circuit comprises: a first port of the first resistor is connected with the input end, a second port of the first resistor is respectively connected with the PMOS tube and the NMOS tube, and the second port of the first resistor is connected with the output end of the input-output circuit; a first port of the second resistor is respectively connected with the PMOS tube and the NMOS tube, and a second port of the second resistor is grounded; when the voltage of the input signal is higher than the voltage-withstanding range, the PMOS tube and the NMOS tube which are both in a conducting state carry out voltage reduction processing on the input signal so as to enable the voltage of the output signal to be in the voltage-withstanding range; when the voltage of the input signal is in the withstand voltage range, the PMOS tube and the NMOS tube which are both in the off state do not perform voltage reduction processing on the input signal, so that the voltage of the output signal is in the withstand voltage range. The invention can process high-voltage signals and simultaneously shield the processing of normal signals.

Description

High-voltage-resistant input/output circuit

Technical Field

The embodiment of the application relates to the technical field of chip safety, in particular to a high-voltage-resistant input/output circuit.

Background

With the continuous progress of integrated circuit technology and the reduction of cost, the integration level of integrated circuits is higher and higher. In order to reduce the power consumption of the chip, the gate Oxide thickness of a CMOS (Complementary Metal Oxide Semiconductor) device is thinner and thinner, so that the threshold voltage of the CMOS device is lower and lower, and the voltage withstanding range of an integrated circuit device is also lower and lower, so that it becomes more and more difficult to process an external high voltage signal. Therefore, it becomes important to design a high voltage tolerant input/output circuit. Specifically, some input signals input to the chip from the outside of the application may exceed the voltage withstanding range of the devices in the chip, and the high-voltage-withstanding input/output circuit needs to reduce the voltage of the input signals to be within the voltage withstanding range of the devices without substantially affecting the signal-to-noise ratio of the input signals.

In the related art, a high-voltage-resistant input/output circuit can be connected to the outside of the chip, and the high-voltage-resistant input/output circuit is realized by adopting a series resistor, so that the voltage of an input signal can be reduced to a withstand voltage range by a voltage division method, and then the reduced output signal is input into the chip. Referring to fig. 1, in the high-voltage tolerant input/output circuit connected to the outside of the chip in fig. 1, the input signal is divided by the resistor R4 and the resistor R5, and the voltage of the input signal is reduced to a withstand voltage range and then input to the chip.

Although the conventional input/output circuit reduces the high-voltage signal to be within the withstand voltage range, for the normal signal with the voltage within the withstand voltage range, the input/output circuit also reduces the voltage of the normal signal, so that the signal input to the chip is attenuated.

Disclosure of Invention

The embodiment of the application provides a high-voltage-resistant input/output circuit, which is used for solving the problem that the input/output circuit reduces the voltage of a normal signal to cause the signal of an input chip to be attenuated. The technical scheme is as follows:

in one aspect, a high voltage tolerant input-output circuit is provided, the input-output circuit being located in a chip;

the input-output circuit includes: the device comprises a first resistor, a P-channel metal oxide semiconductor field effect PMOS (P-channel metal oxide semiconductor) tube, an N-channel metal oxide semiconductor field effect NMOS (N-channel metal oxide semiconductor) tube and a second resistor;

a first port of the first resistor is connected with an input end of the input-output circuit, a second port of the first resistor is respectively connected with the PMOS tube and the NMOS tube, and a second port of the first resistor is connected with an output end of the input-output circuit;

a first port of the second resistor is respectively connected with the PMOS tube and the NMOS tube, and a second port of the second resistor is grounded;

when the voltage of the input signal input into the input end is higher than a withstand voltage range, the PMOS tube and the NMOS tube which are both in a conducting state carry out voltage reduction processing on the input signal, and the voltage of the output signal output from the output end after the voltage reduction processing is within the withstand voltage range;

when the voltage of the input signal input into the input end is within a withstand voltage range, the PMOS tube and the NMOS tube which are both in the off state do not perform voltage reduction processing on the input signal, and the voltage of the output signal output from the output end is within the withstand voltage range.

In a possible implementation manner, the second port of the first resistor is respectively connected to the source electrode of the PMOS transistor and the drain electrode of the NMOS transistor;

and a first port of the second resistor is respectively connected with the drain electrode of the PMOS tube and the source electrode of the NMOS tube.

In one possible implementation, the input-output circuit further includes a nor gate;

the grid electrode of the PMOS tube is connected with the output end of the NOR gate;

and the grid electrode of the NMOS tube is connected with one input end of the NOR gate.

In one possible implementation, the input-output circuit further includes a third resistor;

and a first port of the third resistor is connected with the grid electrode of the PMOS tube, and a second port of the third resistor is grounded.

In a possible implementation manner, a resistance value of the third resistor is greater than a predetermined threshold, and when the chip is not powered on, the third resistor is configured to control a voltage of an output signal output from the output terminal to be within the withstand voltage range.

In one possible implementation, the input-output circuit further includes a not gate;

the input end of the NOT gate is connected with the grid electrode of the PMOS tube;

and the output end of the NOT gate is used for outputting a monitoring signal, and the monitoring signal is used for monitoring the potential of the grid electrode of the PMOS tube.

In one possible implementation, the output of the input-output circuit is used to output an analog output signal.

In a possible implementation manner, an output end of the input/output circuit is connected to an input end of an analog-to-digital conversion element, an output end of the analog-to-digital conversion element is used for outputting a digital output signal, and the digital output signal is obtained by converting an analog output signal output by the input/output circuit.

In one possible implementation, the analog-to-digital conversion element is a schmitt trigger.

In one possible implementation manner, a first ratio of the first resistance to the second resistance is equal to a second ratio of the voltage drop to a maximum value of the withstand voltage range.

The technical scheme provided by the embodiment of the application has the beneficial effects that at least:

when the voltage of the input signal is higher than the voltage-withstanding range, the PMOS tube and the NMOS tube are both in a conducting state, and the input signal can be subjected to voltage reduction processing at the moment, so that the voltage of an output signal output from the output end after the voltage reduction processing is within the voltage-withstanding range; when the voltage of the input signal is in the withstand voltage range, the PMOS tube and the NMOS tube are both in the off state, and the voltage reduction processing of the input signal can be avoided, so that the voltage of the output signal output from the output end is in the withstand voltage range. That is, when a high-voltage signal is input, the input/output circuit can process the high-voltage signal, and devices in the chip are not damaged; when the normal signal is input, the input and output circuit can shield the normal signal from being processed, so that the signal input into the chip can be ensured not to be attenuated.

The grid electrode of the PMOS tube is connected with a third resistor with the resistance value larger than a preset threshold value, when the chip is not electrified, the PMOS tube is in a conducting state, and the third resistor can prevent an external high-voltage signal from being input into the chip, so that Fail-Safe is realized.

Under the condition that the chip is not electrified, the device in the chip can be prevented from being damaged by high voltage, and the design of functional safety is added during normal power supply, so that the reliability of the input and output circuit during application is greatly enhanced.

Drawings

In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings needed to be used in the description of the embodiments are briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present application, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without creative efforts.

Fig. 1 is a schematic diagram showing a structure of a high voltage tolerant input-output circuit according to the related art;

fig. 2 is a schematic structural diagram of a high voltage tolerant input/output circuit according to an embodiment of the present application;

FIG. 3 is a diagram of a first simulated waveform provided by an embodiment of the present application;

FIG. 4 is a diagram of a second simulated waveform provided by an embodiment of the present application;

FIG. 5 is a diagram of a third simulation waveform provided by an embodiment of the present application.

Detailed Description

To make the objects, technical solutions and advantages of the embodiments of the present application more clear, the embodiments of the present application will be further described in detail with reference to the accompanying drawings.

In the input and output circuit in the related art, two resistors are used for performing voltage reduction processing on an input signal, so that not only an input high-voltage signal but also an input normal signal can be processed, and the normal signal can be attenuated. In such an input/output circuit, if a high-precision resistor is used, the cost is high, and if a common resistor is used, the accuracy of voltage reduction is affected, that is, the hardware cost is high, or the performance is poor.

In addition, the chip in the automotive field has higher requirements for reliability, Fail-Safe needs to be ensured, and functional safety needs to be met, and even if the chip is not powered on, internal devices of the chip cannot be damaged by external high-voltage signals, which brings greater challenges to the design of Input/Output (I/O) circuits.

Fig. 1 shows a voltage dividing unit 01, which divides voltage through resistors R4 and R5 to reduce a high voltage signal to a range that can be borne by a device, if a chip is desired to have a flexible application, the two resistors are added outside the chip, the precision of the resistors is determined by the precision requirement of the voltage reduction ratio, the two resistors can be integrated in the chip, and the high precision voltage reduction ratio is achieved by using good matching performance of the process, both of which can achieve the requirements of high reliability and Fail-Safe, but both of which have respective defects, the former may greatly increase the cost due to the increase of the number of I/os and the requirement of the high precision resistors, and the latter may cause the normal signal to be attenuated.

Therefore, it is important to design a high-voltage-resistant input/output circuit with high reliability and safety functions and Fail-Safe characteristics. Aiming at the defects of the prior art, the invention provides the input/output circuit integrated in the chip, which can realize accurate voltage reduction by utilizing the good matching property of the prior art, provide flexible mode selection, simultaneously ensure that the internal devices are not damaged by the influence of high-voltage signals by utilizing the self-bias mode selection under the condition that the chip is not electrified, and greatly enhance the reliability of the input/output circuit in application by adding the design of functional safety during normal power supply.

The invention realizes the application of compatible normal signals and the application of high-voltage signals based on the requirement of high reliability, and specifically takes the normal working voltage of a device as 3.3V and the withstand voltage as 3.63V as an example, and realizes the application of compatible maximum 5.5V signals and the application of maximum normal range as 3.63V. Then, the voltage needs to be dropped to 3.63V when an application with a voltage of 5.5V is accessed, and the signal-to-noise ratio of the signal is not affected; while for applications with a normal maximum amplitude of 3.63V the voltage and signal-to-noise ratio of the signal are not changed. And when the chip is not powered on, the device does not receive a high voltage signal, namely, the so-called Fail-Safe. The main structure of the input/output circuit of the present invention will be described with reference to fig. 2.

Referring to fig. 2, a schematic diagram of a high voltage tolerant input/output circuit according to an embodiment of the present application is shown. The high-voltage-resistant input/output circuit is located in a chip and can comprise: a first resistor R1, a PMOS (P-channel Metal Oxide Semiconductor field effect) transistor MP1, an NMOS (N-channel Metal Oxide Semiconductor field effect) transistor MN1, and a second resistor R2.

In this embodiment, a first port of the first resistor R1 is connected to the input terminal pad (hv) of the input/output circuit, a second port of the first resistor R1 is connected to the PMOS transistor MP1 and the NMOS transistor MN1, respectively, and a second port of the first resistor R1 is connected to the output terminal of the input/output circuit. Specifically, the second port of the first resistor R1 is connected to the source of the PMOS transistor MP1 and the drain of the NMOS transistor MN1, respectively.

The output end of the input and output circuit comprises an analog signal output end AIO and a digital signal output end D _ OUT. When the output end of the input/output circuit is the analog signal output end AIO, the output end AIO of the input/output circuit is used for outputting an analog output signal.

When the output end of the input/output circuit is the digital signal output end D _ OUT, the output end D _ OUT of the input/output circuit is connected with the input end of the analog-to-digital conversion element, the output end of the analog-to-digital conversion element is used for outputting a digital output signal, and the digital output signal is obtained by converting an analog output signal output by the input/output circuit. As shown in fig. 2, a connection point of the second port of the first resistor R1, the source of the PMOS transistor MP1, and the drain of the NMOS transistor MN1 may be referred to as a node a. Then, the analog-to-digital conversion element may perform analog-to-digital conversion on the analog output signal output by the node a, and then output the digital output signal obtained after the conversion to the output terminal D _ OUT, and the output terminal D _ OUT outputs the final digital output signal.

The analog-to-digital conversion element may be a schmitt trigger, or may be another element capable of implementing analog-to-digital conversion, which is not limited in this embodiment.

In this embodiment, the first port of the second resistor R2 is connected to the PMOS transistor MP1 and the NMOS transistor MN1, respectively, and the second port of the second resistor R2 is grounded. Specifically, the first port of the second resistor R2 is connected to the drain of the PMOS transistor MP1 and the source of the NMOS transistor MN1, respectively.

Optionally, the input-output circuit may further include a NOR gate NOR2_ 1; the gate of the PMOS transistor MP1 is connected to the output terminal of the NOR gate NOR2_ 1; the gate of the NMOS transistor MN1 is connected to one input of the NOR gate NOR2_ 1. As shown in fig. 2, a connection point of the gate of the PMOS transistor MP1 and the output terminal of the NOR gate NOR2_1 may be referred to as a node B, a connection point of the gate of the NMOS transistor MN1 and one input terminal of the NOR gate NOR2_1 may be referred to as a node C, and a connection point of the source of the NMOS transistor MN1 and the first port of the second resistor R2 may be referred to as a node D.

The PMOS transistor MP1 is a large P-type MOS transistor, and as long as the voltage difference between the source voltage (i.e. the voltage at the node a) and the gate voltage (i.e. the voltage at the node B) of the transistor MP1 exceeds the threshold voltage (typically about 0.7V), the PMOS transistor MP1 is turned on, and the on-resistance decreases as the voltage difference between the nodes AB increases. The NMOS transistor MN1 is a large N-type NOS transistor, and as long as the voltage difference between the gate voltage (i.e., the voltage at the node C) and the source voltage (i.e., the voltage at the node D) of MN1 exceeds the threshold voltage (typically about 0.7V), the NMOS transistor MN1 is turned on, and the on-resistance decreases as the voltage difference between the nodes CD increases.

The input-output circuit can be put into two operation modes by controlling the potential of the node B in this embodiment. These two modes of operation are described separately below.

The first mode of operation is a high pressure mode. When the voltage of the input signal at the input end is higher than the withstand voltage range, the PMOS transistor MP1 and the NMOS transistor MN1, both of which are in the on state, perform voltage reduction processing on the input signal, and the voltage of the output signal output from the output end after the voltage reduction processing is within the withstand voltage range.

In the high-voltage mode, the node B is controlled to be at a low potential by controlling input signals of two input ends of the NOR gate NOR2_1, so that the PMOS transistor MP1 and the NMOS transistor MN1 are in a conducting state, an externally input high-voltage signal is divided by the first resistor R1 and the second resistor R2, and thus the voltage of an output signal of the node a is reduced, the voltage is reduced to a withstand voltage range of the device, and the device is protected from being damaged.

The first ratio of the first resistor R1 to the second resistor R2 is equal to the second ratio of the voltage drop to the maximum value of the withstand voltage range. Taking an example where the high pressure is 5.5V and the maximum value of the withstand voltage range is 3.63V, R1/R2= (5.5-3.63)/3.63 = 17/33.

The second mode of operation is the bypass mode. In the bypass mode, that is, when the voltage of the input signal at the input terminal is within the withstand voltage range, the PMOS transistor MP1 and the NMOS transistor MN1, both of which are in the off state, do not perform voltage reduction processing on the input signal, and the voltage of the output signal output from the output terminal is within the withstand voltage range.

In the bypass mode, the node B is controlled to be at a high potential by controlling the input signals of the two input ends of the NOR gate NOR2_1, so that the PMOS transistor MP1 and the NMOS transistor MN1 are in an off state, and the externally input normal signal is not divided by the first resistor R1 and the second resistor R2, so that the output signal of the node a is approximately equal to the input signal, and the input signal is prevented from being attenuated.

The user can control the chip to be in the corresponding working mode according to the voltage of the external application of the chip. For example, when the application of the external 5.5V voltage of the chip is determined, the input/output circuit is controlled to be in a high-voltage mode; and when the application of the external 3.3V voltage of the chip is determined, controlling the input and output circuit to be in a bypass mode.

In order to realize Fail-Safe, a large grounded resistor (i.e., the third resistor R3) may be added at the node B, so that when the chip is not powered on, a high-voltage signal is input from the outside, and the PMOS transistor MP1 is turned on by default, so as to ensure that the voltage at the node a is within the withstand voltage range, so that the voltage of the input signal input to the device in the chip does not exceed the withstand voltage range of the device. That is, the gate of the PMOS transistor MP1 is connected to the third resistor R3, which has a resistance greater than a predetermined threshold, when the chip is not powered on, the PMOS transistor MP1 is in a conducting state, and the third resistor R3 can prevent an external high-voltage signal from being input into the chip, so as to implement Fail-Safe.

Specifically, the input-output circuit may further include a third resistor R3; the first port of the third resistor R3 is connected to the gate of the PMOS transistor MP1, and the second port of the third resistor R3 is grounded. The resistance value of the third resistor R3 is greater than a predetermined threshold, and when the chip is not powered on, the third resistor R3 is used for controlling the voltage of the output signal output from the output end to be within a withstand voltage range.

In this embodiment, the NOR2_1 is a two-input NOR gate, and the NOR2_1 outputs a high signal only when the two input terminals Mode _ sel <1> and Mode _ sel <0> simultaneously input a low signal, so as to pull the potential of the node B high to control the PMOS transistor MP1 to be in the off state, and make the input/output circuit enter the bypass Mode. When in the bypass Mode, because the PMOS transistor MP1 and the NMOS transistor MN1 are both in the off high-impedance state, the input signal inputted from the input terminal pad (hv) is not attenuated, and extra care is needed, i.e. two input signals of Mode _ sel <1> and Mode _ sel <0> of the NOR gate NOR2_1 are used to make double guarantee, so as to prevent the problem that when the potential of the node B is controlled by only one input signal, the operation Mode of the input/output circuit enters the bypass Mode erroneously due to the failure of the input signal, and the devices in the chip are damaged by the high-voltage signal. The NMOS transistor MN1 mainly plays a role of conduction at a low voltage portion of an input signal to improve signal quality in a full signal range, so that the potential of the gate voltage C point of the NMOS transistor MN1 is controlled by only one input signal, and thus, safety is not affected.

Optionally, the input/output circuit may further include an inverter INV _ 1; the input end of the NOT gate INV _1 is connected with the grid electrode of the PMOS tube MP 1; the output end of the not gate INV _1 is used for outputting a monitoring signal, and the monitoring signal is used for monitoring the potential of the gate of the PMOS transistor MP 1. Then, the potential of the node B can be monitored through the not gate INV _ 1. Thus, high reliability can be achieved by a combination of the NOR gate NOR2_1 and the NOR gate INV _1, and the embodiment is only illustrated in the above manner, but not limited to this manner, and high reliability can be achieved by flexibly using a redundant design of a logic circuit.

It should be noted that the PMOS transistor MP1 and the NMOS transistor MN1 may form a CMOS switch, so as to ensure that the equivalent resistance in the whole signal range is at a relatively stable value, and ensure that the signal quality is not affected by the presence of the switch, thereby improving the quality of the output signal.

In fig. 2, 001 denotes a mode selection and monitoring unit, 002 denotes a third resistor, and 003 denotes a voltage dividing unit.

Referring to fig. 3-5, fig. 3 shows waveforms in which, when an external voltage is applied in a voltage withstanding range of a device, the amplitude of a chip is attenuated before power-on, and the amplitude is kept unchanged after power-on; FIG. 4 shows waveforms that are attenuated before power-up of the chip and configured in an amplitude attenuation mode after power-up, when an external voltage is applied within a withstand voltage range of the device; fig. 5 shows waveforms that are attenuated before power-up of the chip and are still in attenuation mode after power-up, when the external voltage is higher than the withstand voltage range of the device.

In summary, in the high-voltage tolerant input/output circuit provided in the embodiment of the present application, when the voltage of the input signal is higher than the withstand voltage range, both the PMOS transistor and the NMOS transistor are in the on state, and at this time, the voltage of the input signal may be reduced, so that the voltage of the output signal output from the output terminal after the voltage reduction is within the withstand voltage range; when the voltage of the input signal is in the withstand voltage range, the PMOS tube and the NMOS tube are both in the off state, and the voltage reduction processing of the input signal can be avoided, so that the voltage of the output signal output from the output end is in the withstand voltage range. That is, when a high-voltage signal is input, the input/output circuit can process the high-voltage signal, and devices in the chip are not damaged; when the normal signal is input, the input and output circuit can shield the normal signal from being processed, so that the signal input into the chip can be ensured not to be attenuated.

The NOR gate has two input ends, so that double guarantee can be made in the bypass mode, and the problem that when the potential of the node B is controlled by only one input signal, the working mode of the input-output circuit is mistakenly entered into the bypass mode due to the failure of the input signal, and devices in a chip are damaged by a high-voltage signal is solved. And the monitoring signal can monitor the potential of the node B, so that the reliability of the input-output circuit can be greatly increased.

The PMOS tube and the NMOS tube can form a CMOS switch, so that the equivalent resistance in the whole signal range can be ensured to be at a relatively stable value, the signal quality can be ensured not to be influenced by the existence of the switch, and the quality of output signals is improved.

The above description should not be taken as limiting the embodiments of the present application, and any modifications, equivalents, improvements, etc. made within the spirit and principle of the embodiments of the present application should be included in the scope of the embodiments of the present application.

Claims

1. The input-output circuit with high voltage resistance is characterized in that the input-output circuit is positioned in a chip;

when the voltage of the input signal input into the input end is within a withstand voltage range, the PMOS tube and the NMOS tube which are both in a disconnected state do not perform voltage reduction processing on the input signal, and the voltage of the output signal output from the output end is within the withstand voltage range;

the input-output circuit further comprises a two-input NOR gate; the grid electrode of the PMOS tube is connected with the output end of the NOR gate; the grid electrode of the NMOS tube is connected with one input end of the NOR gate, when two input ends of the NOR gate simultaneously input low level signals, the output end of the NOR gate outputs high level signals, and the high level signals are used for controlling the PMOS tube to be in a disconnection state.

2. The high voltage tolerant input-output circuit of claim 1,

a second port of the first resistor is respectively connected with a source electrode of the PMOS tube and a drain electrode of the NMOS tube;

3. The high voltage tolerant input-output circuit of claim 1, further comprising a third resistor;

4. The high voltage tolerant input-output circuit of claim 3, wherein the third resistor has a resistance value larger than a predetermined threshold value, and is configured to control a voltage of an output signal output from the output terminal to be within the withstand voltage range when the chip is not powered on.

5. The high voltage tolerant input-output circuit of claim 1, further comprising a not gate;

6. The high voltage tolerant input-output circuit of claim 1, wherein an output of the input-output circuit is configured to output an analog output signal.

7. The high voltage tolerant input-output circuit of claim 1, wherein an output terminal of the input-output circuit is connected to an input terminal of an analog-to-digital conversion element, an output terminal of the analog-to-digital conversion element is configured to output a digital output signal, and the digital output signal is obtained by converting an analog output signal output by the input-output circuit.

8. The high voltage tolerant input-output circuit of claim 7, wherein the analog-to-digital conversion element is a Schmitt trigger.

9. The high-voltage-tolerant input-output circuit according to any one of claims 1 to 8, wherein a first ratio of the first resistance to the second resistance is equal to a second ratio of a voltage drop to a maximum value of the withstand voltage range.