CN114498572B - CMOS process compatible interface chip power-down protection circuit and method - Google Patents

Abstract

The invention discloses a CMOS process compatible interface chip power-down protection circuit and a CMOS process compatible interface chip power-down protection method, wherein the circuit comprises a power chip protection sub-circuit and a substrate potential generation sub-circuit; the interface chip power-down protection circuit compatible with the CMOS process does not require the process to be provided with a special device, can be realized under the standard CMOS process, has a simple circuit structure, can generate the substrate potential of a PMOS tube by the substrate potential generation sub-circuit, can effectively reduce the current backflow when the high potential appears at the output end under the condition of power failure of a power supply, and can realize that the leakage current of the interface chip power-down protection circuit is lower than the 1uA index.

Description

CMOS process compatible interface chip power-down protection circuit and method

Technical Field

The invention belongs to the field of integrated circuit devices and digital signal transmission, and particularly relates to a CMOS (complementary metal oxide semiconductor) process compatible interface chip power-down protection circuit and a CMOS process compatible interface chip power-down protection method.

Background

With the rapid development of integrated circuits, digital signal transmission is becoming more common in systems, and the transmission of digital signals often involves many-to-one signal transmission. For a traditional signal transmission system generally adopts an inverter structure, an existing integrated circuit system is often designed to save energy, and under certain conditions, the system can only have the possibility that some signal transmission systems transmit signals, and the rest systems do not transmit signals, so that the system can carry out energy-saving processing on the systems which do not transmit signals to reduce the power consumption of the whole system, and the best method for the energy-saving processing is to directly power down the systems which do not transmit signals and reduce the power supply voltage to the ground potential, so that the system does not have the power consumption. However, when a system sending a signal sends a high level, the high level is output to an OUT end of a power-down system, the OUT end is a high voltage, a power supply of a source electrode of a pull-up PMOS of the output is powered down to a ground potential, a conductive path from the OUT end to GND through a parasitic diode is formed at the moment, when the OUT end has the high level, the path can generate a current I1, and since the PMOS is a pull-up power transistor and is generally large in area, the parasitic diode is also large in area, the current I1 is large, the high level of the OUT end is easily clamped at a low level, and a subsequent signal receiving system cannot recognize the high level.

Disclosure of Invention

Aiming at the defects in the prior art, the power-down protection circuit and the power-down protection method for the interface chip compatible with the CMOS process solve the problem that a conductive path exists between the interface chip and the ground under the condition of power-down.

In order to achieve the purpose of the invention, the invention adopts the technical scheme that: a CMOS process compatible interface chip power-down protection circuit comprises a power chip protection sub-circuit and a substrate potential generation sub-circuit;

the first input end of the power chip protection sub-circuit is used as the input end of the CMOS process compatible interface chip power-down protection circuit, and the output end of the power chip protection sub-circuit is used as the output end of the CMOS process compatible interface chip power-down protection circuit;

the input end of the substrate potential generating sub-circuit is connected with the output end of the power chip protection sub-circuit, and the output end of the substrate potential generating sub-circuit is respectively connected with the second input end and the third input end of the power chip protection sub-circuit;

the power chip protection sub-circuit is used for preventing the current at the output end of the interface chip power-down protection circuit compatible with the CMOS process from flowing backwards to a power port under the condition that the power supply of the interface chip compatible with the CMOS process is powered down; the substrate potential generating sub-circuit is used for outputting a substrate voltage.

Further, the method comprises the following steps: the power chip protection sub-circuit comprises a power chip protection sub-circuit and a power chip protection sub-circuit, wherein the power chip protection sub-circuit comprises a PMOS tube P0, a PMOS tube P1, a PMOS tube P2, a PMOS tube P3, a PMOS tube P4, an NMOS tube N0, an NMOS tube N1, an NMOS tube N2, an NMOS tube N3 and an NMOS tube N4;

wherein the gate of the PMOS transistor P0 is connected to the gate of the NMOS transistor N0, the source of the PMOS transistor P0 is connected to a VDD power supply, the gate of the NMOS transistor N0 serves as the first input terminal of the power chip protection sub-circuit, the source of the NMOS transistor N0 is grounded, the drain of the NMOS transistor N0 is connected to the drain of the PMOS transistor P0, the gate of the PMOS transistor P1 and the gate of the NMOS transistor N1, the source of the PMOS transistor P1 is connected to the VDD power supply, the drain of the PMOS transistor P1 is connected to the drain of the NMOS transistor N1, the gate of the PMOS transistor P2, the gate of the PMOS transistor P3, the gate of the NMOS transistor N2 and the gate of the NMOS transistor N3, the source of the NMOS transistor N1 is grounded, and the source of the PMOS transistor P2 is connected to the VDD power supply, the drain electrode of the PMOS pipe P2 is connected with the drain electrode of the NMOS pipe N2 and the grid electrode of the NMOS pipe N4 respectively, the source electrode of the NMOS pipe N2 is grounded, the source electrode of the PMOS pipe P3 serves as a second input end of the power chip protection sub-circuit, the drain electrode of the PMOS pipe P3 is connected with the drain electrode of the NMOS pipe N3 and the grid electrode of the PMOS pipe P4 respectively, the source electrode of the NMOS pipe N3 is grounded, the source electrode of the PMOS pipe P4 is connected with the VDD power supply, the substrate of the PMOS pipe P4 serves as a third input end of the power chip protection sub-circuit, the drain electrode of the PMOS pipe P4 is connected with the drain electrode of the NMOS pipe N4 and serves as an output end of the power chip protection sub-circuit, and the source electrode of the NMOS pipe N4 is grounded.

The beneficial effects of the above further scheme are: the interface chip power-down protection circuit compatible with the CMOS process does not require the process to be provided with special devices, and can be realized under the standard CMOS process, the output voltage Vbias of the substrate potential generation sub-circuit provides substrate potential for the PMOS pipe P4, the one-way path from the output end of the interface chip power-down protection circuit to a power-down power supply is cut off through the substrate potential generated by the circuit, the Vbias voltage provides the power supply for the PMOS pipe P3, the PMOS pipe P4 is prevented from being started under the condition of power failure, and therefore the output end is prevented from reversely flowing current to a power supply end when the power supply is powered down.

Further: the substrate potential generating sub-circuit comprises a PMOS tube P5, a PMOS tube P6, a PMOS tube P7, a PMOS tube P8, a PMOS tube P9, an NMOS tube N5, an NMOS tube N6 and a resistor R1;

the gate of a PMOS transistor P5 is connected to the gate of the NMOS transistor N5 and the source of a PMOS transistor P9 respectively and serves as the input terminal of the substrate potential generating sub-circuit, the source of the PMOS transistor P5 is connected to the VDD power supply, the drain of the PMOS transistor P5 is connected to the drain of the NMOS transistor N5 and the gate of the NMOS transistor N6 respectively, the source of the NMOS transistor N5 is grounded, the source of the NMOS transistor N6 is grounded, the drain of the NMOS transistor N6 is connected to the gate of the PMOS transistor P6, the drain of the PMOS transistor P8 and the drain of the PMOS transistor P9 respectively, the source of the PMOS transistor P6 is connected to the VDD power supply, the drain of the PMOS transistor P6 is connected to the substrate of the PMOS transistor P6, the source of the PMOS transistor P8, the substrate of the PMOS transistor P9, the gate of the PMOS transistor P7, the drain of the PMOS transistor P7 and the substrate of the PMOS transistor P7 respectively, the source of the PMOS transistor P7 is connected to the PMOS power supply, and the drain of the PMOS transistor P7 serves as the output terminal of the substrate potential generating sub-circuit; the grid electrode of the PMOS tube P8 is respectively connected with the grid electrode of the PMOS tube P9 and one end of the resistor R1, and the other end of the resistor R1 is connected with the VDD power supply.

The beneficial effects of the above further scheme are: the substrate potential generating sub-circuit can generate the substrate potential of the PMOS tube, so that the situation that the substrate potential of the PMOS tube directly adopts power supply voltage is avoided.

A power-down protection method for an interface chip compatible with a CMOS (complementary metal oxide semiconductor) process comprises the following steps:

s1, when a power supply of an interface chip compatible with a CMOS (complementary metal oxide semiconductor) process is powered off, generating a substrate voltage through a substrate potential generation sub-circuit;

and S2, generating substrate voltage generated by the sub-circuit according to the substrate potential, and controlling the PMOS pipe P4 to be closed to finish power-down protection of the interface chip.

Further, the method comprises the following steps: the step S1 specifically includes:

when the power supply of the interface chip compatible with the CMOS process is powered off and the output end of the power-down protection circuit of the interface chip compatible with the CMOS process is externally connected with a high level, the high level of the output end of the power-down protection circuit of the interface chip compatible with the CMOS process is conducted through the PMOS pipe P8 and the PMOS pipe P9 to obtain the substrate voltage Vbias of the high level.

Further: the step S2 specifically comprises the following steps:

and providing a substrate potential for the PMOS tube P4 according to the substrate voltage Vbias, controlling the PMOS tube P4 to be non-conductive according to the gate voltage Vy =0V of the NMOS tube N3 and the gate voltage Vz = Vbias of the PMOS tube P4, and cutting off the substrate of the PMOS tube P4 to a power supply path to realize power failure protection of the interface chip.

The invention has the beneficial effects that:

(1) The interface chip power-down protection circuit compatible with the CMOS process does not require a special device in the process, can be realized under the standard CMOS process, and has a simple circuit structure.

(2) The substrate potential generating sub-circuit can generate the substrate potential of the PMOS tube, the current backflow when the high potential appears at the output end can be effectively reduced under the condition of power failure of a power supply, and the leakage current of the PMOS tube can be lower than the 1uA index.

(3) The invention solves the problem of backward flowing current from the output end to the power port under the condition of power failure of the interface circuit power supply, and no matter the output end DOUT is in high level or low level, the current to the power supply end can not be generated, thereby realizing the power failure protection function of the chip.

Drawings

Fig. 1 is a schematic diagram of a power-down protection circuit of an interface chip compatible with a CMOS process.

Fig. 2 is a flow chart of a power down protection method for a CMOS process compatible interface chip.

Detailed Description

The following description of the embodiments of the present invention is provided to facilitate the understanding of the present invention by those skilled in the art, but it should be understood that the present invention is not limited to the scope of the embodiments, and it will be apparent to those skilled in the art that various changes may be made without departing from the spirit and scope of the invention as defined and defined in the appended claims, and all matters produced by the invention using the inventive concept are protected.

Example 1:

as shown in fig. 1, in an embodiment of the present invention, a CMOS process compatible interface chip power-down protection circuit includes a power chip protection sub-circuit and a substrate potential generation sub-circuit;

the first input end of the power chip protection sub-circuit is used as the input end of the interface chip power-down protection circuit compatible with the CMOS process, and the output end of the power chip protection sub-circuit is used as the output end of the interface chip power-down protection circuit compatible with the CMOS process;

the input end of the substrate potential generating sub-circuit is connected with the output end of the power chip protection sub-circuit, and the output end of the substrate potential generating sub-circuit is respectively connected with the second input end and the third input end of the power chip protection sub-circuit;

the power chip protection sub-circuit is used for preventing the current at the output end of the interface chip power-down protection circuit compatible with the CMOS process from flowing backwards to a power port under the condition that the power supply of the interface chip compatible with the CMOS process is powered down; the substrate potential generating sub-circuit is used for outputting a substrate voltage.

The power chip protection sub-circuit comprises a power chip protection sub-circuit which comprises a PMOS (P-channel metal oxide semiconductor) tube P0, a PMOS tube P1, a PMOS tube P2, a PMOS tube P3, a PMOS tube P4, an NMOS (N-channel metal oxide semiconductor) tube N0, an NMOS tube N1, an NMOS tube N2, an NMOS tube N3 and an NMOS tube N4;

wherein the gate of the PMOS tube P0 is connected to the gate of the NMOS tube N0, the source of the PMOS tube P0 is connected to the VDD power supply, the gate of the NMOS tube N0 is used as the first input terminal of the power chip protection sub-circuit, the source of the NMOS tube N0 is grounded, the drain of the NMOS tube N0 is connected to the drain of the PMOS tube P0, the gate of the PMOS tube P1 and the gate of the NMOS tube N1, the source of the PMOS tube P1 is connected to the VDD power supply, the drain of the PMOS tube P1 is connected to the drain of the NMOS tube N1, the gate of the PMOS tube P2, the gate of the PMOS tube P3, the gate of the NMOS tube N2 and the gate of the NMOS tube N3, the source of the NMOS tube N1 is grounded, the source of the PMOS tube P2 is connected to the VDD power supply, the drain electrode of the PMOS pipe P2 is respectively connected with the drain electrode of the NMOS pipe N2 and the grid electrode of the NMOS pipe N4, the source electrode of the NMOS pipe N2 is grounded, the source electrode of the PMOS pipe P3 is used as a second input end of the power chip protection sub-circuit, the drain electrode of the PMOS pipe P3 is respectively connected with the drain electrode of the NMOS pipe N3 and the grid electrode of the PMOS pipe P4, the source electrode of the NMOS pipe N3 is grounded, the source electrode of the PMOS pipe P4 is connected with the VDD power supply, the substrate of the PMOS pipe P4 is used as a third input end of the power chip protection sub-circuit, the drain electrode of the PMOS pipe P4 is connected with the drain electrode of the NMOS pipe N4 and is used as an output end of the power chip protection sub-circuit, and the source electrode of the NMOS pipe N4 is grounded.

The beneficial effect of this embodiment does: the interface chip power-down protection circuit compatible with the CMOS process does not require the process to be provided with special devices, can be realized under the standard CMOS process, and has a simple circuit structure, the substrate potential is provided for the PMOS tube P4 by the output voltage Vbias of the substrate potential generation sub-circuit, the one-way passage from the output end of the interface chip power-down protection circuit to a power-down power supply is cut off by the substrate potential generated by the circuit, the Vbias voltage provides the power supply for the PMOS tube P3, the PMOS tube P4 is prevented from being started under the condition of power-down, and therefore the output end of the power-down power supply is prevented from reversely flowing current to a power supply end.

Example 2:

the present embodiment is directed to a specific circuit structure of the substrate potential generation sub-circuit.

The substrate potential generating sub-circuit comprises a PMOS (P-channel metal oxide semiconductor) tube P5, a PMOS tube P6, a PMOS tube P7, a PMOS tube P8, a PMOS tube P9, an NMOS (N-channel metal oxide semiconductor) tube N5, an NMOS (N-channel metal oxide semiconductor) tube N6 and a resistor R1;

the gate of a PMOS transistor P5 is connected to the gate of the NMOS transistor N5 and the source of a PMOS transistor P9 respectively and serves as the input terminal of the substrate potential generating sub-circuit, the source of the PMOS transistor P5 is connected to the VDD power supply, the drain of the PMOS transistor P5 is connected to the drain of the NMOS transistor N5 and the gate of the NMOS transistor N6 respectively, the source of the NMOS transistor N5 is grounded, the source of the NMOS transistor N6 is grounded, the drain of the NMOS transistor N6 is connected to the gate of the PMOS transistor P6, the drain of the PMOS transistor P8 and the drain of the PMOS transistor P9 respectively, the source of the PMOS transistor P6 is connected to the VDD power supply, the drain of the PMOS transistor P6 is connected to the substrate of the PMOS transistor P6, the source of the PMOS transistor P8, the substrate of the PMOS transistor P9, the gate of the PMOS transistor P7, the drain of the PMOS transistor P7 and the substrate of the PMOS transistor P7 respectively, the source of the PMOS transistor P7 is connected to the PMOS power supply, and the drain of the PMOS transistor P7 serves as the output terminal of the substrate potential generating sub-circuit; the grid electrode of the PMOS tube P8 is respectively connected with the grid electrode of the PMOS tube P9 and one end of the resistor R1, and the other end of the resistor R1 is connected with the VDD power supply.

The beneficial effect of this embodiment does: the substrate potential generation sub-circuit can generate the substrate potential of the PMOS tube, so that the situation that the substrate potential of the PMOS tube directly adopts power supply voltage is avoided, a path from the output end to a power supply is cut off through the circuit, the current backflow when the high potential occurs at the output end can be effectively reduced under the condition that the power supply is powered off, and the leakage current of the circuit is lower than the 1uA index.

The working principle of the interface chip power-down protection circuit compatible with the CMOS process is as follows: when the power supply VDD supplies power normally, the power supply VDD provides power supply voltage for the interface chip, when an input signal DIN of the input end of the power-down protection circuit of the interface chip compatible with the CMOS process is at a low level, the NMOS tube N4 is turned on, the PMOS tube P4 is turned off, the output end DOUT end of the power-down protection circuit of the interface chip compatible with the CMOS process is pulled to the ground potential by the NMOS tube N4, the NMOS tube N6 in the substrate potential generation sub-circuit is turned on, the drain voltage Vx =0V of the NMOS tube N6 is turned on, and the PMOS tube P6 is turned on, so the substrate potential generation sub-circuit outputs the substrate voltage Vbias = VDD; when the input signal DIN is at a high level, the NMOS transistor N4 is turned off, the PMOS transistor P4 is turned on, and the output terminal DOUT is pulled to a high potential by the PMOS transistor P4.

When the power supply is powered off (VDD = 0V) and the output end DOUT is externally connected with a low level, no voltage difference exists between the output end DOUT and a power supply end and a ground port, and no current is generated; when the output end DOUT is externally connected with a high level, the voltage difference from the output end DOUT to a power supply end and a ground port exists, due to the fact that the power supply is powered off, the grid electrode of the NMOS tube N4 is the ground potential, the NMOS tube N4 is closed, and the current from the output end DOUT to the ground port cannot be generated; the output end DOUT is at a high level, the power supply is at the ground potential, the PMOS tube P8 and the PMOS tube P9 are conducted, and the DOUT at the high level generates substrate voltage Vbias through the PMOS tube P8 and the PMOS tube P9, so that the substrate voltage Vbias = VDOUT (the voltage of the output end DOUT) at the moment and provides substrate potential for the PMOS tube P4; in addition, due to power failure of a power supply, the grid voltage Vy =0V of the NMOS tube N3, the grid voltage Vz = Vbias of the PMOS tube P4 and the PMOS tube P4 cannot be conducted, and due to the fact that the substrate potential of the PMOS tube P4 is Vbias, a path from a substrate to the power supply is cut off, and finally under the condition that the circuit is powered down, no matter the output end is in a high level or a low level, current cannot be generated to a power supply end, and the power failure protection function of the chip is achieved.

Example 3:

the embodiment is a method based on a CMOS process compatible interface chip power-down protection circuit.

As shown in fig. 2, in this embodiment, a power down protection method for an interface chip compatible with a CMOS process includes the following steps:

s1, when a power supply of an interface chip compatible with a CMOS (complementary metal oxide semiconductor) process is powered off, generating a substrate voltage through a substrate potential generation sub-circuit;

and S2, generating substrate voltage generated by the sub-circuit according to the substrate potential, and controlling the PMOS pipe P4 to be closed to finish power-down protection of the interface chip.

The step S1 specifically includes:

when the power supply of the interface chip compatible with the CMOS process is powered off and the output end of the power-down protection circuit of the interface chip compatible with the CMOS process is externally connected with a high level, the high level of the output end of the power-down protection circuit of the interface chip compatible with the CMOS process is conducted through the PMOS pipe P8 and the PMOS pipe P9 to obtain the substrate voltage Vbias of the high level.

The step S2 specifically includes:

and providing a substrate potential for the PMOS tube P4 according to the substrate voltage Vbias, controlling the PMOS tube P4 to be non-conductive according to the grid voltage Vy =0V of the NMOS tube N3 and the grid voltage Vz = Vbias of the PMOS tube P4, and cutting off a substrate-to-power supply path of the PMOS tube P4 to realize power-down protection of the interface chip.

The beneficial effects of the invention are as follows: the invention solves the problem of backward flow of current from the output end to the power port of the interface circuit under the condition of power failure of the power supply, and has the characteristics of simple circuit structure, convenient use and realization by a standard CMOS process.

In the description of the present invention, it is to be understood that the terms "center", "thickness", "upper", "lower", "horizontal", "top", "bottom", "inner", "outer", "radial", and the like, indicate orientations and positional relationships based on the orientations and positional relationships shown in the drawings, and are used merely for convenience in describing the present invention and for simplicity in description, and do not indicate or imply that the referenced devices or elements must have a particular orientation, be constructed and operated in a particular orientation, and thus, are not to be construed as limiting the present invention. Furthermore, the terms "first," "second," and "third" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or an implicit indication of the number of technical features. Thus, features defined as "first", "second", and "third" may explicitly or implicitly include one or more of such features.

Claims (4)

1. A CMOS process compatible interface chip power-down protection circuit is characterized by comprising a power chip protection sub-circuit and a substrate potential generation sub-circuit;

the first input end of the power chip protection sub-circuit is used as the input end of the CMOS process compatible interface chip power-down protection circuit, and the output end of the power chip protection sub-circuit is used as the output end of the CMOS process compatible interface chip power-down protection circuit;

the input end of the substrate potential generating sub-circuit is connected with the output end of the power chip protection sub-circuit, and the output end of the substrate potential generating sub-circuit is respectively connected with the second input end and the third input end of the power chip protection sub-circuit;

the power chip protection sub-circuit comprises a PMOS tube P0, a PMOS tube P1, a PMOS tube P2, a PMOS tube P3, a PMOS tube P4, an NMOS tube N0, an NMOS tube N1, an NMOS tube N2, an NMOS tube N3 and an NMOS tube N4;

wherein the gate of the PMOS tube P0 is connected to the gate of the NMOS tube N0, the source of the PMOS tube P0 is connected to the VDD power supply, the gate of the NMOS tube N0 is used as the first input terminal of the power chip protection sub-circuit, the source of the NMOS tube N0 is grounded, the drain of the NMOS tube N0 is connected to the drain of the PMOS tube P0, the gate of the PMOS tube P1 and the gate of the NMOS tube N1, the source of the PMOS tube P1 is connected to the VDD power supply, the drain of the PMOS tube P1 is connected to the drain of the NMOS tube N1, the gate of the PMOS tube P2, the gate of the PMOS tube P3, the gate of the NMOS tube N2 and the gate of the NMOS tube N3, the source of the NMOS tube N1 is grounded, the source of the PMOS tube P2 is connected to the VDD power supply, the drain electrode of the PMOS tube P2 is respectively connected with the drain electrode of the NMOS tube N2 and the grid electrode of the NMOS tube N4, the source electrode of the NMOS tube N2 is grounded, the source electrode of the PMOS tube P3 is used as a second input end of the power chip protection sub-circuit, the drain electrode of the PMOS tube P3 is respectively connected with the drain electrode of the NMOS tube N3 and the grid electrode of the PMOS tube P4, the source electrode of the NMOS tube N3 is grounded, the source electrode of the PMOS tube P4 is connected with the VDD power supply, the substrate of the PMOS tube P4 is used as a third input end of the power chip protection sub-circuit, the drain electrode of the PMOS tube P4 is connected with the drain electrode of the NMOS tube N4 and is used as an output end of the power chip protection sub-circuit, and the source electrode of the NMOS tube N4 is grounded;

the substrate potential generating sub-circuit comprises a PMOS (P-channel metal oxide semiconductor) tube P5, a PMOS tube P6, a PMOS tube P7, a PMOS tube P8, a PMOS tube P9, an NMOS (N-channel metal oxide semiconductor) tube N5, an NMOS (N-channel metal oxide semiconductor) tube N6 and a resistor R1;

the gate of a PMOS transistor P5 is connected to the gate of the NMOS transistor N5 and the source of a PMOS transistor P9 respectively and serves as the input terminal of the substrate potential generating sub-circuit, the source of the PMOS transistor P5 is connected to the VDD power supply, the drain of the PMOS transistor P5 is connected to the drain of the NMOS transistor N5 and the gate of the NMOS transistor N6 respectively, the source of the NMOS transistor N5 is grounded, the source of the NMOS transistor N6 is grounded, the drain of the NMOS transistor N6 is connected to the gate of the PMOS transistor P6, the drain of the PMOS transistor P8 and the drain of the PMOS transistor P9 respectively, the source of the PMOS transistor P6 is connected to the VDD power supply, the drain of the PMOS transistor P6 is connected to the substrate of the PMOS transistor P6, the source of the PMOS transistor P8, the substrate of the PMOS transistor P9, the gate of the PMOS transistor P7, the drain of the PMOS transistor P7 and the substrate of the PMOS transistor P7 respectively, the source of the PMOS transistor P7 is connected to the PMOS power supply, and the drain of the PMOS transistor P7 serves as the output terminal of the substrate potential generating sub-circuit; the grid electrode of the PMOS tube P8 is respectively connected with the grid electrode of the PMOS tube P9 and one end of the resistor R1, and the other end of the resistor R1 is connected with the VDD power supply;

the power chip protection sub-circuit is used for preventing the current at the output end of the power-down protection circuit of the interface chip compatible with the CMOS process from flowing backwards to a power port under the condition that the power supply of the interface chip compatible with the CMOS process is powered down; the substrate potential generating sub-circuit is used for outputting a substrate voltage.

2. A CMOS process compatible interface chip power down protection method based on the CMOS process compatible interface chip power down protection circuit of claim 1, characterized by comprising the steps of:

s1, generating substrate voltage through a substrate potential generation sub-circuit when a power supply of an interface chip compatible with a CMOS (complementary metal oxide semiconductor) process is powered off;

and S2, generating substrate voltage generated by the sub-circuit according to the substrate potential, and controlling the PMOS pipe P4 to be closed to finish power-down protection of the interface chip.

3. The power-down protection method for the interface chip compatible with the CMOS process according to claim 2, wherein the step S1 specifically comprises:

when the power supply of the interface chip compatible with the CMOS process is powered off and the output end of the power-down protection circuit of the interface chip compatible with the CMOS process is externally connected with a high level, the high level of the output end of the power-down protection circuit of the interface chip compatible with the CMOS process is conducted through the PMOS pipe P8 and the PMOS pipe P9 to obtain the substrate voltage Vbias of the high level.

4. The power-down protection method for the interface chip compatible with the CMOS process according to claim 3, wherein the step S2 is specifically:

and providing a substrate potential for the PMOS tube P4 according to the substrate voltage Vbias, controlling the PMOS tube P4 to be non-conductive according to the gate voltage Vy =0V of the NMOS tube N3 and the gate voltage Vz = Vbias of the PMOS tube P4, and cutting off the substrate of the PMOS tube P4 to a power supply path to realize power failure protection of the interface chip.

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