CN217307656U

CN217307656U - Power-on reset circuit suitable for single-chip microcomputer system and single-chip microcomputer system

Info

Publication number: CN217307656U
Application number: CN202221209984.0U
Authority: CN
Inventors: 彭河锦; 夏建宝; 陈志明; 田杰峰; 陈肃; 钟旭恒
Original assignee: Xiamen Pengpai Microelectronics Co ltd
Current assignee: Xiamen Pengpai Microelectronics Co ltd
Priority date: 2022-05-19
Filing date: 2022-05-19
Publication date: 2022-08-26
Anticipated expiration: 2032-05-19

Abstract

The utility model belongs to the technical field of the single chip microcomputer, specifically provide a power-on reset circuit and single chip microcomputer system suitable for single chip microcomputer system, include: the power-on reset detection circuit, the reset signal generation circuit, the reset hysteresis circuit, the reset delay circuit and the output shaping circuit are sequentially cascaded and used for outputting fixed voltage VA; and one end of the power-on reset detection circuit is connected with a power supply VDD, and the output shaping circuit outputs a power-on reset signal. Compared with the traditional reset circuit, the circuit does not need a special manufacturing process, can realize voltage detection and generate reset functions only by using an MOS (metal oxide semiconductor) tube, and saves the area of a chip. And different power-on speed requirements can be met simultaneously. In addition, a hysteresis module is added on the basis of the traditional circuit, the isolation protection effect on power supply noise is realized, the circuit has a simple structure and low static power consumption, the requirements of fast and slow power-on reset and stable secondary reset can be met, and the power consumption of the power-on reset circuit is reduced.

Description

Power-on reset circuit suitable for single-chip microcomputer system and single-chip microcomputer system

Technical Field

The utility model relates to a single chip microcomputer technical field, more specifically relates to a power-on reset circuit and single chip microcomputer system suitable for single chip microcomputer system.

Background

The conventional reset circuit generally has two types, namely an RC reset circuit and a level detection reset circuit.

In the conventional RC reset circuit, as shown in fig. 1, a capacitor is charged when a power supply is powered on, and after stabilization, through R discharge, a high level duration is determined by an RC parameter, and a voltage value corresponding to the high level is determined by the capacitor, the circuit has the advantages of simple structure, low static power consumption, and the like, but the circuit has the following disadvantages: the power-on time in the system is generally in the millisecond level, while in the traditional RC reset circuit, if C is too small, the reset can be finished under the lower power supply voltage, the system can not be normally reset, even if the delay time can be increased by increasing the C value, the C value is too large, so that the area is too large, and the system is inconvenient or cannot be integrated; in addition, due to the residual charge of the capacitor, reset failure is easily caused in the processes of quick power-down, power-up or secondary reset.

In the conventional level detection reset circuit, as shown in fig. 1, when the power supply voltage VDD is greater than the gate terminal voltages of PMOS and NMOS, i.e., VDD > VGSP + VGSN1+ VGSN2, P2 is turned on according to the current mirror principle, charging the capacitor to generate a reset pulse. The circuit has the advantages of simple structure and low static power consumption, but accurate jump decompression (trip-point) cannot be obtained in power-on at different time. The power-on speed of the power supply is different in different application scenes of the single chip microcomputer system, and the jump voltage can be seriously deviated. In addition, the circuit cannot realize undervoltage detection, and has poor secondary reset effect on the system.

SUMMERY OF THE UTILITY MODEL

The utility model discloses the secondary that exists to the traditional reset circuit who exists among the prior art technical problem that resets inefficacy.

The utility model provides a power-on reset circuit suitable for single chip microcomputer system, include:

the power-on reset detection circuit is used for outputting a fixed voltage VA, the reset signal generation circuit is used for generating a reset delay circuit, a reset delay circuit and an output shaping circuit;

the power-on reset detection circuit is connected with a power supply VDD at one end, the output end of the power-on reset detection circuit is connected with the input end of the reset signal generation circuit, the output end of the reset signal generation circuit is connected with the input end of the reset hysteresis circuit, the output end of the reset hysteresis circuit is connected with the input end of the reset delay circuit, and the output end of the reset delay circuit is connected with the output shaping circuit and then outputs a power-on reset signal.

Preferably, the power-on reset detection circuit includes an NMOS transistor M1 and an NMOS transistor M2;

the grid end of the M1 is connected to a power supply VDD, the source end of the M1 is connected with the drain end of the M2 and then output to the next stage, and the grid end of the M2 is grounded.

Preferably, the M2 is a Native MOS tube.

Preferably, the reset signal generating circuit comprises a MOS transistor M3 and a MOS transistor M4;

the grid end of the M3 is connected to a power supply VDD, the source end of the M3 is connected with the drain end of the M4 and then outputs, the grid end of the M4 is grounded, and the grid end of the M4 is connected with the input of the previous stage.

Preferably, the M3 is a Native MOS tube.

Preferably, the reset hysteresis circuit is a schmitt trigger.

Preferably, the reset delay circuit includes a delay circuit, an input terminal of the delay circuit is connected to an output terminal of the reset hysteresis circuit, and an output terminal of the delay circuit is connected to an input terminal of the output shaping circuit.

Preferably, the delay circuit comprises MOS transistors P1, P2, M5 and M6;

the source end of P1 is connected with power supply VDD, and the drain end of P1 is connected with the source end of P2; the drain terminal of P2, the drain terminal of M5 and the gate terminal of M6 are connected and then output to the next stage; the grid end of P1 and the grid end of P2 are connected and then connected with the output end of the previous stage.

Preferably, the output shaping circuit comprises MOS transistors P3, P4, M7 and M8;

the source end of P3 and the source end of P4 are connected with a power supply VDD together, the gate end of P3 is connected with the gate end of M7 and then connected with the output end of the previous stage, the drain end of P3 is connected with the drain end of M7 and then connected with the gate end of P4, the gate end of P4 is connected with the gate end of M8, and the drain end of P4 is connected with the drain end of M8 and then outputs a power-on reset signal.

The utility model also provides a single chip microcomputer system, including the singlechip, the singlechip is including the power-on reset circuit who is applicable to single chip microcomputer system.

Has the advantages that: the utility model provides a pair of power-on reset circuit and single chip microcomputer system suitable for single chip microcomputer system, include: the power-on reset detection circuit is used for outputting a fixed voltage VA, the reset signal generation circuit is used for generating a reset delay circuit, a reset delay circuit and an output shaping circuit; the power-on reset detection circuit is connected with a power supply VDD, the output end of the power-on reset detection circuit is connected with the input end of the reset signal generation circuit, the output end of the reset signal generation circuit is connected with the input end of the reset hysteresis circuit, the output end of the reset hysteresis circuit is connected with the input end of the reset delay circuit, and the output end of the reset delay circuit is connected with the output shaping circuit and then outputs a power-on reset signal. Compared with the traditional reset circuit, the circuit does not need a special manufacturing process, can realize voltage detection and generate reset functions only by using the MOS tube, and saves the area of a chip. And different power-on speed requirements can be met at the same time. In addition, a hysteresis module is added on the basis of the traditional circuit, the isolation protection effect on power supply noise is realized, the circuit has a simple structure and low static power consumption, the requirements of fast and slow power-on reset and stable secondary reset can be met, and the power consumption of the power-on reset circuit is reduced.

Drawings

FIG. 1 is a schematic diagram of a conventional reset circuit;

fig. 2 is a circuit diagram of the power-on reset detection circuit provided by the present invention;

fig. 3 is a circuit diagram of the reset signal generation circuit provided by the present invention;

fig. 4 is a reset hysteresis circuit diagram provided by the present invention;

fig. 5 is a reset delay circuit diagram provided by the present invention;

fig. 6 is a circuit diagram of the power-on reset circuit applicable to the single chip microcomputer system.

Detailed Description

The following detailed description of the embodiments of the present invention is provided with reference to the accompanying drawings and examples. The following examples are intended to illustrate the invention, but are not intended to limit the scope of the invention.

As shown in fig. 1, in the conventional power-on reset circuit, a capacitor is charged when a power supply is powered on, and after stabilization, discharge is performed through R, the duration of a high level is determined by an RC parameter, and a voltage value corresponding to the high level is determined by the capacitor. The circuit has the advantages of simple structure, low static power consumption and the like. However, this circuit has the following disadvantages: the power-on time in the system is generally in the millisecond level, and in the traditional RC reset circuit, if the C is too small, the reset is completed under a lower power supply voltage, and the system cannot be normally reset. Even if the delay time can be increased by increasing the value of C, the value of C is too large, resulting in too large area to be convenient or impossible to integrate; in addition, due to the residual charge of the capacitor, reset failure is easily caused in the processes of quick power-down, power-up or secondary reset.

As shown in fig. 1, in the conventional level detection reset circuit, when a power supply voltage VDD is greater than gate terminal voltages of PMOS and NMOS, i.e., VDD > VGSP + VGSN1+ VGSN2, P2 is turned on according to the current mirror principle, charging a capacitor to generate a reset pulse. The circuit has the advantages of simple structure and low static power consumption, but accurate jump decompression (trip-point) cannot be obtained in power-on at different time. The power-on speed of the power supply is different in different application scenes of the single chip microcomputer system, and the jump voltage can be seriously deviated. In addition, the circuit cannot realize undervoltage detection, and has poor secondary reset effect on the system.

Fig. 2 to fig. 6 show that the present invention provides a power-on reset circuit and single chip microcomputer system suitable for single chip microcomputer system, including: the power-on reset detection circuit is used for outputting a fixed voltage VA, the reset signal generation circuit is used for generating a reset delay circuit, a reset delay circuit and an output shaping circuit; the power-on reset detection circuit is connected with a power supply VDD at one end, the output end of the power-on reset detection circuit is connected with the input end of the reset signal generation circuit, the output end of the reset signal generation circuit is connected with the input end of the reset hysteresis circuit, the output end of the reset hysteresis circuit is connected with the input end of the reset delay circuit, and the output end of the reset delay circuit is connected with the output shaping circuit and then outputs a power-on reset signal. Compared with the traditional reset circuit, the circuit does not need a special manufacturing process, can realize voltage detection and generate reset functions only by using an MOS (metal oxide semiconductor) tube, and saves the area of a chip. And different power-on speed requirements can be met simultaneously. In addition, a hysteresis module is added on the basis of the traditional circuit, the isolation protection effect on power supply noise is realized, the circuit has a simple structure and low static power consumption, the requirements of fast and slow power-on reset and stable secondary reset can be met, and the power consumption of the power-on reset circuit is reduced.

Preferably, as shown in fig. 2, the power-on reset detection circuit is composed of an NMOS transistor M1 and an NMOS transistor M2. The grid end of M1 is connected to power VDD, and the source end of M1 is connected with the drain end of M2 and then output to the next stage; the gate terminal of M2 is grounded. M1 detects the power-on voltage of the power supply, and M2 equivalent resistor and M1 divide the voltage; during the voltage rising process, when the power supply voltage VDD is larger than the gate voltage of M1 and M2, namely VDD is larger than V _THM1 +V _THM2 When M1 is on, voltage V at point A _A Slowly raises until the power supply voltage is stabilized, and generates a fixed voltage V _A 。

Preferably, as shown in fig. 3, the reset signal generating circuit is composed of an NMOS transistor M3 and an NMOS transistor M4, wherein M2 and M3 are both Native MOS transistors. When the power supply voltage is 0, M1. M2 is cut off, and as the power supply rises, the voltage at point A rises continuously, when V is _A ＞V _THM4 When the voltage at the point B is pulled low, the M4 is conducted, and the POR signal is released; when the power supply voltage drops from VDD, M1 gradually changes from a saturation region to a linear region and finally is cut off; the voltage at point A also decreases with the decrease of the power supply voltage, when V _A ＜V _THM4 When M4 is cut off gradually, the voltage at the point B follows the voltage of the power supply VDD due to the characteristics of a Native MOS tube, and the BOR signals are released by M3 and M4. When VDD rises again, M1 and M4 are conducted again, and the processes are repeated to realize secondary reset.

It should be noted that the above mentioned M2 and M3 are not conventional Active tubes, but Native tubes. The Native tube consumes even though, unlike the commonly used enhancement tube, the Native tube is actually a tube with a threshold voltage close to zero, and only needs a small driving voltage to conduct the operation. The M2 and the M3 only need to consume small power consumption and area.

The NMOS transistors M2 and M3 are not limited to depletion mode transistors, and are not particularly limited in this embodiment.

Preferably, as shown in fig. 4, the reset hysteresis circuit is a schmitt trigger. The function is to realize waveform shaping, and the waveform of the reset signal B which changes slowly due to discharging is converted into a steep signal C. It should be noted that the reset hysteresis circuit provided by the present invention is not limited to the schmitt trigger, and the present embodiment does not specifically limit the reset hysteresis circuit.

Preferably, as shown in fig. 5, the reset delay circuit includes a signal delay circuit composed of P1, P2, M5 and M6, and an inverter composed of P3, P4, M7 and M8. The circuit utilizes the gate capacitance of the sixth NMOS transistor M6 and the on-resistances of the first PMOS transistor P1 and the second PMOS transistor P2 to generate an RC time constant, and the time delay can be adjusted by controlling the discharge currents of the P1 and the P2 and the gate capacitance value of the M6 by adjusting the RC time constant. After the signal is delayed, the POR and BOR signals which are needed by stable output, namely power-on reset signals, are finally stably output after buffer shaping of an inverter string consisting of P3, M7, P4 and M8.

The reset delay circuit includes, but is not limited to, a first PMOS transistor P1, a second PMOS transistor P2, a third PMOS transistor P3, a fourth PMOS transistor P4, a fifth NMOS transistor M5, a sixth NMOS transistor M6, a seventh NMOS transistor M7, and an eighth NMOS transistor M8. The source end of P1 is connected with power VDD, and the drain end of P1 is connected with the source end of P2; the drain end of P2 is connected with the drain end of M5; the gate end of the P1 and the gate end of the P2 are connected and then connected with the output end of the previous stage, namely the output end of the Schmitt trigger of the reset hysteresis circuit.

It should be noted that the sixth NMOS transistor M6 is used as a MOS capacitor, and forms a delay module with P1, P2, and M5, and outputs the delayed reset signal to the buffer terminals P3, M7, P4, and M8 for shaping, and finally outputs the power-on reset signal.

Specifically, a source end of P3 and a source end of P4 are connected with a power supply VDD together, a gate end of P3 is connected with a gate end of M7 and then connected with an output end of the previous stage, a drain end of P3 is connected with a drain end of M7 and then connected with a gate end of P4, a gate end of P4 is connected with a gate end of M8, and a drain end of P4 is connected with a drain end of M8 and then outputs a power-on reset signal.

The embodiment of the utility model provides a single chip microcomputer system is still provided, including the singlechip, wherein, the singlechip includes as before the power-on reset circuit who is applicable to single chip microcomputer system.

The power-on and power-off detection of the power supply is realized, the power supply noise is better inhibited through the hysteresis of the threshold value, the undervoltage detection is realized, and the digital reset signal is generated.

Compared with the traditional reset circuit, the circuit does not need a special manufacturing process and only needs the most basic CMOS process; compared with the traditional power-on reset circuit, the circuit is insensitive to the power-on speed of a power supply, can meet different power-on speed requirements simultaneously, is additionally provided with the hysteresis module on the basis of the traditional circuit, realizes the isolation protection effect on power supply noise, has a simple structure, and reduces the power consumption of the power-on reset circuit.

While the preferred embodiments of the present invention have been described, additional variations and modifications in those embodiments may occur to those skilled in the art once they learn of the basic inventive concepts. It is therefore intended that the appended claims be interpreted as including the preferred embodiment and all such alterations and modifications as fall within the scope of the invention.

It will be apparent to those skilled in the art that various changes and modifications may be made without departing from the spirit and scope of the invention. Thus, if such modifications and variations of the present invention fall within the scope of the claims of the present invention and their equivalents, the present invention is also intended to include such modifications and variations.

Claims

1. A power-on reset circuit for a single chip microcomputer system, comprising:

2. The power-on reset circuit suitable for the one-chip microcomputer system as claimed in claim 1, wherein the power-on reset detection circuit comprises an NMOS transistor M1 and an NMOS transistor M2;

3. The power-on reset circuit suitable for the one-chip microcomputer system as claimed in claim 2, wherein the M2 is a Native MOS transistor.

4. The power-on reset circuit suitable for the single chip microcomputer system as claimed in claim 1, wherein the reset signal generating circuit comprises a MOS transistor M3 and a MOS transistor M4;

5. A power-on reset circuit suitable for a system on a chip as claimed in claim 4, wherein the M3 is a Native MOS transistor.

6. The power-on reset circuit for a one-chip microcomputer system according to claim 1, wherein the reset hysteresis circuit is a schmitt trigger.

7. The power-on reset circuit suitable for the one-chip microcomputer system according to claim 1, wherein the reset delay circuit comprises a delay circuit, an input terminal of the delay circuit is connected to an output terminal of the reset hysteresis circuit, and an output terminal of the delay circuit is connected to an input terminal of the output shaping circuit.

8. The power-on reset circuit suitable for the microcomputer-on-chip system as claimed in claim 7, wherein the delay circuit comprises MOS transistors P1, P2, M5 and M6;

9. The power-on reset circuit suitable for the microcomputer-on-chip system as claimed in claim 1, wherein the output shaping circuit comprises MOS transistors P3, P4, M7 and M8;

10. A one-chip microcomputer system comprising a one-chip microcomputer, wherein the one-chip microcomputer comprises the power-on reset circuit suitable for the one-chip microcomputer system as claimed in any one of claims 1 to 9.