CN111007910B - Open-drain output control circuit - Google Patents
Open-drain output control circuit Download PDFInfo
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- CN111007910B CN111007910B CN201911317504.5A CN201911317504A CN111007910B CN 111007910 B CN111007910 B CN 111007910B CN 201911317504 A CN201911317504 A CN 201911317504A CN 111007910 B CN111007910 B CN 111007910B
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- G—PHYSICS
- G05—CONTROLLING; REGULATING
- G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
- G05F1/00—Automatic systems in which deviations of an electric quantity from one or more predetermined values are detected at the output of the system and fed back to a device within the system to restore the detected quantity to its predetermined value or values, i.e. retroactive systems
- G05F1/10—Regulating voltage or current
- G05F1/46—Regulating voltage or current wherein the variable actually regulated by the final control device is dc
- G05F1/56—Regulating voltage or current wherein the variable actually regulated by the final control device is dc using semiconductor devices in series with the load as final control devices
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Abstract
The invention discloses an open-drain output control circuit, which comprises: the first MOS tube and the second MOS tube are electrically connected between a first power supply voltage and a reference potential, the grid electrodes of the first MOS tube and the second MOS tube are connected with the DRV unit, and the DRV unit receives a first enabling signal; the first resistor and the third MOS tube are electrically connected between a second power supply voltage and a reference potential, the grid electrode of the third MOS tube is connected with the drain electrodes of the first MOS tube and the second MOS tube, and the drain electrode of the third MOS tube outputs a second enabling signal; and the second resistor is connected between the grid electrode and the drain electrode of the third MOS tube and used for clamping the second enabling signal within a preset voltage range when the first power voltage is lower than the undervoltage locking voltage. According to the invention, by a method of connecting a resistor across the third MOS tube, a high-level fault of the output enable signal FLAG when the output enable signal FLAG is electrified along with the voltage of the first power supply can be eliminated, the output enable signal FLAG is clamped near Vgs voltage, and the FLAG output is prevented from being triggered by mistake.
Description
Technical Field
The invention belongs to the technical field of open-drain circuits, and particularly relates to an open-drain output control circuit.
Background
In an integrated circuit, an Open Drain (OD) circuit or an Open Collector (OC) circuit is often used, wherein the "drain" and the "collector" correspond to the drain of a MOS transistor and the collector of a transistor, respectively. The open-drain circuit is a circuit which takes the drain electrode of the MOS tube as an output end, can convert a control signal under a certain power supply voltage into a signal under another power supply voltage, and is commonly used for transmitting signals between different power supply modules in the power management chip.
Referring to fig. 1, a schematic circuit diagram of an open-drain output control circuit in the prior art is shown, which includes a PMOS transistor MP1, an NMOS transistor MN1, an NMOS transistor M1, and a pull-up resistor R1, where MP1, MN1, and M1 are internal circuits of a chip, R1 is an external pull-up resistor, MP1 and MN1 are connected between a first power voltage VCC1 and GND, R1 and M1 are connected between a second power voltage VCC2 and GND, a drain of MP1 is connected to a drain of MN1, a gate of M1 is connected to a drain of MN1, a drain of M1 is connected to a pull-up resistor R1, gates of MP1 and MN1 are connected to receive an enable signal EN through a DRV unit (driving unit), and a drain of M1 is used for outputting an enable signal g flab.
As shown in fig. 2 and 3, when EN is equal to 0 after the first power voltage VCC1 reaches the normal operating voltage, MP1 is turned on, MN1 is turned off, M1 is turned on, and FLAG is pulled low; when EN is 1, MP1 is turned off, MN1 is turned on, M1 is turned off, and FLAG is pulled high. The first power voltage VCC1 and the second power voltage VCC2 may be the same power voltage or different power voltages.
Referring to fig. 2 and 3, the reason for the oval dotted line inner waveform outgoing line in the waveform diagram is as follows: the voltage at VCC1 is too low, causing DRV to malfunction, the gate of M1 is not pulled high to ensure M1 is conducting, and M1 is still in the high impedance state, so FLAG is pulled high by R1 to VCC 2.
Whether VCC2 powers up before VCC1 or VCC2 powers up simultaneously with VCC1, there is an undesirable high fault with the output enable signal FLAG, which may cause the FLAG output to false trigger.
Therefore, in view of the above technical problems, it is necessary to provide an open-drain output control circuit.
Disclosure of Invention
The invention aims to provide an open-drain output control circuit to solve the problem of high level fault (glitch) of an output enable signal FLAG.
In order to achieve the above object, an embodiment of the present invention provides the following technical solutions:
an open drain output control circuit, the open drain output control circuit comprising:
the first MOS tube and the second MOS tube are electrically connected between a first power supply voltage and a reference potential, the grid electrodes of the first MOS tube and the second MOS tube are connected with the DRV unit, and the DRV unit receives a first enabling signal;
the first resistor and the third MOS tube are electrically connected between a second power supply voltage and a reference potential, the grid electrode of the third MOS tube is connected with the drain electrodes of the first MOS tube and the second MOS tube, and the drain electrode of the third MOS tube outputs a second enabling signal;
and the second resistor is connected between the grid electrode and the drain electrode of the third MOS tube and used for clamping the second enabling signal within a preset voltage range when the first power voltage is lower than the undervoltage locking voltage.
In one embodiment, the first MOS transistor is a PMOS transistor, the second MOS transistor is an NMOS transistor, and the third MOS transistor is an NMOS transistor.
In one embodiment, the source of the first MOS transistor is connected to a first power voltage, the source of the second MOS transistor is connected to a reference potential, the drain of the third MOS transistor is connected to the first resistor, and the source of the third MOS transistor is connected to the reference potential.
In one embodiment, the preset voltage range is (Vgs- Δ V ), where Vgs is a gate-source voltage of the third MOS transistor, and Δ V is a preset voltage value.
In one embodiment, the resistance R2 of the second resistor satisfies:
Rdson_MN1_max/(R1_min+R2+Rdson_MN1_max)<Vth_M1_max/VCC2_max，
wherein Rdson _ MN1_ max is the maximum resistance of the second MOS transistor when conducting, R1_ min is the minimum resistance of the first resistor, Vth _ M1_ max is the maximum turn-on voltage of the third MOS transistor, and VCC2_ max is the maximum value of the second power voltage.
In one embodiment, the first power voltage and the second power voltage are the same power voltage.
In one embodiment, the first power voltage and the second power voltage are different power voltages.
In an embodiment, a fourth MOS transistor is disposed between the first MOS transistor and the second MOS transistor, and the fourth MOS transistor is configured to block a backward flow path from the second power voltage to the first power voltage.
In an embodiment, when the first power voltage is lower than the under-voltage locking voltage, the fourth MOS transistor is turned off, and when the first power voltage is higher than or equal to the under-voltage locking voltage, the fourth MOS transistor is turned on.
In one embodiment, the DRV unit is connected to an enable signal generation unit, and the enable signal generation unit is configured to generate the first enable signal.
Compared with the prior art, the invention has the following advantages:
according to the invention, by a method of connecting a resistor across the third MOS tube, a high-level fault of the output enable signal FLAG when the output enable signal FLAG is electrified along with the voltage of the first power supply can be eliminated, the output enable signal FLAG is clamped near Vgs voltage, and the FLAG output is prevented from being triggered by mistake;
the backward flowing path from the second power supply voltage to the first power supply voltage can be blocked by the arrangement of the fourth MOS tube.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only some embodiments described in the present invention, and for those skilled in the art, other drawings can be obtained according to the drawings without creative efforts.
FIG. 1 is a circuit schematic of an open-drain output control circuit of the prior art;
FIG. 2 is a timing diagram of a prior art first power supply voltage and a second power supply voltage being the same power supply voltage (VCC2 and VCC1 are powered on simultaneously);
FIG. 3 is a timing diagram illustrating a first power supply voltage and a second power supply voltage of different power supply voltages (VCC2 is powered up before VCC 1) in the prior art;
fig. 4 is a circuit schematic diagram of an open-drain output control circuit in embodiment 1 of the present invention;
fig. 5 is a timing diagram of the first power voltage and the second power voltage being the same power voltage (VCC2 and VCC1 are powered on simultaneously) in embodiment 1 of the present invention;
fig. 6 is a timing diagram of the first power voltage and the second power voltage being different power voltages (VCC2 is powered up before VCC 1) in embodiment 1 of the present invention;
fig. 7a and 7b are specific circuit diagrams of an enable signal generating unit according to embodiment 1 of the present invention;
fig. 8 is a circuit schematic diagram of an open-drain output control circuit in embodiment 2 of the present invention.
Detailed Description
The present invention will be described in detail below with reference to embodiments shown in the drawings. The embodiments are not intended to limit the present invention, and structural, methodological, or functional changes made by those skilled in the art according to the embodiments are included in the scope of the present invention.
The invention discloses an open-drain output control circuit, comprising:
the first MOS tube and the second MOS tube are electrically connected between a first power supply voltage and a reference potential, the grid electrodes of the first MOS tube and the second MOS tube are connected with the DRV unit, and the DRV unit receives a first enabling signal;
the first resistor and the third MOS tube are electrically connected between the second power supply voltage and the reference potential, the grid electrode of the third MOS tube is connected with the drain electrodes of the first MOS tube and the second MOS tube, and the drain electrode of the third MOS tube outputs a second enabling signal;
and the second resistor is connected between the grid electrode and the drain electrode of the third MOS tube and used for clamping the second enabling signal within a preset voltage range when the first power voltage is lower than the undervoltage locking voltage.
The present invention is further illustrated by the following specific examples.
Example 1:
referring to fig. 4, an open-drain output control circuit according to an embodiment of the present invention includes:
the first MOS transistor MP1 and the second MOS transistor MN1 are electrically connected between a first power voltage VCC1 and a reference potential, the gates of the first MOS transistor MP1 and the second MOS transistor MN1 are connected with a DRV unit, and the DRV unit receives a first enable signal EN;
the first resistor R1 and the third MOS transistor M1 are electrically connected between the second power voltage VCC2 and a reference potential, the grid electrode of the third MOS transistor M1 is connected with the drain electrodes of the first MOS transistor MP1 and the second MOS transistor MN1, and the drain electrode of the third MOS transistor M1 outputs a second enable signal FLAG;
the second resistor R2 is connected between the gate and the drain of the third MOS transistor M1, and is configured to clamp the second enable signal within a predetermined voltage range when the first power voltage is lower than an undervoltage lockout (UVLO).
Specifically, in this embodiment, the first MOS transistor MP1 is a PMOS transistor, the second MOS transistor MN1 is an NMOS transistor, and the third MOS transistor M1 is an NMOS transistor. The source of the first MOS transistor MP1 is connected to a first power supply voltage VCC1, the source of the second MOS transistor MN1 is connected to a reference potential, the drain of the third MOS transistor M1 is connected to the first resistor R1, and the source of the third MOS transistor M1 is connected to the reference potential.
The reference potential in the present embodiment is described by taking the ground potential GND as an example, but may be set to another potential in other embodiments.
The DRV unit is connected with the enable signal generation unit, and the enable signal generation unit is used for generating a first enable signal EN.
As shown in fig. 7a or 7b, a specific circuit of the enable signal generating unit may be a comparator, a schmitt trigger inverter (schmitt inverter), or another circuit for determining an analog voltage and converting the analog voltage into a digital signal, and a resistor, a voltage source, or a capacitor is connected between the power voltage VCC and GND to finally generate the first enable signal EN shown in fig. 5 and 6.
As shown in fig. 5 and 6, when EN is equal to 0 after the first power voltage VCC1 reaches the normal operating voltage, MP1 is turned on, MN1 is turned off, M1 is turned on, and FLAG is pulled low; when EN is 1, MP1 is turned off, MN1 is turned on, M1 is turned off, and FLAG is pulled high. The first power voltage VCC1 and the second power voltage VCC2 may be the same power voltage (VCC2 and VCC1 are powered on simultaneously), or may be different power voltages (VCC2 is powered on before VCC 1).
As discussed in the background, the fault voltage in existing circuits can be high, especially when the power-up speed is fast.
The second resistor R2 in this embodiment is connected across the gate and the drain of the third MOS transistor M1, when the first power supply voltage VCC1 is low (lower than the under-voltage-locked voltage), the third MOS transistor M1 and the second resistor R2 form a diode structure, the third MOS transistor M1 is in a saturation operating region, the second resistor R2 can maintain the FLAG voltage within a preset voltage range (Vgs- Δ V ), Vgs is the gate-source voltage of the third MOS transistor M1, and Δ V is a preset voltage value, that is, the FLAG voltage can be maintained near the Vgs voltage.
The second resistor R2 is selected taking into account the following factors:
when EN is equal to 0, the current I consumed by VCC1 is equal to VCC1/R2, so the larger R2, the smaller VCC1 quiescent current;
when EN is 1, the current I consumed by VCC2 is VCC2/(R1+ R2+ Rdson _ MN1), so the larger R2, the smaller VCC2 quiescent current; however, if R2 is too small, M1 may fail to turn off, causing FLAG to go high, with the critical condition Rdson _ MN1_ max/(R1_ min + R2+ Rdson _ MN1_ max) < Vth _ M1_ max/VCC2_ max,
wherein Rdson _ MN1_ max is the maximum resistance of the second MOS transistor MN1 when conducting, R1_ min is the minimum resistance of the first resistor R1, Vth _ M1_ max is the maximum turn-on voltage of the third MOS transistor M1, and VCC2_ max is the maximum value of the second power voltage VCC 2.
3. Considering the power consumption and the area (cost), the resistance of R2 is usually set to be more than hundred k Ω.
Example 2:
referring to fig. 8, in another embodiment of the present invention, an open-drain output control circuit includes:
the first MOS transistor MP1 and the second MOS transistor MN1 are electrically connected between a first power voltage VCC1 and a reference potential, the gates of the first MOS transistor MP1 and the second MOS transistor MN1 are connected with a DRV unit, and the DRV unit receives a first enable signal EN;
the first resistor R1 and the third MOS transistor M1 are electrically connected between the second power voltage VCC2 and a reference potential, the grid electrode of the third MOS transistor M1 is connected with the drain electrodes of the first MOS transistor MP1 and the second MOS transistor MN1, and the drain electrode of the third MOS transistor M1 outputs a second enable signal FLAG;
the second resistor R2 is connected between the gate and the drain of the third MOS transistor M1, and is configured to clamp the second enable signal within a preset voltage range when the first power voltage is lower than an undervoltage lockout voltage (UVLO);
the fourth MOS transistor MP2 is disposed between the first MOS transistor MP1 and the second MOS transistor MN1, and the fourth MOS transistor MP1 is configured to block a backward flow path from the second power voltage VCC2 to the first power voltage VCC 1.
Preferably, the fourth MOS transistor MP2 in this embodiment is a PMOS transistor, the drain of the fourth MOS transistor MP2 is connected to the drain of the first MOS transistor MP1, the source is connected to the drain of the second MOS transistor MN1, and the gate is connected to the external driving voltage.
The embodiment is directed to a case where the first power voltage VCC1 and the second power voltage VCC2 are different power voltages, the VCC2 is powered up before the VCC1, when the first power voltage VCC1 is lower than the under-voltage locking voltage, the fourth MOS transistor MP2 is turned off, and when the first power voltage VCC1 is higher than or equal to the under-voltage locking voltage, the fourth MOS transistor MP2 is turned on, so that a backward flow path from the second power voltage VCC2 to the first power voltage VCC1 can be blocked.
The technical scheme shows that the invention has the following beneficial effects:
according to the invention, by a method of connecting a resistor across the third MOS tube, a high-level fault of the output enable signal FLAG when the output enable signal FLAG is electrified along with the voltage of the first power supply can be eliminated, the output enable signal FLAG is clamped near Vgs voltage, and the FLAG output is prevented from being triggered by mistake;
the backward flowing path from the second power supply voltage to the first power supply voltage can be blocked by the arrangement of the fourth MOS tube.
It will be evident to those skilled in the art that the invention is not limited to the details of the foregoing illustrative embodiments, and that the present invention may be embodied in other specific forms without departing from the spirit or essential attributes thereof. The present embodiments are therefore to be considered in all respects as illustrative and not restrictive, the scope of the invention being indicated by the appended claims rather than by the foregoing description, and all changes which come within the meaning and range of equivalency of the claims are therefore intended to be embraced therein. Any reference sign in a claim should not be construed as limiting the claim concerned.
Furthermore, it should be understood that although the present description refers to embodiments, not every embodiment may contain only a single embodiment, and such description is for clarity only, and those skilled in the art should integrate the description, and the embodiments may be combined as appropriate to form other embodiments understood by those skilled in the art.
Claims (8)
1. An open-drain output control circuit, comprising:
the first MOS tube and the second MOS tube are electrically connected between a first power supply voltage and a reference potential, the grid electrodes of the first MOS tube and the second MOS tube are connected with the DRV unit, and the DRV unit receives a first enabling signal;
the first resistor and the third MOS tube are electrically connected between a second power supply voltage and a reference potential, the grid electrode of the third MOS tube is connected with the drain electrodes of the first MOS tube and the second MOS tube, and the drain electrode of the third MOS tube outputs a second enabling signal;
the second resistor is connected between the grid electrode and the drain electrode of the third MOS tube and used for clamping the second enabling signal within a preset voltage range when the first power voltage is lower than the undervoltage locking voltage;
the first MOS tube is a PMOS tube, the second MOS tube is an NMOS tube, and the third MOS tube is an NMOS tube;
the source electrode of the first MOS tube is connected with a first power supply voltage, the source electrode of the second MOS tube is connected with a reference potential, the drain electrode of the third MOS tube is connected with the first resistor, and the source electrode of the third MOS tube is connected with the reference potential.
2. The open-drain output control circuit according to claim 1, wherein the predetermined voltage range is (Vgs- Δ V ), where Vgs is a gate-source voltage of the third MOS transistor and Δ V is a predetermined voltage value.
3. The open-drain output control circuit according to claim 1, wherein the resistance value R2 of the second resistor satisfies:
Rdson_MN1_max/(R1_min+R2+Rdson_MN1_max)<Vth_M1_max/VCC2_max，
wherein Rdson _ MN1_ max is the maximum resistance of the second MOS transistor when conducting, R1_ min is the minimum resistance of the first resistor, Vth _ M1_ max is the maximum turn-on voltage of the third MOS transistor, and VCC2_ max is the maximum value of the second power voltage.
4. The open-drain output control circuit of claim 1, wherein the first and second supply voltages are the same supply voltage.
5. The open-drain output control circuit of claim 1, wherein the first and second supply voltages are different supply voltages.
6. The open-drain output control circuit according to claim 5, wherein a fourth MOS transistor is disposed between the first MOS transistor and the second MOS transistor, and the fourth MOS transistor is used for blocking a backward flow path from the second power voltage to the first power voltage.
7. The open-drain output control circuit according to claim 6, wherein the fourth MOS transistor is turned off when the first power voltage is lower than the under-voltage-locked voltage, and the fourth MOS transistor is turned on when the first power voltage is higher than or equal to the under-voltage-locked voltage.
8. The open-drain output control circuit of claim 1, wherein the DRV unit is connected to an enable signal generation unit, and the enable signal generation unit is configured to generate the first enable signal.
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| CN201911317504.5A CN111007910B (en) | 2019-12-19 | 2019-12-19 | Open-drain output control circuit |
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| CN201911317504.5A CN111007910B (en) | 2019-12-19 | 2019-12-19 | Open-drain output control circuit |
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| US6301344B1 (en) * | 1997-11-05 | 2001-10-09 | Protel, Inc. | Intelligent public telephone system and method |
| US7023250B2 (en) * | 2004-01-14 | 2006-04-04 | Intersil Americas Inc. | Programmable bandwidth during start-up for phase-lock loop |
| CN103324235B (en) * | 2013-06-09 | 2015-05-20 | 中山大学 | Starting circuit for reference source |
| CN107066007B (en) * | 2017-05-09 | 2018-08-10 | 普冉半导体（上海）有限公司 | A kind of voltage-stabiliser circuit |
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