JP2002204154A - Termination circuit and method thereof - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an active termination circuit for clamping a signal on a transmission line in an electronic device rapidly and effectively. SOLUTION: An active termination circuit is constituted to clamp a signal on a transmission line 306 to one of a first reference voltage level and a second reference voltage level. In one embodiment, the active termination circuit has a bottom clamping transistor 320 coupled to a first potential having a bottom clamp transistor control node arranged for clamping a signal at about a first reference voltage. The active termination circuit also has a top clamping transistor 332 coupled to a second potential having a top clamping transistor control node arranged for clamping a signal at about a second reference voltage.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] The present invention relates to a termination circuit and a method thereof. More particularly, the present invention relates to termination circuits that provide fast and efficient clamping of signals transmitted through transmission lines of electronic systems.

[0002]

2. Description of the Related Art Electronic systems (digital computers,
In the design and implementation of systems using integrated circuits, in particular consumer / industrial electronic devices, etc., there is a particular interest in the undesirable effects on transmission lines.
When a signal travels along a transmission line, for example, wiring on a printed circuit board, reflections may occur on the line. Reflections may result, for example, from mismatched impedance between the drive circuit and the line, causing the signal to reflect in the forward and reverse directions, causing ringing. The effects of these reflections and other undesirable transmission lines are
It often increases as the signal transmission rate increases. Without correction, reflections would cause the voltage of the signal to exceed a voltage level that defines "0" or "1", causing the receiving device to misinterpret the received signal and produce incorrect results. There is.

Various techniques have been tried in the prior art to address the impedance mismatch between the driving (or receiving) circuit and the transmission line. FIG. 1A shows a resistor terminated approach. In that approach, a resistor 102 is inserted between the end of the transmission line and ground or power. The resistance value of the resistor 102 is the transmission line 1
06 is selected to match and prevent reflection, so that the voltage on transmission line 106 is
A value outside the operating range defined for the signal is prevented.

FIG. 1B shows another approach terminated by a resistor. In that approach, an impedance matching resistor 152 is inserted between the drive circuit 104 and the transmission line 106. The impedance matching resistor 152 matches the impedance of the transmission line 106. The system is based on the fact that a signal of 1/2 voltage of the signal propagates down the line and doubles in magnitude and returns to the drive end where it reaches a properly terminated line and stabilizes. I have.

While the resistor terminated approach has been found to be suitable for some systems, it has disadvantages. For example, since a signal is weakened by using a resistor for impedance matching, noise resistance is reduced and power loss is dramatically increased. For example, due to the presence of the resistor 102, a voltage dividing circuit including the resistor is formed between the line 106 and the characteristic impedance of the resistor 102, and the voltage level of the signal in the receiving circuit is reduced.

Further, the presence of the resistor 102 increases the power loss, thereby increasing the load on the drive circuit.
Not only does the amount of power to be supplied from the system power supply increase, but the amount of heat generated also increases. The presence of the resistor 152 in FIG. 1B causes the line to stabilize, but causes an undesirable condition in which the amplitude of the input to other devices connected to the transmission line is halved. Furthermore, it is often difficult to provide impedance matching for a transmission line whose characteristic impedance may change with the configuration of the system. For example, a transmission line that connects to a computer's memory system may terminate in multiple memory slots. Some or all of these slots are occupied, depending on the amount of memory being prepared. As can be seen from the above description, the characteristic impedance of these transmission lines depends on the number of occupied memory slots. Since the impedance of these transmission lines changes, it is difficult to realize impedance matching using a resistor.

[0007] Diode termination matching circuits are another approach to minimizing reflections in the transmission line. FIG. 2 is a simplified diagram of a diode termination matching circuit 200 including diodes 202 and 204. As shown in FIG. 2, the diode 202 is connected between the common termination 206 and one power line voltage (ground voltage in this example). The diode 204 is connected between the common termination 206 and another power line voltage (VDD in this example). As the signal passes through line 106, the voltage on the line increases due to reflection, turning on the diode and clamping the voltage on line 106 to the desired clamp voltage. In the example of FIG. 2, the clamp voltage is “VDD + VTD” and “ground voltage −V
TD ". Here, VTD indicates a forward voltage drop of the diode. A Schottky diode is typically used so that the diode is turned off immediately when the line voltage falls within the desired clamp voltage.

In the diode termination approach, impedance matching is not critical. Therefore, the diode termination approach is suitable for transmission lines where the characteristic impedance can change. It seems that such an approach has been commonly used since the late 1960's. However, as the operating voltage of the electronic device decreases, the diode termination clamp circuit proves to be inadequate. For example, microprocessors and memory circuits using 0.1 micron technology are designed to operate at voltages on the order of 1 volt. Since the forward drop voltage of a Schottky diode is typically about 0.6 V, the diode termination clamp circuit requires a transmission line voltage of 1.6.
Clamping is not started until the swing exceeds the range of V (VDD + VTD) to -0.6 V (-VTD).
In other words, the voltage on the transmission line can change by up to 60% before the clamp starts. Such a large difference between the clamp voltage and the operating voltage makes this diode application ineffective.

Although electronic system manufacturers have long wanted a termination circuit design that provides efficient clamping of modern high speed, low voltage signals and is easy to implement, most attempts have been made to use diode termination. Improvements have been made to approaches (eg, by attempting to reduce the diode forward bias voltage in diode termination solutions) and resistor termination approaches. This is because the task of addressing impedance mismatch at the board level is typically assigned to a VLSI digital engineer who is more knowledgeable in digital system technology than a complex analog line termination. When analog engineers are assigned to do the work, they are usually more familiar with analog circuits, such as diodes and resistors, than VLSI design principles. For example, if the diode drop is too large, engineers typically adopt a policy of changing to a termination system with resistors. Thereby, as described above, the power loss is increased, and also the performance of the system is affected.

[0010] With current manufacturing techniques, reliable zero voltage forward bias diodes have not yet been obtained.
Therefore, current diode termination designs are still
Not suitable for use in modern low voltage circuits. Moreover, even with such diodes, diode termination clamp circuits cannot be easily integrated into modern CMOS (complementary metal oxide semiconductor) receiving or driving circuits such as microprocessors and memory circuits. (In this regard, the same applies to the resistor termination clamp circuit). Typically, these approaches require that the termination circuit be implemented as a separate stand-alone chip. For example, like a small or portable electronic system,
In designs where there are demanding restrictions on the shape, this requirement is greatly disadvantaged because it requires additional space on the circuit board and increases costs.

In view of the foregoing, there is a need for an improved termination circuit and method that advantageously provides fast and efficient clamping of signals transmitted through transmission lines in electronic systems, particularly signals having a low operating voltage range. It is rare.

[0012]

SUMMARY OF THE INVENTION In one embodiment, the present invention describes an active termination circuit for clamping a signal on a transmission line in an electronic device. The active termination circuit is
A lower clamp transistor having a lower clamp transistor control node configured to clamp a signal near a first reference voltage and connected to a first potential, and configured to provide a first reference voltage. A lower threshold reference transistor connected to the first reference voltage source. The first threshold reference transistor supplies a lower bias transistor control node with a first bias voltage that biases the lower clamp transistor control node near a first threshold voltage that is greater than the first reference voltage. The first threshold voltage is a threshold voltage of the lower clamp transistor. The active termination circuit also includes an upper clamp transistor control node configured to clamp the signal near a second reference voltage, an upper clamp transistor connected to a second potential, and a second reference voltage. An upper threshold reference transistor connected to a second reference voltage source configured to supply. The upper threshold reference transistor supplies the upper clamp transistor control node with a second bias voltage that biases the upper clamp transistor control node near a second threshold voltage smaller than the second reference voltage. The second threshold voltage is a reference voltage of the upper clamp transistor threshold voltage.

[0013] In another embodiment, a method is described for clamping a signal on a transmission line to one of a first and a second reference voltage.

[0014] These and other advantages of the present invention will become apparent from the following detailed description and the various drawings.

[0015]

BRIEF DESCRIPTION OF THE DRAWINGS The invention will now be described in detail with reference to several preferred embodiments illustrated in the associated drawings. In the following description, numerous specific details are set forth in order to provide a thorough understanding of the present invention. It will be apparent, however, to one skilled in the art, that the present invention may be practiced without some or most of these specific details. In other instances, well-known process steps or structures have not been described in detail so as not to unnecessarily obscure the present invention.

According to one embodiment of the present invention, there is provided an improved active termination circuit for clamping a signal traveling on a transmission line of an electronic system. An advantage of the improved active termination circuit is that it uses active devices (eg, transistors) to promote high speed operation and low power consumption and to clamp signals. Unlike prior art diode termination clamp circuits, the active termination circuit of the present invention is configured to provide sufficient clamping at or near the power line voltage of the signal, thereby simulating the effect of a zero threshold diode. Thus, it is compatible with the use of modern electronic devices for low voltage signals while retaining compatibility with high voltage devices.

In the embodiment shown, the invention comprises a first node connected to a transmission line and a first gate connected to a first stable voltage source via a first stabilizing capacitor. And a first clamp transistor having a node. The circuit further includes a gate threshold potential excursion at either the first or second gate node,
A second node having a second node connected to the transmission line and a second gate node connected to the second stable voltage source such that the voltage is substantially reduced as compared to the case where no stabilizing capacitor is present. 2 clamp transistors.

To further illustrate the advantages and features of the present invention,
FIG. 3 illustrates a termination circuit 300 of the present invention for terminating a signal traveling on a transmission line of an electronic system according to one embodiment of the present invention. As shown in FIG.
0 comprises an upper active clamp device 302 and a lower active clamp device 304. In the embodiment of FIG. 3, the upper active clamp device 302 is implemented by a p-type MOS device 332 and the transmission line 306
Is clamped near the upper power supply line voltage (for example, VDD). On the other hand, the lower active clamp device 304 is realized by an n-type MOS device 320, and has a function of clamping a signal on the transmission line 306 to a vicinity of a lower power supply line voltage (for example, a ground voltage or GND). As defined herein, the upper device is used to clamp the voltage level of the signal on the transmission line to an upper range (eg, near VDD), and the lower device is used to clamp the voltage level of the signal to the lower range (eg, near VDD). For example, it is used for clamping around the ground voltage.

The source of the MOS device 332 is connected to VDD, and the source of the MOS device 320 is connected to the ground line. As shown, the drains of both devices 332 and 320 are both connected to transmission line 3
06. Here, looking at the lower active clamp device 304, the gate 3 of the MOS device 320
14 is connected to both the gate and the drain of the lower threshold reference device 312. As shown in FIG. 3, the lower threshold reference device 312 has an n-gate-to-drain connection.
A type MOS device 318 will be provided.

A sufficient current is supplied to the n-type MOS device 318
(Current can be sourced from any conventional current generator, which is shown in FIG. 3).
The gate 314 of the lower active clamp device 304 is biased near a threshold voltage of one of the n-type MOS devices 318 above ground voltage. Typically, the voltage at gate 314 is n
The threshold voltage VT of the MOS device 318 is
18 is biased to the sum of the small overdrive voltage required to maintain the current through. The current source 316 is either a constant current source or a variable current source (VCS) depending on the application in which the termination circuit 300 is used.

The signal on transmission line 306 begins to reflect,
When the voltage drops below the ground voltage, that is, as soon as the potential difference between the gate and the source of the n-type MOS device 320 of the lower active clamp device 304 exceeds VT, the n-type device 320 is turned on as shown in FIG. To start supplying current from the drain connected to the ground line. Therefore, the signal is clamped near or slightly below ground voltage. As described above, the n-type device 320
Gate 314 is typically biased slightly above VT. Thus, n-type device 320 typically begins to conduct when the signal on transmission line 306 becomes greater than the ground voltage. Thus, n-type device 320 is completely turned on when the signal on transmission line 306 falls below ground voltage.

N-type device 318 and n-type device 320
Can be formed on the same die, so their threshold voltages VT are substantially equal regardless of process differences. Therefore, the n-type device 320 has a gate potential biased by the VT of the n-type device 318, and easily as soon as the signal on the transmission line 306 falls below (or near) the ground voltage. Can be turned on.

The p-type M of the upper active clamp device 302
Referring to gate 330 of OS device 332, a similar configuration exists. Gate 330 is connected to the gate and drain of p-type MOS device 334. As shown, the source of the p-type MOS device 330 is VD
D. When a sufficient voltage flows to the drain of the p-type device 334, the gate 3
30 is biased near VDD-VT. However,
VT is the threshold voltage of the p-type MOS device 334.
In practice, the gate 330 of the p-type device 332 is biased slightly below this value (VDD-VT) because there is an overdrive voltage required to maintain the current through the p-type MOS device 334.

The signal on transmission line 306 begins to reflect,
When the voltage rises above VDD, the p-type MOS device 33
2 turns on and clamps this signal near VDD. Since the above-mentioned overdrive voltage exists, p-type M
OS device 332 is normally turned on shortly before the voltage level of the signal on transmission line 306 reaches VDD, so that when the voltage level of the signal exceeds VDD, p.
It is guaranteed that the type MOS device 302 is completely turned on. Again, since both p-type devices 332 and 334 may be fabricated on the same die, their threshold voltages VT will be substantially equal regardless of process differences.

When turned on, the p-type MOS device 332 and the n-type MOS device 320 have their clamp impedance substantially lower than the characteristic impedance of the transmission line 306 (eg, about 50 in one embodiment).
It is preferable that the size is determined so as to reduce the ohm. In some cases, due to the parasitic capacitance between the drain and the gate of the n-type device 320, the voltage of the gate 314 may change when the voltage level of the signal on the transmission line 306 changes (the n-type MOS device 318). The impedance at the destination node 344 is typically very large because there is little current flowing through the n-type MOS device 318). In this case, it is advantageous to stabilize the voltage level of the gate 314 of the n-type MOS device 320 using an appropriate voltage stabilizing circuit.

In one embodiment, node 344 may be of an appropriate size (eg, about one to one drain-to-gate parasitic capacitance).
(0x) is considered to be connected to an internal or external capacitor. Since a similar problem exists with respect to node 342, a similar voltage stabilization circuit is used to ensure that p-type MOS device 332 is turned on when the signal on transmission line 306 exceeds power supply line voltage VDD. To the node 342 is an advantage.

As understood by those skilled in the art, the termination circuit 3
The advantage of 00 is that the voltage on the terminated transmission line is clamped to the power line voltage as soon as the signal voltage is about to exceed the power line voltage. Through the use of threshold reference devices (devices 310 and 312), upper active clamp device 302 and upper active clamp device 304 function as "zero threshold" transistors. That is, they clamp as soon as the voltage of the signal exceeds VDD and ground. The above facts make the approach far more difficult since the prior art diode termination approach cannot start clamping until the voltage of the signal exceeds the power supply line voltage by the forward voltage drop of the electrodes (eg, typically about 0.6V). This is an advantage over. Therefore, the active termination circuit of the present invention is well suited for use with modern low voltage signals.

The termination circuit shown in FIG. 3 may be made in an external termination component (eg, placing multiple termination circuits 300 on separate chips for use with existing receive / drive circuits). May be). The termination circuit 300 is a CM
It can be easily integrated into a CMOS receiving or driving circuit such as an OS microprocessor or a CMOS memory device, and in this case, similar advantages are obtained. Conventional VL
Since the terminating circuit 300 can be easily incorporated into the CMOS receiving or driving circuit using the SI design method, the signal terminating process is facilitated. Moreover, CMOS
Since few, if any, additional process steps are involved in the manufacture of the receiving or driving circuit, a long-felt need in the industry is solved. That is, if the termination circuit could be incorporated into an existing receiving or driving circuit, the need for external termination components would be eliminated, thereby saving space on the circuit board. The space issue has been quite pressing for designers of small form factor electronic systems (eg, portable computers, portable electronic devices, etc.).

Further, the termination circuit 300 consumes significantly less power than the resistor termination solution shown in FIGS. 1A and 1B. Although the p-type device 334 and the n-type device 318 of the threshold reference device are always on, these devices need only to supply enough current to maintain the threshold voltage of the gates 330 and 314. A small current (for example, 1 to 2 mA, typically 1/20 of the current consumed in FIG. 1A) may be configured to flow. MOS device 3 of clamp device
When clamps 32 and 320 are turned on (ie, the voltage level of the signal on transmission line 306 exceeds the power supply line voltage), the low clamp voltage minimizes power consumption. These features make termination circuit 300 particularly suitable for use in battery operated electronic systems.

It will be further appreciated that the use of active devices in the termination circuit 300 results in faster clamping. The termination circuit 300 is essentially tuned because the clamping occurs as soon as (or shortly before) the voltage level on the transmission line 306 exceeds the power line voltage and is essentially independent of the characteristic impedance of the transmission line. Not required. Therefore, the termination circuit 300 is extremely suitable for use in a case where the characteristic impedance changes with the configuration of an electronic system (for example, a data line connected to a memory bank).

The embodiment of the active termination circuit proposed in FIG. 3 is particularly suitable for use in combination with a CMOS tristate circuit. As an example, FIG.
4 shows a tri-state termination circuit 400 having an input receiver 4, an input receiver 414, and a tri-state control signal. Node 406
Is connected to a bias voltage of about VDD-VT (generated by the voltage reference block 410) instead of VDD, and the node 408 has a bias of about + VT (generated by the voltage reference block 412) instead of the ground voltage. When connected to a voltage, the tristate circuit 416 also functions as a termination circuit for clamping the voltage level of the signal on the transmission line 402 when the control signal sets the tristate circuit 416 to a “tristate” mode. it can.

For example, the upper threshold reference device 31 shown in FIG.
Note that zero node 342 may be used as a reference voltage for node 406 of FIG.
Similarly, another embodiment of the voltage reference circuit 410 may be used to provide a bias voltage to the node 406 of FIG. Similarly, the lower threshold reference device 312 of FIG.
May be used as a reference voltage for node 408 of FIG. Similarly, another embodiment of voltage reference circuit 412 may be used to provide a bias voltage to node 408 of FIG. Although FIG. 4 illustrates one particular implementation of an active termination tristate circuit, those skilled in the art will appreciate that the techniques disclosed herein are applicable to other tristate designs. right.

The technique described above is equally applicable to drivers that are not tristated. Since a circuit such as that shown in FIG. 4 or a similar circuit can be easily incorporated into an existing CMOS input / output circuit, the driving circuit includes a driver (tri-state or non-tri-state).
And the function of the termination circuit can be provided with a minimal design and / or minimal additional space on the die.

FIG. 5 illustrates a bipolar implementation of the active termination circuit of the present invention, according to one embodiment of the present invention. The operating principle of the termination circuit of FIG. 5 implemented using bipolar technology is the same as that of the termination circuit of FIG. 3, except for the upper and lower clamp devices and the upper and lower threshold reference devices of FIG. Similar. The bipolar technology allows the termination circuit to be easily integrated into the bipolar receiving / driving circuit (of course, the termination circuit of FIG. 5 can work with existing electronic devices even with a stand-alone implementation). ). In addition, bipolar technology has several advantages, for example, high speed, small size, and the like. Furthermore, bipolar terminations may have lower effective impedance than CMOS implementations.

According to FIG. 5, npn transistor 504
A lower threshold setting device comprising: Transistor 504 is configured to be connected between the collector and the base, the emitter is connected to the ground line, and the base is connected to the base of npn transistor 506 of lower clamp device 508. The lower threshold device 502 sets a voltage of about + VBE above ground voltage to np when sufficient current flows through npn transistor 504.
It has the function of supplying to the base of an n-transistor 506 (current is supplied to the collector of an npn transistor 504 used as a conventional power supply transistor,
This power supply configuration is symbolized in FIG. 5 as a current source 524).

The npn transistor 506 is connected to the transmission line 5
When the voltage level on 20 drops slightly below ground, it begins to conduct, thereby clamping the voltage near ground. Again, since there is a small overdrive voltage to maintain the conduction of transistor 504,
The base of npn transistor 506 is biased slightly above + VBE, and shortly before the voltage of the signal reaches ground voltage, npn transistor 506 turns on. Thus, when the signal voltage drops below the ground voltage,
Transistor 506 is guaranteed to be completely on.

It should be noted that the fact that the npn transistor 506 is connected to VDD instead of the ground line has the advantage that the npn transistor 506 is surely turned off before clamping starts. If the collector of transistor 506 is connected to the ground line, then due to the high β of this transistor, a considerable amount of current will flow even when the voltage level of the signal on transmission line 520 is within the power supply line voltage. Power consumption will increase significantly.

The pnp transistor 530 connected between the collector and base of the upper threshold device 534 biases the voltage at the base of the pnp transistor 540 of the upper clamp device 542 to about VDD-VBE.
If the voltage of the signal on transmission line 520 exceeds VDD (or just below VDD in the presence of an overdrive voltage that maintains conduction in transistor 530), p
The np transistor 540 is turned on, and clamps the voltage level to about VDD.

Due to the base-emitter parasitic capacitance of transistors 506 and 540, additional voltage stabilization circuits are connected to the gates of these transistors so that when the voltage level on transmission line 520 changes, these transistors In some cases, it may be necessary to ensure that the clamps are securely clamped. Conventional voltage stabilization approaches, including those described in connection with FIG. 3, may be used for voltage stabilization.

The termination circuit of FIG. 5 requires no adjustment and can be flexibly mounted (independent type or embedded in a driving / receiving circuit), and as described with reference to FIG. It should be understood that it has a low clamp voltage characteristic. However, the power consumption of the termination circuit of FIG.
It is slightly higher than the termination circuit of FIG. This means that when the voltage of the signal exceeds VDD, the current will flow to the ground terminal (unlike VDD in FIG. 3), ie the pnp transistor 540
Because it is supplied from the collector end. Since the voltage applied to the transistor 540 when energized increases, it is considered that power consumption increases. Similarly, when the voltage of the signal exceeds the ground voltage, the current becomes VDD (unlike ground in FIG. 3), ie, the npn transistor 5
06 from the collector end. Since the voltage applied to the transistor 506 when the power is turned on increases, it is considered that power consumption increases.

FIG. 6 shows another CMOS embodiment, in which the upper clamp device 6 is shown.
A p-type device 602 at 04 is connected to the ground line (instead of VDD in FIG. 3). Conversely, the n-type device 606 of the lower clamp device 608 is connected to VDD instead of the ground line. The rest of the termination circuit of FIG. 6 is substantially the same as the termination circuit shown in FIG.

When the voltage level on transmission line 620 drops below ground (or approaches ground when the overdrive voltage described above is present), the current that clamps the voltage to ground is: It flows from VDD instead of the ground voltage (in the case of FIG. 3). Conversely, transmission line 6
If the voltage level on 20 exceeds VDD (or approaches VDD due to the presence of the overdrive voltage described above), the current that clamps the voltage to VDD is reduced to ground instead of VDD (in FIG. 3). Flow from the line. FIG.
This configuration, similar to, ensures that the p-type device 602 and the n-type device 606 are more completely turned off when the voltage level on the transmission line 620 is within the power supply line.

Furthermore, during clamping, a large voltage is applied from the drain to the source of these transistors. The increase in conductivity makes it possible to reduce the size of these transistors, which has the advantage of reducing the area and capacitance, and also leads to higher speed. The termination circuit shown in FIG. 6 requires no adjustment and is flexible (independent type or built-in type in the driving / receiving circuit).
It should be understood that it has the low clamping voltage characteristics described above in connection with FIGS. However, higher voltages on clamp transistors 602 and 606 during clamping will increase power consumption. As already mentioned, in order to ensure that the upper clamp device 604 and the lower clamp device 608 clamp even when the voltage level on the transmission line 620 changes, the above-described voltage stabilization may be performed in some cases. A circuit may be connected to the gates of transistors 602 and 606.

<Additional Discussion, Examples, and Applications> In order to clarify the theory and application of the present invention, an additional explanation will be given below with the aim of supplementing understanding. In particular, issues including impedance mismatch will be discussed in more detail to facilitate an understanding of the difficulties inherent in prior art approaches and the advantages of the present invention.

Electronic systems such as computers, consumer / industrial electronic devices, especially integrated circuits (ICs)
In the design and implementation of systems using, the problem of transmission line termination is a major problem. When a signal travels along a transmission line and an impedance mismatch occurs at the end of the line, the signal reflects at the end, reciprocates on the line, and causes a phenomenon generally called ringing.

A typical solution to this problem is to terminate the transmission line with an impedance equal to the characteristic impedance of the line. The problem with this is that in such systems, the power loss of the system increases, the required circuit drive capacity increases, and the problem with other devices connected along the line, i.e., depends on the solution chosen. There are a number of other issues that may arise.

As a result, designers prefer logic systems that do not require such termination. When TTL (transistor-transistor logic) circuits were becoming more common, designers did not use terminations,
Suffered from severe ringing and noise problems. Building large systems has been almost impossible.

Another approach is to use a TTL circuit having a clamp diode on the input side. Since these diodes do not affect the termination impedance within the operating range of the device, they do not consume extra power and the waveform at the input side is a clamp voltage (usually the forward drop voltage of the power line voltage diode). As soon as the threshold was exceeded or exceeded, the diode clamp was activated, clamping the reflection and retaining the operating signal within a predetermined level. The basic concept of such a termination system is that a non-linear termination device that provides proper termination outside of the standard operating range and maintains a high characteristic impedance within the operating range can be used.

FIG. 7 shows a general circuit configuration that applies to all of the following descriptions. A circuit for driving a transmission line with a receiving device at the opposite end is shown. The dashed box indicates termination clamp or other form of application at the receiving end.

FIGS. 8A and 8B illustrate the problem and show a conventional C without a special diode clamp.
Indicate the MOS or TTL situation (note in particular the following analysis and discussion of the falling waveform shown here and the lower half of all clamp circuits. However, the same applies to the rising waveform and the upper half of the clamp circuit). Discussion is possible.)

FIG. 8A is a voltage-current correlation diagram showing a phenomenon that occurs electrically in the transmission line. When a 50 ohm transmission line is first stabilized at 5V (right side of "Start" in FIG. 8A) and the driver output is turned on (transition to "output low"), the waveform of the current flowing through the line is: This is shown visually by drawing a 50 ohm impedance line from the "start" point to intersect the driver's output impedance curve (crossing point "A"). In this case, the output voltage first drops to about 0.9 V, and a current waveform of about 80 mA is sent to the transmission line. In this description, the polarity of the current is positive when the current flows through the transmission line from the receiver to the driver. With respect to voltage, the convention is to refer to positive from the ground line.

When the drawing method is changed, the same transition is obtained as shown in FIG.
It can be shown as follows. Each rectangle along the "t" (time) axis represents one trip of the waveform flowing forward or backward through the transmission line. Therefore, after one transmission time (one rectangle) when the output voltage first drops to the voltage at the point “A”, the receiving end starts to change.

The equilibrium point at the receiving end (the balance between the waveform reaching the receiving end and the load impedance) is indicated by drawing a 50 ohm impedance line from point A to intersect the receiving gate impedance curve. It is.
Therefore, when the drive side changes from 5V to 0.9V,
A reflection is sent back to the drive side, which is indicated as a change from 5V at the receiving end to -2.5V (point "B"). Point "C" crossing the drive end again
It can be seen that pulling a 50 ohm transmission line towards the end of the line would expect the output of the driver to be driven to about -0.3 volts by another current sent through the line towards the receiving end. Each of these state transitions is shown in FIG. 8B at the appropriate time intervals.

When the reflection from the output (point "C") returns to the receiving side (point "D"), a problem arises because the new reflection raises the receiving side to the 0.9V range (point "D"). In the worst case, it exceeds the noise level of the receiving device, possibly causing an erroneous signal. This can cause the receiving device to misinterpret the input voltage and generate incorrect data.

By arranging the Schottky diode in parallel with the receiving device as shown in FIG. 9, the input characteristics of the receiving device are complemented to a normal state. The waveform of the current in the first transition is the same as that of FIG. 8A, but the input voltage does not become an excessively negative value due to the fact that the clamp operation of the diode changes the equilibrium point of the receiving end. Note that the energy returning on the line has been reduced by this. Eventually, the receiving device will not receive the detrimental positive voltage reflection in the previous example.

FIG. 10 shows a characteristic in a case where a resistor is inserted in series with the Schottky diode as a special case of the state of FIG. The resistance values are chosen and selected such that the equivalent impedance at the equilibrium point exactly matches the 50 ohm transmission line. In this state, the amount of reflected current returning from the receiving end to the transmission line is just the amount required for the reflection to be stable by one reflection of the transmission line.

Apart from whether this approach is a practical alternative in a real situation (though it is necessary to fully understand the characteristics of both the driver and the transmission line), the above analysis From the following, it is understood that: That is, if the composite characteristic impedance of the device on the receive line outside the operating range is greater than the impedance of the transmission line at the equilibrium point, the system will eventually have a reflection that causes a positive reflection into the device operating range. , Probably causing noise problems. Conversely, if the composite characteristic impedance at the receiving end at the equilibrium point is smaller than that of the transmission line, no positive reflection occurs. Furthermore, the closer the match between the transmission line and the termination at the equilibrium point, the sooner the system will settle.

However, other issues need to be considered. First, the equilibrium point is a function of all states preceding it, in particular the initial starting voltage of the system. But more importantly, perhaps, is that the effective impedance of the diode changes with current. Since the operating range of the Schottky diode below 0.5V exhibits a very high equivalent impedance, the equilibrium point in that region can cause unwanted reflections.

FIG. 11 illustrates this point. Here, the operating voltage is reduced to 1V (close to the crossover point for Schottky diode effectiveness if operating at 3V). In this case, the equilibrium point at the receiving end of the transmission line exists in a region where the equivalent impedance of the diode is high, and a proportionally high level of reflection returns along the transmission line. As shown, such a situation can have catastrophic consequences. Since the impedance of the diode is very high in the low voltage region,
The problem of reflection becomes greater than in the case of the TTL circuit before the introduction of the clamp diode.

Since the reflection problem exists in the circuit design using the diode, especially at a low voltage, the designer is again paying attention to the resistance termination system. However, employing a resistive termination system results in significant power losses. This is an important issue that cannot be overlooked, especially in portable or other small systems. Also, obtaining accurate termination is difficult for board-level engineers, especially if the bus line in question includes sockets with varying numbers of loads that change the effective impedance.

FIG. 12 shows the characteristics of a new type of termination that operates at low voltages, while taking advantage of the low power of diode termination. There, "zero threshold" transistors, or even those with slightly negative threshold values, are used for termination. Please refer to FIG.
Within the active area of the bus operation, these devices draw some current (probably 1-2 mA (milliamps)). However, in this example, the value is extremely low as compared with the current of 20 mA or more that is typically consumed by the terminating resistor. However, the voltage of the transmission line is
Upon reflection out of the operating range, the zero threshold device
Turns on, providing a very smooth turn-on.

In such a system, much power can be saved. In addition, the system could ultimately be integrated into the IC itself, using two additional implants and masking steps as needed. In addition, diode termination is very useful for applications such as memory buses where different numbers of cards are inserted.
In such an application, it is very difficult to accurately determine the termination impedance. Therefore, when the diode class is used, a circuit design basically requiring no adjustment is made. If other receiving devices perform more clamping / termination operations, the diode will suppress operation. Also, diodes are not sensitive to the exact characteristic impedance of the transmission line. In addition, since the termination using a resistor network with high power consumption is not required, the chip designer can use a small drive circuit to reduce the load, and enough to increase the inherent noise margin. Large power line voltages can be used.

One of the disadvantages of diode termination is that "n
T "class. Here, n is the number of bus transitions required until the bus is sufficiently stable for further operation. Parallel termination is a 1T type termination device in which all points of the transmission line are terminated accurately and reflections are not allowed. The series termination is a 2T termination. This termination is such that when the signal propagated on the transmission line is reflected and doubled and returns to the power supply side, the reflection becomes a half-height wave so that the signal has a size comparable to the setting. I have to. In either case, although theoretically, the inaccuracy of the termination usually requires more stabilization.

In a first approximation, the diode must reflect back to the receiver after the waveform has propagated through the transmission line and returned to the power source before the bus was effectively stabilized.
+ T termination device. Therefore, if the operating frequency of the bus is higher than the length of the bus, the bus may not be completely stabilized when the next transition occurs. Under such circumstances, the line voltage will vary slightly from transition to transition, causing obvious edge jitter in the signal. This is when transitioning from one cycle to another,
This happens because the output can have a slightly higher or lower voltage. In today's systems with fast rise and fall times, this is probably less than a tenth of a nanosecond, but must be considered in any case.

One advantageous use of this termination is in SD
It can be found on a memory bus as used on RAM. In the SDRAM, the load characteristics change depending on the number of inserted devices, and the voltage swing is expected to be high as a standard component. However, if the bus length is not too long compared to the operating frequency and edge jitter is not critical, it could be used in almost any type of system.

However, there is a problem in mounting. If the threshold value of the "zero threshold" device is very close to 0V, there is no significant problem. However, the region of interest is in the range 0V-3V. The standard deviation of the threshold value of the CMOS process is ± 0.2V. Differences in the process suggest that the diode can assume a state from non-conductive to highly conductive within its operating range. this is,
Will not be acceptable in many applications.

FIG. 14 shows an example of circuit design for solving this problem. In this case, the gate of the clamp transistor is connected not to the power supply line, but to a reference voltage designed to track the threshold voltage deviation. therefore,
When the threshold voltage is on the high side, the gate node is biased higher. If the threshold voltage is low, the gate will be biased lower. As a result, when the voltage on the clamp reaches one of the power line voltages, the transistor is properly biased to provide the proper impedance characteristics and behaves like a zero threshold device. There will be some conduction through the clamp transistor, but as discussed above, this will be very small compared to the current when resistive termination is used.

FIG. 15 shows a bipolar implementation of the termination circuit of the present invention. In FIG. 15, the clamp transistor is non-conductive during the standard operating range of the bus and is biased to provide a clamping operation outside the power supply range. Occasionally, a bipolar circuit has a lower effective impedance than a MOS device.

This could be used in two ways. First, for some applications, a low clamping voltage is desirable. However, in other cases, it may be desirable to optionally include the series resistor shown in FIG. 15 to simply provide an impedance that stabilizes the transmission line. When used in low voltage systems (2.5V or less), the initial undershoot voltage may be on the order of -0.75V. Such a magnitude of voltage would not significantly forward bias the receiving device's substrate diode, but if it did, it would cause stored charge problems. If you have a resistor,
Will stabilize almost instantly. If the supply voltage is low, there will be no problem with the magnitude of the undershoot. Bipolar systems may be suitable for such systems. The bipolar system also has the advantage that there is no bias current through the output device when the operating level of the transmission line is within power supply limits.

Finally, a completely equivalent circuit to a bipolar circuit can be made using CMOS technology. Incorporating clamps in integrated circuits is a suitable alternative and would provide near the performance of bipolar devices. Also, it typically does not have a current drain within the operating range.

The advantageous applications of these clamps are potentially twofold. One is an independent device (eg, 1 /
4 size small outline package, ie QSOP
(Device) in a system where the original device does not have such a clamp circuit. Alternatively, it is expected that this class of clamp will be added to all CMOS integrated circuits manufactured.

Additional Embodiments of the Invention As is well known to those skilled in the art, all junction-type devices (including transistors) have a unique parasitic capacitance formed between various junctions, commonly referred to as parasitic capacitance. have. One such parasitic element, particularly relevant to the termination circuit of the present invention, is the MO
It is called SFET capacitance. These parasitic elements mainly cause the inherent delay of the logic gate. FIG.
Shows a typical MOSFET 1600 with an associated junction parasitic capacitance represented as a lumped element between device terminations. Based on physical origin, parasitic capacitances can be classified into two main groups: (1) oxide-related capacitances, and (2) junction capacitances. In the example shown, the gate-oxide related capacitances are Cgd (gate-drain capacitance), Cgs (gate-source capacitance), Cgb
(Capacitance between gate and substrate). It is well known to those skilled in the art that the gate-channel capacitance is distributed and voltage dependent so that all of the oxide-related capacitances described herein change with the state of the transistor bias. Note that the overall gate oxide capacitance is primarily determined by the parallel plate capacitance between the gate and the underlying structure. Therefore, the size of the oxide-related capacitance is (1)
It has a very close relationship with gate oxide thickness and (2) MOSFET gate area.

Usually, the parasitic capacitance Cg between the gate and the drain
d1 (for transistor 332) and Cgd
2 (for transistor 320) degrades the clamping performance of termination circuit 300 by changing the gate voltages of clamp transistors 332 and 320 in relation to the rise or fall of the input voltage on transmission line 306. Sometimes, the change in gate voltage is about 200 mV
(Millivolts). However, by providing the stabilizing capacitors 1702 and 1704, it is possible to suppress the change in the gate voltage to about 50 mV.

With this in mind, FIG. 17 illustrates a termination circuit 1700 having stabilizing capacitors 1702 and 1704 in accordance with an embodiment of the present invention. In the embodiment shown, ballast capacitors 1702 and 170
Reference numeral 4 is used for compensating the parasitic capacitance between the gate and the oxide. It should be noted that termination circuit 1700 is one possible embodiment of termination circuit 300 shown in FIG. 3, and therefore should not be considered as limiting the scope and intent of the present invention. .

As shown in FIG. 17, the termination circuit 1700
Comprises an upper active clamp device 302 and a lower active clamp device 304. In the embodiment of FIG. 17, the lower active clamp device 302 has a source
Is realized by a p-type MOS device 332 (having a parasitic capacitance Cgd1 between the gate and the drain) connected to the potential of the reference voltage, and has a function of clamping the signal on the transmission line 306 to around the second reference voltage (for example, VDD). . On the other hand, the lower active clamp device 304 is realized by an n-type MOS device 320 (having a parasitic capacitance Cgd2 between the gate and the drain) whose source is connected to the first potential,
It has a function of clamping a signal on the transmission line 306 to a first reference voltage (for example, a ground voltage, that is, GND). Although the clamp circuit of the present invention has been described with reference to MOS devices, those skilled in the art will appreciate that other suitable devices such as bipolar devices may be used.

Here, the second potential is set to VDD, and the first potential is set to GND. However, these definitions are
It should be noted that this is for illustrative purposes only and should not be considered as limiting the scope and breadth of the present invention. Therefore, in this example, the source of MOS device 332 is connected to VDD and the source of MOS device 320 is connected to the ground line. As shown, the drains of devices 332 and 320 are both connected to transmission line 306. Turning now to the lower active clamp device 304, the gate 314 of the MOS device 320 is connected to both the gate and the drain of the lower threshold reference device 312. To compensate the MOS device 320 for all changes in transistor gate voltage due to parasitic capacitance, the stabilizing capacitor 1704
Gate 314 is connected to a suitable and stable voltage source, such as a first reference voltage source. However, FIGS. 18 and 19
It should be noted that any voltage source that is appropriately stabilized can be used, as shown in FIG. By connecting gates 330 and 314 to a suitable and regulated voltage source (VDD and GND, respectively, in this example), any change in clamp transistor gate voltage due to voltage transitions caused by parasitic capacitances Cgd1 and Cgd2 is It is significantly reduced compared to a termination circuit without capacitors 1702 and 1704.

For example, if the signal on the transmission line 306 is HI
When the transition from the GH signal, that is, logic 1 (about VDD) to logic 0 (about GND) starts, the stabilizing capacitor 1
704 controls the gate 31 of the n-type MOS device 320 by reducing the temporary voltage decrease of the gate 314.
4 functions to substantially maintain VT. As the signal on transmission line 306 begins to reflect and drop below ground voltage (ie, as soon as the potential difference between the gate and source of n-type MOS device 320 of lower active clamp device 304 exceeds VT). , N-type device 320
It starts conducting and supplies current from the drain connected to the ground line as shown in FIG. Therefore, 30
The signal of No. 6 is clamped near the ground voltage.

Similarly, the signal on the transmission line 306 is
W signal, that is, logic 0 (about GND) to logic 1
(About VDD), the stabilizing capacitor 17
02 functions to substantially keep the gate 330 of the p-type MOS device 332 at VDD-VT by reducing voltage transients on the gate 330. As the signal on transmission line 306 begins to reflect and rise above VDD, p-type MOS device 332 turns on to clamp the signal near VDD. Therefore, the signal at 306 is clamped near VDD.

FIGS. 18 and 19 show a further embodiment of the termination circuit 1700 as one embodiment of the present invention.
The stabilizing capacitors are transistors 332 and 320
Gates 330 and 314 may be connected to a suitable stabilized voltage source. For example, in FIG. 18, the termination circuit 1800 sets the gates 330 and 314 to GN, respectively.
19 has stabilizing capacitors 1802 and 1804 connected to D and VDD. In FIG. 19, stabilizing capacitors 1902 and 1904 have gates 330 and 31 respectively.
4 are discrete constant voltage supply circuits 1906, respectively.
And 1908. Discrete constant voltage supply circuits 1906 and 1908 may be the same or substantially the same circuit as required.

As a transmission line to be clamped, for example,
One of a plurality of bus-specific transmission lines such as a data bus, an address bus, and a memory bus can be considered. An example of this is the bus termination circuit 2000 according to the embodiment of the present invention.
FIG. In the illustrated embodiment,
The bus termination circuit 2000 is appropriately configured to terminate a plurality of transmission lines 2002-1 to 2002-n forming the bus 2003 collectively. In the example shown in FIG. 20, the circuit 2000 includes a second reference voltage source and a plurality of upper clamp transistors 2006-1 to 2006.
-N (each source is connected to a second potential) and a first shared line 20 connected to each gate in turn.
05-1 connected to the first stabilizing capacitor 20
01. The circuit 2000 includes a first reference voltage source and a plurality of lower clamp transistors 2008-1 to 2008-1.
A second stabilizing capacitor 2004 connected to a second shared line 2005-2 sequentially connected to each gate of 2008-n (each source is connected to a first potential). Thus, the plurality of transmission lines 2002-1 to 2002-n forming the bus 2003 are individually clamped by the respective upper and lower clamp transistors. For example, the transmission line 2002-1
Is set to V by the upper clamp transistor 2006-1.
DD (of course, when the second reference voltage is VDD)
And the lower clamp transistor 2008-
1 to GND (of course, the first reference voltage is set to GND
Is clamped). In the configuration shown in FIG. 20, stabilizing capacitors 2001 and 200
4 is set to be large enough to compensate for the parasitic capacitance existing in all the clamp transistors. Note that a capacitor with sufficient capacity for compensation may be too large for certain applications,
In some cases, it is difficult to carry out as it is.

FIG. 21 shows a modification of the bus termination circuit 2000 in which each of the clamp transistors 2006-1 to 2008-n and 2008-1 to 2008-n has its own compensating capacitor in order to meet such a demand. More specifically, the bus termination circuit 2100 shown in FIG.
Instead of a single compensation capacitor 2001 and 2004, a plurality of upper clamp transistors 2006-1-2
006-n and the lower clamp transistor 2008-
1-2008-n each have a stabilizing capacitor 2102 directly connected to the gate of the corresponding transistor.
Except for having -1 to n and 2104-1 to n, it has an embodiment substantially similar to the bus termination circuit 2000 shown in FIG. Thus, the capacitor 21
The size of each of 02-1 through n and 2104-1 through n is such that each compensates for only one gate node,
It is much smaller than 2001 and 2004. It can be seen that an isolation resistor or inductor can be connected to each gate of the clamp transistor.

The bus termination circuit 2200, which is another embodiment shown in FIG. 22, includes a first isolation resistor 2202-1-n directly connected to a corresponding one of the capacitors 2102-1-n. , And second isolation resistors 2204-1-n connected directly to the corresponding ones of the capacitors 2104-1-n. By adding such resistors, the bus termination circuit 2200 isolates each of the clamp transistors 2006 and 2008 from each other and reduces or substantially eliminates crosstalk between various transmission lines known to those skilled in the art. be able to. It should be noted that inductors may be used instead of resistors. It should also be noted that connection tracks in the IC can be used in place of resistors because they have resistance and inductance.

In some situations, the threshold reference device 3
Preferably, a variable current supply is provided at 10 and 312. Such a situation is caused by the termination circuit 300
It is desirable to include situations that require low power consumption, i.e., those circuits or systems can take a reduced power mode. Considering this, an embodiment of the present invention is applied to a variable current source (VCS) termination circuit 230.
23A is shown in FIG. VCS
Termination circuit 2300 is merely one embodiment of termination circuit 300 shown in FIG. 3 and is suitable for circuits and systems where low DC power or power reduction (such as sleep mode) is desired. In the illustrated embodiment,
The VCS termination circuit 2300 includes a variable current source (VCS) 2302 that connects to the threshold reference devices 310 and 312.
(See current source 316 in FIGS. 3 and 17). An enable input pin 2304 provides an enable / disable signal to the VCS 2302, the value of which determines the bias current supplied to the threshold reference devices 310 and 312. In the embodiment shown, VCS2
302 includes a current mirror 2305 formed by a transistor 2306;
Is connected between the drain and the gate, the drain and the gate are connected to the resistor 2308, the source is connected to the first reference voltage source (for example, GND), and the gate is connected to the gate of the transistor 2310. . In one particular implementation, transistor 2310 has a source connected to the first reference voltage source (eg, GND) and a drain connected to the drain and gate of transistor 334. In addition, resistor 2308 is connected in parallel with resistor 2312 connecting the drain and gate of transistor 318 to enable input pin 2304 so that the bias current (I) provided by VCS 2302 is enabled by enable input pin 2304 It is directly related to the applied voltage.

For example, when the voltage at the enable input pin 2304 rises, the bias voltage at the gate of 320 also rises, improving its clamp voltage. Also, the rise in the voltage on the enable input pin 2304 reduces the bias voltage on the gate of 332, thereby improving its clamp voltage. In those situations where the termination circuit 2300 is put into sleep or inactive mode,
The voltage at the enable pin 2304 can be reduced to a sufficiently low threshold voltage VT, in which case no DC current flows and no DC power is consumed. this is,
Also referred to as a shutdown mode specific to those circuits or systems where a sleep or low power mode is desired. Note that improved clamp performance requires a larger bias current to be provided by VCS 2302 and vice versa, so there is a trade-off between clamp voltage performance and good DC power loss. Should.

In some embodiments, the enable input pin 2304 can be controlled by a controller, similar to the VCS termination circuit 2350 shown in FIG. 23B. In the illustrated implementation, the microprocessor unit 2352 is connected to the enable input pin 2304 via an external resistor 2354. In this case, the enable / disable signal generated by the microprocessor 2352 is set to GND to turn off (i.e., disable) the power to the VCS termination circuit 2350 and to enable the microprocessor 2352 when clamping is required. Generates an enable signal set to VDD, in which case resistor 2354 determines the clamp voltage and the corresponding DC power loss. For example, if the value of resistor 2354 is increased, the DC power loss is reduced (due to reduced current drive) instead of decreasing clamping efficiency,
The reverse is also true.

As is well known to those skilled in the art, since there is no perfect conductor, whenever a current flows, a small voltage drop occurs due to the resistance of the conductor. This can cause problems for termination circuits where the various clamp devices and their associated bias voltage generators are connected to the same supply voltage. For example, if the input voltage is higher than VDD, a significant current will flow into the VDD line when the upper clamp transistor 332 is conducting. This current raises the local VDD voltage, and if the bias transistor 334 is connected to this local VDD line, its gate / drain voltage also increases by the same amount, thereby causing the voltage at the gate of 332 to increase. To rise. This effect is based on the fact that when the current I is constant, the voltage between the source and the gate of 334 always becomes constant. In this situation, furthermore, the clamp voltage is increased by the same amount due to the increase of the gate voltage of 332,
Thereby, the effectiveness of the upper clamping device 302 is reduced. One approach to solving this problem is shown in FIG. 24, which illustrates a split power line type termination circuit 2400 according to an embodiment of the present invention. As can be easily understood, each of the upper clamp transistors 332
And two independent power lines VDD1 and VDD2 connected to the upper threshold reference transistor 334, the current flowing in the power line VDD2 by the transistor 332 does not cause a voltage transition in the power line VDD1. A similar analysis is performed for an independent pair of GND personnel, GND1 and GND, each for the lower clamp transistor 320 and the lower reference threshold device 318.
This applies to 2.

Therefore, a large current flows through VDD2, and the resulting increase in VDD2 does not affect VDD1 used only in the bias voltage generation circuit. Therefore, by effectively increasing the number of power supply lines, it is possible to effectively increase VDD2. This problem is solved.

FIGS. 25-29 show various alternative implementations of the tristate circuit described above. One such alternative implementation is shown in FIG. 25, which illustrates a low DC power tri-state termination circuit 2500 according to an embodiment of the present invention. The circuit 400 converts VDD to the transistor 320
The tri-state termination circuit 2500 has a lower DC power loss than the tri-state circuit 400 when the circuit 2500 is operating as an output buffer, because more DC power is lost due to the totem pole current flowing to GND through and 332. Is configured to be low. To eliminate such totem pole currents, transistors 2502 and 2504 are each connected to a termination circuit 40
At 0, the portion connected to the bias voltage generator 410 is connected to the power supply lines VDD and GND. Thus, when the output buffer is asserting logic "0", the gate of 332 is pulled to the VDD line, so that no current flows reliably through 332. Similarly, when the output buffer is asserting a logic "1", the gate of 320 is pulled to the GND line, ensuring that no current flows through 320.

FIG. 26 shows a tristate termination circuit 26 having a reduced number of transistors according to an embodiment of the present invention.
00 is shown. By reducing the number of transistors used, the termination circuit 2600 can be connected to, for example, the termination circuits 2500 and 4.
Potentially faster and smaller than 00. A further implementation of the tristate termination circuit 400 is a transmission gate type tristate termination circuit 2700 shown in FIG.
7 is shown. Also for tristate termination circuit 2500, when circuit 2700 is in output buffer mode, no totem pole current flows through transistors 332 and 320. It should be noted that each of transmission gates 2702 and 2704 can be replaced by a tri-state inverter (not shown) that adds inversion to the output signal path when needed. With this in mind,
FIG. 28 shows a termination circuit 2700 in which transmission gates 2702 and 2704 are replaced by tristate inverters 2802 and 2804, respectively, to form low DC power tristate termination circuit 2800.

FIG. 29 illustrates the bias voltage generation circuits 310 and 312 of FIG. 3 according to another embodiment of the present invention.
Shows a tristate termination circuit 2900 incorporating a tristate function. In this configuration, when the tristate signal is high (ie, the negative logic tristate signal indicated by a bar is low), the gate of transistor 334 is shorted to the drain by transistor 2906 (ie, transistor 334). Is diode-connected), tri-state enabled current source 2908 (ie, supplies current only when tri-state signal is high)
This causes a current I1 to flow through the transistor 334,
As a result, the gate 3 of the upper clamp transistor 332
The voltage at 42 becomes VDD-VT. When the tristate signal is low, the current source 2908 cannot be used,
The n-type transistor 2910 is off and the p-type transistor 2906 is off. As a result, the signal becomes OUT
(Bar) to I / O (ie 332 drain)
And undergoes three inversions.

Returning to FIG. 3, the upper and lower clamp transistors 332 and 320, respectively, can further provide the robust electrostatic discharge (ESD) protection typically provided for integrated circuits. As is well known to those skilled in the art, both transistors 332 and 320 have intrinsic diodes connected to their respective power lines as shown in FIG. As shown, transistor 33
2 is interposed between VDD and the input node 3004, and the intrinsic diode 3006 for the transistor 320 is connected between GND and the input node 304.
04 is interposed. The input signal on input node 3004 is driven by two line voltages (ie, VDD and G
ND), the diode 3002 is also 300
It should be noted that 6 also does not carry current. ES provided by intrinsic diodes 3002 and 3006
Two approaches to increasing D protection are transistor 3
One is to increase the spacing between the source / drain contacts and the gate contacts of 32 and 320, and the other is to increase the gate length of both transistors. However, ES
By increasing the D protection to approximately 10 kV (2 kV for a standard diode ESD protection circuit), the speed of the circuit can be adversely affected due to the increased parasitic capacitance due to the junctions and oxides described above.

Although the present invention has been described with reference to certain preferred embodiments, various modifications, substitutions and equivalents are included within the scope of the present invention. It should also be noted that there are many alternative ways to implement the method and apparatus of the present invention. Therefore, the description of each claim is
It is to be interpreted as including all alterations, substitutions, and equivalents that fall within the true spirit and scope of the invention.

[Brief description of the drawings]

1A is a schematic diagram of various prior art resistive termination approaches for clamping signals. FIG.

1A and 1B are schematic diagrams of various prior art resistive termination approaches for clamping signals.

FIG. 2 is a schematic diagram of a prior art diode termination approach for clamping a signal.

FIG. 3 is a diagram showing a configuration example in which an active termination circuit according to the present invention is mounted by CMOS as one embodiment of the present invention;

FIG. 4 is a diagram illustrating a configuration example in which a termination circuit according to the present invention using a tristate signal is mounted by CMOS as one embodiment of the present invention;

FIG. 5 is a diagram showing a configuration example in which an active termination circuit according to the present invention is mounted by bipolar technology as one embodiment of the present invention.

FIG. 6 is a diagram showing a configuration example in which a termination circuit according to the present invention is alternatively mounted by CMOS as one embodiment of the present invention.

FIG. 7 is a diagram showing a general circuit configuration including a driving circuit, a transmission line, a receiving circuit, and a termination device for ease of explanation.

FIG. 8A is an explanatory diagram showing a voltage-current relationship for facilitating the description of a problem relating to a transmission system without a special diode clamp.

FIG. 8B is a diagram illustrating a voltage-time relationship to facilitate the description of a problem with a transmission system without a special diode clamp.

FIG. 9 is an explanatory diagram showing a voltage-current relationship indicating a response of the transmission system when input characteristics of the transmission system are complemented by Schottky diode devices arranged in parallel.

FIG. 10 is an explanatory diagram showing a voltage-current relationship showing a response of the transmission system of FIG. 9 when a resistor is inserted in series with a Schottky diode device.

FIG. 11 is an illustration showing a voltage-current relationship showing the response of the transmission system when the operating voltage is reduced to about 1 V to facilitate the description of the reflection problem.

FIG. 12 is a diagram illustrating a voltage-current relationship illustrating the response of the transmission system when a “zero threshold” transistor or a transistor having a slightly negative threshold value is used for termination.

FIG. 13 is an illustration generally illustrating a termination device in which a “zero threshold” transistor or a transistor having a slightly negative threshold value was used for termination.

FIG. 14 is an illustration showing an improved termination circuit according to one embodiment of the present invention.

FIG. 15 according to a further embodiment of the present invention.
It is explanatory drawing which shows the improved termination circuit which improves the time of stabilization.

FIG. 16 shows a typical MOSFET 160 with associated junction parasitic capacitances represented as lumped elements between device terminations.
It is explanatory drawing which shows 0.

FIG. 17 is a diagram illustrating a termination circuit having a stabilizing capacitor according to an embodiment of the present invention.

FIG. 18 is an explanatory diagram showing another embodiment of the termination circuit shown in FIG. 17;

FIG. 19 is an explanatory diagram showing another embodiment of the termination circuit shown in FIG. 17;

FIG. 20 is an explanatory diagram showing a bus termination circuit according to an embodiment of the present invention.

FIG. 21 is an explanatory diagram showing a modified example of the bus termination circuit shown in FIG. 20 in which each clamp transistor has its own compensation capacitor.

FIG. 22 is an explanatory diagram showing a bus termination circuit having an isolation resistor directly connected to each stabilizing capacitor.

FIG. 23A is an illustration depicting one particular implementation of a variable current source (VCS) termination circuit, in accordance with an embodiment of the present invention.

FIG. 23B is an illustration depicting one particular implementation of a variable current source (VCS) termination circuit in accordance with an embodiment of the present invention.

FIG. 24 is an explanatory diagram showing a split power supply line type termination circuit according to an embodiment of the present invention.

FIG. 25 is an illustration showing a low DC power tri-state termination circuit according to an embodiment of the present invention.

FIG. 26 is an explanatory diagram showing mounting of the tristate termination circuit shown in FIG. 4 in which the number of transistors is reduced.

FIG. 27 is an explanatory diagram showing a transmission gate type tri-state implementation of the termination circuit shown in FIG. 4;

FIG. 28 is an explanatory diagram showing the tristate termination circuit of FIG. 27 in which each transmission gate is replaced by a corresponding tristate inverter.

FIG. 29 is an explanatory diagram showing mounting of the tristate termination circuit of FIG. 4 in which a tristate function is incorporated in a bias voltage generation circuit.

30 shows an embodiment of the termination circuit shown in FIG.
It is explanatory drawing which shows the mode used as SD protection circuit.

[Explanation of symbols]

REFERENCE SIGNS LIST 102 resistor 104 driver circuit transmission line 152 impedance matching resistor 200 diode termination matching circuit 202 diode 204 diode 206 termination 300 termination circuit 302 upper active clamp circuit 304 lower active clamp circuit 306 ... transmission line 310 ... upper threshold reference device 312 ... lower threshold reference device 314 ... gate 316 ... current source 318 ... n-type MOS device 320 ... n-type MOS device 330 ... gate 332 ... p-type MOS device 334 ... p-type MOS device 342 node 344 node 400 tristate termination circuit 402 transmission line 404 output driver 406 node 408 node 410 voltage reference block 412 voltage reference block 414 input driver 4 16 tristate circuit 502 lower threshold device 504 npn transistor 506 npn transistor 508 lower clamp device 520 transmission line 530 pnp transistor 534 upper threshold device 540 pnp transistor 542 upper clamp device 602 p Type device 604 Upper clamp device 606 N-type device 608 Lower clamp device 620 Transmission line 1600 MOSFET 1700 Terminating circuit 1702 Stabilizing capacitor 1704 Stabilizing capacitor 1800 Terminating circuit 1802 Stabilizing capacitor 1804 Stabilizing capacitor 1902 Stabilizing capacitor 1904 Stabilizing capacitor 1906 Discrete stable voltage supply circuit 1908 Discrete stable voltage supply circuit Path 2000 Bus termination circuit 2001 First stabilizing capacitor 2002-1 to 2002-n Transmission line 2003 Bus 2004 Second stabilizing capacitor 2005-1 First shared line 2005-2 Second Shared line 2006-1 to 2006-n ... upper clamp transistor 2008-1 to 2008-n ... lower clamp transistor 2100 ... bus termination circuit 2102-1 to n ... stabilizing capacitor 2104-1 to n ... stabilizing capacitor 2200 .. Bus termination circuit 2202-1-n ... first isolation resistor 2204-1-n ... second isolation resistor 2300 ... variable current source (VCS) termination circuit 2302 ... variable current source (VCS) 2304 ... enable input pin 2305 ... current mirror 2306 ... transistor 2308 ... resistor 2310 ... transistor 2 50 VCS termination circuit 2352 Microprocessor 2354 External resistor 2400 Split line termination circuit 2500 Low DC power tristate termination circuit 2502 Transistor 2504 Transistor 2600 Tristate termination circuit 2700 Transmission gate type tristate termination circuit Reference numeral 2702: Transmission gate 2704: Transmission gate 2800: Low DC power tri-state termination circuit 2802: Tri-state inverter 2804: Tri-state inverter 2900: Tri-state termination circuit 2906: P-type transistor 2908: Tri-state usable current source 2910: N-type Transistor 3002 ... Intrinsic diode 3004 ... Input node 3006 ... Intrinsic diode

 ──────────────────────────────────────────────────続 き Continuation of the front page (31) Priority claim number 09/705520 (32) Priority date November 2, 2000 (2000. 11.2) (33) Priority claim country United States (US) (31) Priority claim number 09/705595 (32) Priority date November 2, 2000 (November 12, 2000) (33) Priority claim country United States (US) (31) Priority claim number 09/706237 (32) Priority date November 2, 2000 (November 12, 2000) (33) Priority claim country United States (US) (31) Priority claim number 09/706239 (32) Priority date November 2, 2000 ( (2000.11.1.2) (33) Priority Country United States (US) (72) Inventor Adam Jay.・ Whitworth, 94087 Sunnyvale, California, Bellevue Way, 1534 (72) Inventor Dominic Lichiuso, United States 95020 Saratoga, Chablis Court, 19303 F-term (reference) 5J056 AA00 AA40 BB18 CC01 CC02 DD02 DD13 DD25 DD29 DD51 DD55 EE15 5K029 AA11 DD04 HH01 JJ08 LL06

Claims (7)

[Claims] 1. An active termination circuit for clamping a signal on a transmission line to one of a first reference voltage and a second reference voltage, wherein the active termination circuit clamps the signal near the first reference voltage. A lower clamp transistor having a configured lower clamp transistor control node and connected to a first potential; and a lower threshold reference connected to a first reference voltage source that supplies the first reference voltage. A first bias voltage that biases the lower clamp transistor control node near a first threshold voltage higher than the first reference voltage, the first bias voltage being supplied to the lower clamp transistor control node; A lower threshold reference transistor having a first threshold voltage as a threshold voltage of the lower clamp transistor; and a step of clamping the signal near the second reference voltage. An upper clamp transistor connected to a second potential, and an upper threshold reference transistor connected to a second reference voltage source for supplying the second reference voltage. Supplying a second bias voltage for biasing the upper clamp transistor control node near a second threshold voltage higher than the second reference voltage to the upper clamp transistor control node; An active termination circuit comprising: the upper threshold reference transistor having a voltage as a threshold voltage of the upper clamp transistor. 2. An active termination circuit for terminating a signal traveling on a transmission line of an electronic device, comprising: a lower clamp transistor control node configured to clamp the signal near a first reference voltage. A lower clamp transistor connected to a first potential; a lower threshold reference transistor connected to a first reference voltage source configured to supply the first reference voltage; A first bias voltage for biasing a clamp transistor control node near a first threshold voltage higher than the first reference voltage is supplied to the lower clamp transistor control node, and the first threshold voltage is reduced to the lower threshold voltage. A lower threshold reference transistor that is a threshold voltage of a side clamp transistor; and an upper clamp configured to clamp the signal near a second reference voltage. An upper clamp transistor having a transistor control node and connected to a second potential, and an upper threshold reference transistor connected to a second reference voltage source configured to supply the second reference voltage. Supplying a second bias voltage for biasing the upper clamp transistor control node near a second threshold voltage higher than the second reference voltage to the upper clamp transistor control node; An upper threshold reference transistor that sets a threshold voltage of the upper clamp transistor; a first stabilizing capacitor connected between the lower clamp transistor control node and a first stable voltage source; An active termination circuit comprising a second stabilizing capacitor connected between the node and a second stable voltage source; . 3. An active termination circuit configured to clamp a signal on each of the transmission lines to one of a first reference voltage and a second reference voltage for terminating a plurality of transmission lines in an electronic device. And a plurality of first clamp transistors connected to corresponding transmission line terminals and a first terminal and configured to clamp the signal near a first reference voltage, wherein the transmission line terminal comprises: , Configured to be connected to the corresponding transmission line in the electronic device, wherein the first terminal is configured to be connected to a first potential in the electronic device; And a plurality of second clamp transistors connected to a corresponding one of the transmission line terminals and a second terminal, wherein the second terminal is connected to the electronic device. And a first bias transistor control node, wherein each of the plurality of first clamp transistor control nodes is biased from the first reference voltage to a vicinity of a first threshold voltage. A first threshold reference device connected to a first bias voltage source configured to supply a voltage to each of the plurality of first clamp transistor control nodes, wherein the first threshold voltage comprises:
A first clamp transistor threshold voltage, and a second bias voltage such that each of the plurality of second clamp transistor control nodes is biased from the second reference voltage to a vicinity of a second threshold voltage. A second threshold voltage reference device connected to a second bias voltage source configured to supply each of the plurality of second clamp transistor control nodes, wherein the second threshold voltage comprises:
An active termination circuit that is a second clamp transistor threshold voltage. 4. An active termination circuit for terminating a signal traveling on a transmission line having selective DC power consumption, wherein the first clamp is configured to clamp the signal near a first reference voltage. A first clamp transistor connected to a first potential having a transistor control node, and a first threshold reference transistor connected to a first reference voltage source configured to supply a first reference voltage. Supplying a first bias voltage for biasing the first clamp transistor control node from the first reference voltage to near a first threshold voltage to the first clamp transistor control node; The threshold voltage is set to the first
A first threshold reference transistor to be a threshold voltage of the clamp transistor of the first and second, and a second clamp transistor control node configured to clamp the signal near the second reference voltage,
A second clamp transistor connected to a second potential; a second threshold reference transistor connected to a second reference voltage source configured to supply a second reference voltage; A second bias voltage for biasing the clamp transistor control node from the second reference voltage to the vicinity of a second threshold voltage from the second reference voltage to the second clamp transistor control node, and setting the second threshold voltage to the second The second threshold reference transistor as a threshold voltage of the clamp transistor of the above, further connected to the first threshold reference transistor and the second threshold reference transistor, if necessary, the DC power of the active termination circuit Variable current supply means configured to reduce consumption. 5. An E for protecting a node from electrostatic discharge.
An SD protection circuit comprising: a first node connected to a first potential; and a diode in a lower ESD protection transistor connecting the node to a first reference voltage source in reverse bias. A first threshold voltage transistor connected to the first reference voltage source, the first bias voltage biasing the lower clamp transistor gate from the first reference voltage to near a first threshold voltage; A lower threshold reference transistor for supplying a voltage to the lower ESD protection transistor gate, the first threshold voltage being a threshold voltage of the lower ESD protection transistor, and a second potential connected to a second potential. An upper ESD protection transistor having a node and a diode in an upper ESD protection transistor that connects the node to a second reference voltage in reverse bias. And an upper threshold reference transistor connected to the second reference voltage source, the second bias biasing the upper clamp transistor gate near a second threshold voltage lower than the second reference voltage. A voltage to the upper ESD protection transistor gate, the second threshold voltage being the threshold voltage of the upper ESD protection transistor, and the upper and lower intrinsic diodes during an electrostatic discharge having an associated ESD voltage. Means that the node voltage transition is the ES
The second voltage so as to be substantially reduced over the D voltage.
And an upper threshold reference transistor providing a bypass current path for each of the first reference voltages. 6. An active termination circuit for terminating a signal traveling on a transmission line, the first locality having a lower clamp transistor control node configured to clamp the signal near a first reference voltage. A lower clamp transistor connected to a local potential; a lower threshold reference transistor connected to a first local reference voltage source configured to supply the first reference voltage; A first bias voltage for biasing the side clamp transistor control node near a first threshold voltage higher than the first reference voltage is supplied to the lower clamp transistor control node, and the first threshold voltage is set to the first threshold voltage. A lower threshold reference transistor that is a threshold voltage of a lower clamp transistor; and an upper clamp configured to clamp the signal near a second reference voltage. An upper clamp transistor having a pump transistor control node and connected to a second local potential, and connected to a second local reference voltage source configured to supply the second reference voltage An upper threshold reference transistor, wherein a second bias voltage for biasing the upper clamp transistor control node near a second threshold voltage higher than the second reference voltage is supplied to the upper clamp transistor control node; An upper threshold reference transistor having the second threshold voltage as an upper clamp transistor threshold voltage, wherein the deviation of the voltage at the first local potential affects the first local reference voltage. Without giving it, and vice versa,
An active termination circuit in which the excursion of the voltage at the second local potential does not affect the second local reference voltage and vice versa. 7. An active termination circuit for terminating a signal transmitted on a transmission line in a tristate mode, comprising: a tristate output buffer; and a lower clamp transistor control node configured to clamp the signal near GND. And a lower clamp transistor connected to GND and the tristate output buffer; and a lower threshold reference transistor connected to a first reference voltage source configured to supply the first reference voltage. And the lower clamp transistor control node is connected to GND.
Supplying a first bias voltage biasing around a higher first threshold voltage to the lower clamp transistor control node, and setting the first threshold voltage to a threshold voltage of the lower clamp transistor. A reference transistor; an upper clamp transistor control node configured to clamp the signal near VDD; an upper clamp transistor connected to VDD and the tristate output buffer; and providing the second reference voltage. An upper threshold reference transistor connected to a second reference voltage source, wherein the upper clamp transistor control node is connected to VDD.
An upper threshold reference transistor that supplies a second bias voltage biasing from around to a second threshold voltage to the upper clamp transistor control node, and sets the second threshold voltage to an upper clamp transistor threshold voltage. Termination circuit.