CN110995239A - Driving circuit with impedance matching and working method - Google Patents
Driving circuit with impedance matching and working method Download PDFInfo
- Publication number
- CN110995239A CN110995239A CN201911021775.6A CN201911021775A CN110995239A CN 110995239 A CN110995239 A CN 110995239A CN 201911021775 A CN201911021775 A CN 201911021775A CN 110995239 A CN110995239 A CN 110995239A
- Authority
- CN
- China
- Prior art keywords
- resistor
- diode
- nmos tube
- tube
- pmos tube
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000000034 method Methods 0.000 title claims abstract description 20
- 230000003071 parasitic effect Effects 0.000 claims description 19
- 238000011017 operating method Methods 0.000 claims description 4
- 238000012986 modification Methods 0.000 description 3
- 230000004048 modification Effects 0.000 description 3
- 230000007547 defect Effects 0.000 description 2
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000005540 biological transmission Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/0175—Coupling arrangements; Interface arrangements
- H03K19/017509—Interface arrangements
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/003—Modifications for increasing the reliability for protection
- H03K19/00315—Modifications for increasing the reliability for protection in field-effect transistor circuits
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/003—Modifications for increasing the reliability for protection
- H03K19/00346—Modifications for eliminating interference or parasitic voltages or currents
- H03K19/00361—Modifications for eliminating interference or parasitic voltages or currents in field effect transistor circuits
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/01—Modifications for accelerating switching
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/01—Modifications for accelerating switching
- H03K19/017—Modifications for accelerating switching in field-effect transistor circuits
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/0175—Coupling arrangements; Interface arrangements
- H03K19/017545—Coupling arrangements; Impedance matching circuits
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- Computing Systems (AREA)
- General Engineering & Computer Science (AREA)
- Mathematical Physics (AREA)
- Logic Circuits (AREA)
- Amplifiers (AREA)
Abstract
The invention belongs to the technical field of integrated circuit high-speed drive IO, and particularly relates to a drive circuit with impedance matching and a working method. The driving circuit comprises a second PMOS tube (1), a first PMOS tube (2), a first NMOS tube (3), a second NMOS tube (4), a resistor R1, a resistor R2, a resistor R3, a diode D1, a diode D2, a Tcoil inductor L1 and a Tcoil inductor L2. The output impedance of the driver under the direct-current condition is equal to the characteristic impedance of the signal link by adjusting the voltage of the grid bias voltage of the PMOS tube and the voltage of the grid bias voltage of the NMOS tube. The driving circuit and the working method can realize impedance matching of low frequency and high frequency, and increase the bandwidth and the ESD resistance of the driver.
Description
Technical Field
The invention relates to the technical field of integrated circuit high-speed drive IO, in particular to a drive circuit with impedance matching and a working method.
Background
In the transmission process of the existing high-frequency signal, the data rate of the existing high-frequency signal is over 10Gbps, and if the impedance of a driver and a signal link is not matched, the signal is reflected, so that the signal integrity problem is caused. The output impedance of the driver is consistent with the impedance of the signal link when transmitting high frequency signals. The traditional method for realizing impedance matching of the driver is to divide the driver into N parts to be connected in parallel, and enable the number to be combined according to the requirement of output impedance. Therefore, extra parasitic capacitance is caused by the output node of the driver which is not needed, the highest working speed of the driver is limited, high-frequency impedance is reduced, impedance of the driver is not matched with impedance of a signal link when the driver is at high frequency, and the problem of signal integrity is caused. Meanwhile, the working speed and the ESD resistance of the driver are low.
Disclosure of Invention
Aiming at the defects in the prior art, the invention aims to provide a driving circuit for impedance matching at high frequency and a working method.
In order to solve the technical problems, the technical scheme adopted by the invention is as follows:
a driving circuit with impedance matching comprises a second PMOS tube, a first NMOS tube, a second NMOS tube, a resistor R1, a resistor R2, a resistor R3, a diode D1, a diode D2, a T-shaped coil inductor L1 and a T2;
the grid electrode of the second PMOS tube is connected with a variable bias voltage end PBIAS, the source electrode of the second PMOS tube is connected with the power supply and one end of a resistor R1, and the drain electrode of the second PMOS tube is connected with the source electrode of the first PMOS tube and the other end of a resistor R1; the grid electrode of the first PMOS tube is connected with the input IN and the grid electrode of the first NMOS tube, the source electrode of the first PMOS tube is connected with the drain electrode of the second PMOS tube and one end of a resistor R1, and the drain electrode of the first NMOS tube is connected with the drain electrode of the first NMOS tube and one end of a resistor R3; the grid electrode of the first NMOS tube is connected with the input IN and the grid electrode of the first PMOS tube, the source electrode is connected with the drain electrode of the second NMOS tube and one end of a resistor R2, and the drain electrode is connected with the drain electrode of the first PMOS tube and one end of a resistor R3; the grid electrode of the second NMOS tube is connected with a variable bias voltage end NBIAS, the source electrode of the second NMOS tube is grounded and one end of a resistor R2, and the drain electrode of the second NMOS tube is connected with the source electrode of the first NMOS tube and the other end of a resistor R2; one end of the resistor R1 is connected with a power supply and a source electrode of the second PMOS tube, and the other end of the resistor R1 is connected with a drain electrode of the second PMOS tube and a source electrode of the first PMOS tube; one end of the resistor R2 is grounded and the source electrode of the second NMOS tube, and the other end of the resistor R2 is connected with the drain electrode of the second NMOS tube and the source electrode of the first NMOS tube; one end of the resistor R3 is connected with the drain electrode of the PMOS tube I and the drain electrode of the NMOS tube I, and the other end of the resistor R3 is connected with one end of the T-shaped coil inductor L1; one end of a T-type coil inductor L1 is connected with one end of a resistor R3, the other end of the T-type coil inductor L1 is connected with one end of a T-type coil inductor L2, the anode of a diode D1 and the cathode of a diode D2; one end of the T-type coil inductor L2 is connected with one end of the T-type coil inductor L1, the anode of the diode D1 and the cathode of the diode D2, and the other end of the T-type coil inductor L2 is connected with the output OUT; the cathode of the diode D1 is connected with a power supply, the anode of the diode D1 is connected with one end of a T-shaped coil inductor L1, one end of the T-shaped coil inductor L2 and the cathode of the diode D2; the anode of the diode D2 is grounded, the cathode of the diode D2 is connected to one end of the T-type coil inductor L1, one end of the T-type coil inductor L2 and the anode of the diode D1.
The driving circuit with the impedance matching function further comprises an ESD device, and the ESD device is arranged on the central tap of the T-shaped coil inductor.
Based on the working method of the driving circuit with impedance matching, the method enables the output impedance of the driver to be equal to the characteristic impedance of a signal link under the direct-current condition by adjusting the voltage of the grid variable bias voltage end of the PMOS tube and the voltage of the grid variable bias voltage end of the NMOS tube.
The specific method for making the output impedance of the driver equal to the characteristic impedance of the signal link under the direct-current condition by adjusting the gate bias voltage terminal voltage of the PMOS transistor and the gate bias voltage terminal voltage of the NMOS transistor is as follows:
when the signal input end IN is equal to 0, adjusting the voltage of the grid variable bias voltage end of the PMOS tube to enable the impedance of the output end OUT to be equal to the characteristic impedance of the signal link;
when the signal input end IN is equal to 1, adjusting the voltage of the grid variable bias voltage end of the NMOS tube to enable the impedance of the output end OUT to be equal to the characteristic impedance of the signal link;
according to the parasitic capacitance at the drain terminals of the second PMOS tube and the first NMOS tube, the parasitic capacitance of the diode D1 and the diode D2, the parasitic capacitance at the output terminal OUT determines T-type coil inductors L1 and L2.
In the operating method of the driving circuit with impedance matching, the method for determining the T-type coil inductors L1 and L2 according to the parasitic capacitances at the drain terminals of the second PMOS transistor and the first NMOS transistor, the parasitic capacitances of the diode D1 and the diode D2, and the parasitic capacitance at the output terminal OUT is as follows: the T-type coil inductors L1 and L2 have a reflection coefficient S11 looking into OUT of less than-10 dB over half the nyquist frequency.
The working method of the driving circuit with the impedance matching function is characterized in that the ESD device is placed on the central tap of the T-shaped coil inductor.
Compared with the prior art, the invention has the following beneficial effects:
(1) the invention overcomes the defects of the prior art, can effectively reduce the parasitic capacitance, and leads the signal reflection to reach-40 dB at DC (direct current) and reach-10 dB at 20 GHz; the bandwidth of the driver can reach 40 GHz; the HBM ESD (human body electrostatic discharge) capability reaches more than 2500V. Under the same process condition, the performance indexes are better than those of the traditional driver circuit with impedance matching, and the phenomenon that the impedance of the impedance matching driver is seriously unmatched under high frequency is avoided.
(2) The invention simultaneously solves the contradiction between the ESD capacity and the driver bandwidth, designs the inductor as a Tcoil inductor, arranges the ESD device on the center tap of the Tcoil inductor, and improves the ESD capacity through the inductor, thus reducing the area of the ESD device, namely reducing the ESD parasitic capacitance to improve the driver bandwidth, and improving the working rate of the driver and the ESD resistance.
Drawings
Fig. 1 is a circuit diagram of a drive circuit with impedance matching in an embodiment.
Detailed Description
The following detailed description of embodiments of the invention refers to the accompanying drawings.
As shown in fig. 1, the driving circuit with impedance matching according to this embodiment includes a second PMOS transistor 1, a first PMOS transistor 2, a first NMOS transistor 3, a second NMOS transistor 4, a resistor R1, a resistor R2, a resistor R3, a diode D1, a diode D2, a T-type coil inductor (Tcoil inductor) L1, and a T2.
The grid electrode of the second PMOS tube (1) is connected with a variable bias voltage end PBIAS, the source electrode is connected with the power supply and one end of a resistor R1, and the drain electrode is connected with the source electrode of the first PMOS tube (2) and the other end of a resistor R1; the grid electrode of the first PMOS tube (2) is connected with the input IN and the grid electrode of the first NMOS tube (3), the source electrode is connected with the drain electrode of the second PMOS tube (1) and one end of a resistor R1, and the drain electrode is connected with the drain electrode of the first NMOS tube (3) and one end of a resistor R3; the grid electrode of the first NMOS tube (3) is connected with the input IN and the grid electrode of the first PMOS tube (2), the source electrode is connected with the drain electrode of the second NMOS tube (4) and one end of a resistor R2, and the drain electrode is connected with the drain electrode of the first PMOS tube (2) and one end of a resistor R3; the grid electrode of the second NMOS tube (4) is connected with a variable bias voltage end NBIAS, the source electrode is grounded and one end of a resistor R2, and the drain electrode is connected with the source electrode of the first NMOS tube (3) and the other end of a resistor R2; one end of the resistor R1 is connected with a power supply and the source electrode of the second PMOS tube (1), and the other end of the resistor R1 is connected with the drain electrode of the second PMOS tube (1) and the source electrode of the first PMOS tube (2); one end of the resistor R2 is grounded and the source electrode of the second NMOS tube (4), and the other end of the resistor R2 is connected with the drain electrode of the second NMOS tube (4) and the source electrode of the first NMOS tube (3); one end of the resistor R3 is connected with the drain electrode of the first PMOS tube (2) and the drain electrode of the first NMOS tube (3), and the other end of the resistor R3 is connected with one end of the T-shaped coil inductor L1; one end of a T-type coil inductor L1 is connected with one end of a resistor R3, the other end of the T-type coil inductor L1 is connected with one end of a T-type coil inductor L2, the anode of a diode D1 and the cathode of a diode D2; one end of the T-type coil inductor L2 is connected with one end of the T-type coil inductor L1, the anode of the diode D1 and the cathode of the diode D2, and the other end of the T-type coil inductor L2 is connected with the output OUT; the cathode of the diode D1 is connected with a power supply, the anode of the diode D1 is connected with one end of a T-shaped coil inductor L1, one end of the T-shaped coil inductor L2 and the cathode of the diode D2; the anode of the diode D2 is grounded, the cathode of the diode D2 is connected to one end of the T-type coil inductor L1, one end of the T-type coil inductor L2 and the anode of the diode D1.
In consideration of the contradiction between the ESD capacity and the driver bandwidth, the driving circuit in the embodiment designs the inductor into the Tcoil inductor, the ESD device is arranged on the center tap of the Tcoil inductor, and the ESD capacity is improved through the inductor, so that the area of the ESD device can be reduced, namely the ESD parasitic capacitance is reduced, and the driver bandwidth is improved.
The operation method of the drive circuit with impedance matching in this embodiment is as follows: the output impedance of the driver under the direct-current condition is equal to the characteristic impedance of the signal link by adjusting the voltage of the grid bias voltage of the PMOS tube and the voltage of the grid bias voltage of the NMOS tube.
Specifically, the method comprises the following steps: when the signal input end IN is equal to 0, the variable grid bias voltage end voltage of the PMOS tube is adjusted to enable the impedance of the output end OUT to be equal to the characteristic impedance of the signal link.
When the signal input end IN is equal to 1, adjusting the voltage of the gate variable bias voltage end of the NMOS tube to make the impedance of the output end OUT equal to the characteristic impedance of the signal link.
According to the parasitic capacitance of the drain terminals of the second PMOS tube and the first NMOS tube, the parasitic capacitance of the diode D1 and the diode D2 and the parasitic capacitance of the output terminal OUT, a Tcoil inductor L1 and a Tcoil inductor L2 are designed, so that the reflection coefficient S11 looking into the OUT is smaller than-10 dB within a half range of the Nyquist frequency of T-shaped coil inductors L1 and L2.
The driving circuit and the working method thereof in the embodiment can realize impedance matching of low frequency and high frequency, and increase the bandwidth and the anti-ESD capability of the driver.
It will be apparent to those skilled in the art that various changes and modifications may be made in the present invention without departing from the spirit and scope of the invention. Thus, if such modifications and variations of the present invention fall within the scope of the claims of the present invention and their equivalents, the present invention is intended to include such modifications and variations.
Claims (6)
1. A kind of drive circuit with impedance match, characterized by that: the device comprises a second PMOS tube (1), a first PMOS tube (2), a first NMOS tube (3), a second NMOS tube (4), a resistor R1, a resistor R2, a resistor R3, a diode D1, a diode D2, a T-shaped coil inductor L1 and a T2;
the grid electrode of the second PMOS tube (1) is connected with a variable bias voltage end PBIAS, the source electrode is connected with the power supply and one end of a resistor R1, and the drain electrode is connected with the source electrode of the first PMOS tube (2) and the other end of a resistor R1; the grid electrode of the first PMOS tube (2) is connected with the input IN and the grid electrode of the first NMOS tube (3), the source electrode is connected with the drain electrode of the second PMOS tube (1) and one end of a resistor R1, and the drain electrode is connected with the drain electrode of the first NMOS tube (3) and one end of a resistor R3; the grid electrode of the first NMOS tube (3) is connected with the input IN and the grid electrode of the first PMOS tube (2), the source electrode is connected with the drain electrode of the second NMOS tube (4) and one end of a resistor R2, and the drain electrode is connected with the drain electrode of the first PMOS tube (2) and one end of a resistor R3; the grid electrode of the second NMOS tube (4) is connected with a variable bias voltage end NBIAS, the source electrode is grounded and one end of a resistor R2, and the drain electrode is connected with the source electrode of the first NMOS tube (3) and the other end of a resistor R2; one end of the resistor R1 is connected with a power supply and the source electrode of the second PMOS tube (1), and the other end of the resistor R1 is connected with the drain electrode of the second PMOS tube (1) and the source electrode of the first PMOS tube (2); one end of the resistor R2 is grounded and the source electrode of the second NMOS tube (4), and the other end of the resistor R2 is connected with the drain electrode of the second NMOS tube (4) and the source electrode of the first NMOS tube (3); one end of the resistor R3 is connected with the drain electrode of the first PMOS tube (2) and the drain electrode of the first NMOS tube (3), and the other end of the resistor R3 is connected with one end of the T-shaped coil inductor L1; one end of a T-type coil inductor L1 is connected with one end of a resistor R3, the other end of the T-type coil inductor L1 is connected with one end of a T-type coil inductor L2, the anode of a diode D1 and the cathode of a diode D2; one end of the T-type coil inductor L2 is connected with one end of the T-type coil inductor L1, the anode of the diode D1 and the cathode of the diode D2, and the other end of the T-type coil inductor L2 is connected with the output OUT; the cathode of the diode D1 is connected with a power supply, the anode of the diode D1 is connected with one end of a T-shaped coil inductor L1, one end of the T-shaped coil inductor L2 and the cathode of the diode D2; the anode of the diode D2 is grounded, the cathode of the diode D2 is connected to one end of the T-type coil inductor L1, one end of the T-type coil inductor L2 and the anode of the diode D1.
2. The band rejection impedance matched driver circuit of claim 1, wherein: the driving circuit further comprises an ESD device, and the ESD device is arranged on the central tap of the T-shaped coil inductor.
3. The operating method of the driving circuit with impedance matching according to claim 1 or 2, wherein the operating method is as follows: the output impedance of the driver under the direct current condition is equal to the characteristic impedance of the signal link by adjusting the voltage of the grid variable bias voltage end of the PMOS tube and the voltage of the grid variable bias voltage end of the NMOS tube.
4. The method for operating the driver circuit with impedance matching as claimed in claim 3, wherein the specific method for making the output impedance of the driver equal to the characteristic impedance of the signal link under the condition of direct current by adjusting the gate variable bias voltage terminal voltage of the PMOS transistor and the gate variable bias voltage terminal voltage of the NMOS transistor is as follows:
when the signal input end IN is equal to 0, adjusting the voltage of the grid variable bias voltage end of the PMOS tube to enable the impedance of the output end OUT to be equal to the characteristic impedance of the signal link;
when the signal input end IN is equal to 1, adjusting the voltage of the grid variable bias voltage end of the NMOS tube to enable the impedance of the output end OUT to be equal to the characteristic impedance of the signal link;
according to the parasitic capacitance at the drain terminals of the second PMOS tube and the first NMOS tube, the parasitic capacitance of the diode D1 and the diode D2, the parasitic capacitance at the output terminal OUT determines T-type coil inductors L1 and L2.
5. The operating method of the driving circuit with impedance matching as claimed in claim 4, wherein the method for determining T-type coil inductances L1 and L2 according to the parasitic capacitances at the drain terminals of the PMOS transistor II and the NMOS transistor I, the parasitic capacitances of the diode D1 and the diode D2, and the parasitic capacitance at the output terminal OUT is as follows: the T-type coil inductors L1 and L2 have a reflection coefficient S11 looking into OUT of less than-10 dB over half the nyquist frequency.
6. The method of operating a drive circuit with impedance matching as defined in claim 3, wherein: and placing the ESD device on a central tap of the T-shaped coil inductor.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201911021775.6A CN110995239A (en) | 2019-10-25 | 2019-10-25 | Driving circuit with impedance matching and working method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201911021775.6A CN110995239A (en) | 2019-10-25 | 2019-10-25 | Driving circuit with impedance matching and working method |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN110995239A true CN110995239A (en) | 2020-04-10 |
Family
ID=70082389
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201911021775.6A Pending CN110995239A (en) | 2019-10-25 | 2019-10-25 | Driving circuit with impedance matching and working method |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN110995239A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN118157462A (en) * | 2024-05-12 | 2024-06-07 | 中茵微电子(南京)有限公司 | Circuit structure for eliminating IO driver connection line capacitance |
Citations (23)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4959561A (en) * | 1989-01-04 | 1990-09-25 | Motorola, Inc. | MOS output buffer with reduced supply line disturbance |
| DE4305864A1 (en) * | 1992-02-27 | 1993-09-16 | Mitsubishi Electric Corp | Output buffer digital driver - has overshoot limiting and changes impedance with output voltage |
| CN1211108A (en) * | 1997-09-11 | 1999-03-17 | 三菱电机株式会社 | Semiconductor device allowing fast and stable transmission of signal |
| US6133749A (en) * | 1999-01-04 | 2000-10-17 | International Business Machines Corporation | Variable impedance output driver circuit using analog biases to match driver output impedance to load input impedance |
| CN1357973A (en) * | 2000-11-02 | 2002-07-10 | 加利福尼亚微设备公司 | Terminal circuit and its method |
| CN1518224A (en) * | 2002-11-20 | 2004-08-04 | 威盛电子股份有限公司 | Output driver with low ground jump noise |
| US20040155675A1 (en) * | 2003-02-07 | 2004-08-12 | Zerbe Jared L. | Input/output circuit with on-chip inductor to reduce parasitic capacitance |
| US20050088199A1 (en) * | 2003-10-28 | 2005-04-28 | Bales Tim J. | Mos linear region impedance curvature correction |
| JP2005184644A (en) * | 2003-12-22 | 2005-07-07 | Nippon Telegr & Teleph Corp <Ntt> | Current switching logic circuit |
| US20060232349A1 (en) * | 2002-07-12 | 2006-10-19 | Daniel Kehrer | Integrated circuit arrangement |
| US7532037B1 (en) * | 2008-05-05 | 2009-05-12 | International Business Machines Corporation | Enhanced CML driver circuit for “quiet-driver” measurement enablement |
| CN101442291A (en) * | 2007-11-23 | 2009-05-27 | 上海华虹Nec电子有限公司 | Whole differential wideband high-frequency local oscillation driver circuit |
| CN102340288A (en) * | 2010-07-21 | 2012-02-01 | 中国科学院微电子研究所 | Radio-frequency integrated band-pass filter with impedance match |
| US20130176647A1 (en) * | 2012-01-10 | 2013-07-11 | Xilinx, Inc. | Driver circuit and method of generating an output signal |
| CN104756407A (en) * | 2012-10-23 | 2015-07-01 | 高通股份有限公司 | Methods and devices for matching transmission line characteristics using stacked metal oxide semiconductor (MOS) transistors |
| CN105097786A (en) * | 2014-05-14 | 2015-11-25 | 三星电子株式会社 | Semiconductor device including electrostatic discharge circuit and operation method thereof |
| CN206363743U (en) * | 2016-03-07 | 2017-07-28 | 意法半导体股份有限公司 | For half-bridge or the gate driver circuit and electronic system of full-bridge out drive stage |
| CN107210977A (en) * | 2015-01-20 | 2017-09-26 | 三菱电机株式会社 | Signal transmitting apparatus |
| CN107733424A (en) * | 2017-09-08 | 2018-02-23 | 灿芯创智微电子技术（北京）有限公司 | A kind of ddr interface circuit with preemphasis function |
| CN108259028A (en) * | 2016-12-29 | 2018-07-06 | 大北欧听力公司 | Include the output driver of the MOS switch with adjustable reverse biased |
| US20180226969A1 (en) * | 2017-02-03 | 2018-08-09 | The Regents Of The University Of California | Multi-level adiabatic charging methods, devices and systems |
| CN108418577A (en) * | 2017-02-10 | 2018-08-17 | 硅实验室公司 | The device and correlation technique of the electronic circuit of leakage current with reduction |
| CN108809296A (en) * | 2017-04-26 | 2018-11-13 | 三菱电机株式会社 | High-pressure level shift circuit and driving device |
-
2019
- 2019-10-25 CN CN201911021775.6A patent/CN110995239A/en active Pending
Patent Citations (24)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4959561A (en) * | 1989-01-04 | 1990-09-25 | Motorola, Inc. | MOS output buffer with reduced supply line disturbance |
| DE4305864A1 (en) * | 1992-02-27 | 1993-09-16 | Mitsubishi Electric Corp | Output buffer digital driver - has overshoot limiting and changes impedance with output voltage |
| CN1211108A (en) * | 1997-09-11 | 1999-03-17 | 三菱电机株式会社 | Semiconductor device allowing fast and stable transmission of signal |
| US6133749A (en) * | 1999-01-04 | 2000-10-17 | International Business Machines Corporation | Variable impedance output driver circuit using analog biases to match driver output impedance to load input impedance |
| CN1357973A (en) * | 2000-11-02 | 2002-07-10 | 加利福尼亚微设备公司 | Terminal circuit and its method |
| US20060232349A1 (en) * | 2002-07-12 | 2006-10-19 | Daniel Kehrer | Integrated circuit arrangement |
| CN1518224A (en) * | 2002-11-20 | 2004-08-04 | 威盛电子股份有限公司 | Output driver with low ground jump noise |
| US20040155675A1 (en) * | 2003-02-07 | 2004-08-12 | Zerbe Jared L. | Input/output circuit with on-chip inductor to reduce parasitic capacitance |
| US20050088199A1 (en) * | 2003-10-28 | 2005-04-28 | Bales Tim J. | Mos linear region impedance curvature correction |
| JP2005184644A (en) * | 2003-12-22 | 2005-07-07 | Nippon Telegr & Teleph Corp <Ntt> | Current switching logic circuit |
| CN101442291A (en) * | 2007-11-23 | 2009-05-27 | 上海华虹Nec电子有限公司 | Whole differential wideband high-frequency local oscillation driver circuit |
| US7532037B1 (en) * | 2008-05-05 | 2009-05-12 | International Business Machines Corporation | Enhanced CML driver circuit for “quiet-driver” measurement enablement |
| CN102340288A (en) * | 2010-07-21 | 2012-02-01 | 中国科学院微电子研究所 | Radio-frequency integrated band-pass filter with impedance match |
| US20130176647A1 (en) * | 2012-01-10 | 2013-07-11 | Xilinx, Inc. | Driver circuit and method of generating an output signal |
| CN104067518A (en) * | 2012-01-10 | 2014-09-24 | 吉林克斯公司 | Driver circuit and method of generating an output signal |
| CN104756407A (en) * | 2012-10-23 | 2015-07-01 | 高通股份有限公司 | Methods and devices for matching transmission line characteristics using stacked metal oxide semiconductor (MOS) transistors |
| CN105097786A (en) * | 2014-05-14 | 2015-11-25 | 三星电子株式会社 | Semiconductor device including electrostatic discharge circuit and operation method thereof |
| CN107210977A (en) * | 2015-01-20 | 2017-09-26 | 三菱电机株式会社 | Signal transmitting apparatus |
| CN206363743U (en) * | 2016-03-07 | 2017-07-28 | 意法半导体股份有限公司 | For half-bridge or the gate driver circuit and electronic system of full-bridge out drive stage |
| CN108259028A (en) * | 2016-12-29 | 2018-07-06 | 大北欧听力公司 | Include the output driver of the MOS switch with adjustable reverse biased |
| US20180226969A1 (en) * | 2017-02-03 | 2018-08-09 | The Regents Of The University Of California | Multi-level adiabatic charging methods, devices and systems |
| CN108418577A (en) * | 2017-02-10 | 2018-08-17 | 硅实验室公司 | The device and correlation technique of the electronic circuit of leakage current with reduction |
| CN108809296A (en) * | 2017-04-26 | 2018-11-13 | 三菱电机株式会社 | High-pressure level shift circuit and driving device |
| CN107733424A (en) * | 2017-09-08 | 2018-02-23 | 灿芯创智微电子技术（北京）有限公司 | A kind of ddr interface circuit with preemphasis function |
Non-Patent Citations (1)
| Title |
|---|
| 朱敏: "一种高功率因数单级PFC变换器的研究", 《湖南工业大学学报》 * |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN118157462A (en) * | 2024-05-12 | 2024-06-07 | 中茵微电子(南京)有限公司 | Circuit structure for eliminating IO driver connection line capacitance |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US10505537B2 (en) | Radio frequency antenna switch | |
| CN109873628B (en) | Radio frequency switch circuit | |
| CN104852706A (en) | Low additional phase shift digital attenuator | |
| CN104953996A (en) | High-isolation RF (radio frequency) switch circuit | |
| CN113381713A (en) | Dual-band low-noise amplifier based on reconfigurable inductor | |
| CN102655404B (en) | Differential radio frequency switch circuit | |
| WO2019104015A1 (en) | High power silicon on insulator switch | |
| CN104079275A (en) | Radio frequency switch assembly | |
| CN110995239A (en) | Driving circuit with impedance matching and working method | |
| WO2020049877A1 (en) | Variable capacitance circuit and radio communication device | |
| TWI724954B (en) | Matching circuit | |
| CN114944827B (en) | Folding coil and distributed amplifier | |
| CN112003574B (en) | K-band CMOS efficient radio frequency power amplifier circuit | |
| CN103973261A (en) | High frequency and wide attenuation range active variable attenuator circuit | |
| CN110113013B (en) | High octave ultra-wideband input matching circuit for low noise amplifier | |
| CN113014202A (en) | Adjustable amplitude equalizer based on variable capacitance diode and PIN diode | |
| CN110932689A (en) | Two-dimensional synthesis distribution type high-power linear broadband power amplifier | |
| CN108768316B (en) | High-frequency high-power high-efficiency composite transistor die based on four-stacking technology | |
| CN220511094U (en) | High-isolation multi-cut switch | |
| CN111147059A (en) | High-power radio frequency switch for wireless communication | |
| CN104579236A (en) | Unsymmetrical microwave digital attenuator circuit and control method thereof | |
| US12028071B2 (en) | High-speed wide-band low-power level shifter for high-speed applications | |
| CN219718204U (en) | Withstand voltage stacks switching tube circuit | |
| CN220775802U (en) | Reflection type single-pole double-throw switch chip | |
| US20240154608A1 (en) | High-speed wide-band low-power level shifter for high-speed applications |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| RJ01 | Rejection of invention patent application after publication | ||
| RJ01 | Rejection of invention patent application after publication |
Application publication date: 20200410 |