NL2034089A - A CMOS Process Compatible Interface Chip power-failure Protection Circuit and The Method Thereof - Google Patents

A CMOS Process Compatible Interface Chip power-failure Protection Circuit and The Method Thereof Download PDF

Info

Publication number
NL2034089A
NL2034089A NL2034089A NL2034089A NL2034089A NL 2034089 A NL2034089 A NL 2034089A NL 2034089 A NL2034089 A NL 2034089A NL 2034089 A NL2034089 A NL 2034089A NL 2034089 A NL2034089 A NL 2034089A
Authority
NL
Netherlands
Prior art keywords
pmos tube
tube
drain
nmos tube
power supply
Prior art date
Application number
NL2034089A
Other languages
Dutch (nl)
Other versions
NL2034089B1 (en
Inventor
Han Genliang
Wang Xiangqian
Xie Mingling
Yuan Chaoxin
Gao Xiaoping
Original Assignee
Institute Of Sensor Tech Gansu Academy Of Sciences
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Institute Of Sensor Tech Gansu Academy Of Sciences filed Critical Institute Of Sensor Tech Gansu Academy Of Sciences
Publication of NL2034089A publication Critical patent/NL2034089A/en
Application granted granted Critical
Publication of NL2034089B1 publication Critical patent/NL2034089B1/en

Links

Classifications

    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02H—EMERGENCY PROTECTIVE CIRCUIT ARRANGEMENTS
    • H02H7/00—Emergency protective circuit arrangements specially adapted for specific types of electric machines or apparatus or for sectionalised protection of cable or line systems, and effecting automatic switching in the event of an undesired change from normal working conditions
    • H02H7/20—Emergency protective circuit arrangements specially adapted for specific types of electric machines or apparatus or for sectionalised protection of cable or line systems, and effecting automatic switching in the event of an undesired change from normal working conditions for electronic equipment
    • H02H7/205—Emergency protective circuit arrangements specially adapted for specific types of electric machines or apparatus or for sectionalised protection of cable or line systems, and effecting automatic switching in the event of an undesired change from normal working conditions for electronic equipment for controlled semi-conductors which are not included in a specific circuit arrangement
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/003—Modifications for increasing the reliability for protection
    • H03K19/00315—Modifications for increasing the reliability for protection in field-effect transistor circuits
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02H—EMERGENCY PROTECTIVE CIRCUIT ARRANGEMENTS
    • H02H3/00—Emergency protective circuit arrangements for automatic disconnection directly responsive to an undesired change from normal electric working condition with or without subsequent reconnection ; integrated protection
    • H02H3/02—Details
    • H02H3/021—Details concerning the disconnection itself, e.g. at a particular instant, particularly at zero value of current, disconnection in a predetermined order
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
    • H03K17/20—Modifications for resetting core switching units to a predetermined state
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/0021—Modifications of threshold
    • H03K19/0027—Modifications of threshold in field effect transistor circuits
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/003—Modifications for increasing the reliability for protection
    • H03K19/00346—Modifications for eliminating interference or parasitic voltages or currents
    • H03K19/00361—Modifications for eliminating interference or parasitic voltages or currents in field effect transistor circuits

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Mathematical Physics (AREA)
  • Power Engineering (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Logic Circuits (AREA)

Abstract

The invention discloses a CMOS process compatible interface chip power-failure protection circuit and a method thereof. The circuit comprises a power supply chip protection sub-circuit and a substrate potential generator sub-circuit. The CMOS process compatible interface chip power-failure protection circuit of the invention does not require the process to have special devices, and can be realized under the standard CMOS process, and the circuit structure is simple. The substrate potential generator sub-circuit will generate the substrate potential of PMOS tube, which can effectively reduce the current backflow when the output end has high potential in the case of power-failure. The leakage current can be lower than the index of 1uA.

Description

Institute of Sensor Technology, Gansu Academy of Sciences 23/013 NL
A CMOS Process Compatible Interface Chip power-failure Protection Circuit and The Method Thereof
Technical Field
The invention belongs to the field of integrated circuit devices and digital signal transmission, in particular to a CMOS process compatible interface chip power-failure protection circuit and a method thereof.
Background Technology
With the rapid development of integrated circuits, digital signal transmission is more and more common in the system, and the transmission of digital signals often involves many- to-one signal transmission. For the traditional signal sending system, the inverter structure is generally adopted. Now the integrated circuit system often has energy saving design. In some cases, only some signal sending systems may send signals, while the remaining systems will not send signals. The best way to save energy is to directly power off the system that does not send signals, and reduce its power supply voltage to ground potential, so that the system will not have power consumption. But the problem comes at this time, when the signal sending system sends a high level, the high level is output to the OUT end of the power-down system, the OUT end is a high voltage, and the power supply of the source of the output pull-up PMOS is a ground potential, then a conductive path from the OUT end to
GND through the parasitic diode will be formed. When the high level occurs at the OUT port,
This path will produce a current 11, because the PMOS tube is a pull-up power tube, the area is generally large, so the parasitic diode area is also large, the current 11 will be large, it is easy to clamp the high level of the OUT port at a very low level, resulting in the following signal receiving system can not identify the high level.
Summary of the Invention
In view of the above shortcomings in the existing technology, the invention provides a
CMOS process compatible interface chip power-failure protection circuit and a method to solve the problem of conductive path to ground in the case of interface chip power-failure.
In order to achieve the purpose of the invention, the invention adopts the following technical scheme: a CMOS process compatible interface chip power-failure protection circuit, including a power supply chip protection sub-circuit and a substrate potential generating sub-circuit;
Wherein, the first input of the power supply chip protection sub-circuit is the input of the CMOS process compatible interface chip power-failure protection circuit, and the output of the power supply chip protection sub-circuit is the output of the CMOS process compatible interface chip power-failure protection circuit;
The input end of the substrate potential generator sub-circuit is connected with the output end of the power supply chip protection sub-circuit, the output end of the substrate potential generator sub-circuit is connected with the second input end and the third input end of the power supply chip protection sub-circuit respectively;
The power supply chip protection sub-circuit is used in CMOS process compatible interface chip power-failure case, to prevent CMOS process compatible interface chip power-failure protection circuit output current backflow to the power port; The substrate potential generator sub-circuit is used to output the substrate voltage.
Further: the power supply chip protection sub-circuit comprises a power supply chip protection sub-circuit including PMOS tube PO, PMOS tube P1, PMOS tube P2, PMOS tube
P3, PMOS tube P4, NMOS tube NO, NMOS tube N1, NMOS tube N2, NMOS tube N3 and
NMOS tube N4;
Wherein, the gate of the PMOS tube PO is connected with the gate of the NMOS tube
NO, the source of the PMOS tube PO is connected with the VDD power supply, the gate of the NMOS tube NO is the first input of the power supply chip protection sub-circuit, the source of the NMOS tube NO is grounded, The drain of the NMOS tube NO is respectively connected with the drain of the PMOS tube PO, the gate of the PMOS tube P1 and the gate of the
NMOS tube N1, and the source of the PMOS tube P1 is connected with the VDD power supply. The drain of the PMOS tube P1 is respectively connected with the drain of the NMOS tube N1, the gate of the PMOS tube P2, the gate of the PMOS tube P3, the gate of the
NMOS tube N2 and the gate of the NMOS tube N3. The source of the NMOS tube N1 is grounded, and the source of the PMOS tube P2 is connected with the VDD power supply.
The drain of the PMOS tube P2 is respectively connected with the drain of the NMOS tube
N2 and the gate of the NMOS tube N4. The source of the NMOS tube N2 is grounded, and the source of the PMOS tube P3 is used as the second input of the power supply chip protection sub-circuit. The drain of the PMOS tube P3 is respectively connected with the drain of the NMOS tube N3 and the gate of the PMOS tube P4, the source of the NMOS tube N3 is grounded, the source of the PMOS tube P4 is connected with the VDD power supply, and the substrate of the PMOS tube P4 is the third input of the power supply chip protection sub-circuit. The drain of the PMOS tube P4 is connected with the drain of the
NMOS tube N4 and serves as the output end of the power supply chip protection sub-circuit, and the source of the NMOS tube N4 is grounded.
The beneficial effects of the further scheme above are as follows: The CMOS process compatible interface chip power-failure protection circuit of the invention does not require the process to have special devices, and can be realized under the standard CMOS process.
The output voltage Vbias of the substrate potential generator sub-circuit provides the substrate potential for PMOS tube P4. The substrate potential generated by this circuit cuts off the unidirectional path from the output end of the interface chip power-failure protection circuit to the power-failure, and the Vbias voltage provides the power supply for PMOS tube
P3, so as to avoid the PMOS tube P4 to be opened under the condition of power-failure, so as to avoid the backflow current from the output end to the power supply end when the power-failure occurs.
Further: the substrate potential generator sub-circuit comprises PMOS tube P5, PMOS tube PS, PMOS tube P7, PMOS tube P8, PMOS tube P9, NMOS tube N5, NMOS tube N6 and resistor R1;
Wherein, the gate of PMOS tube P5 is respectively connected with the gate of NMOS tube N5 and the source of PMOS tube P9 and serves as the input end of the substrate potential generator sub-circuit. The source of PMOS tube P5 is connected with the VDD power supply. The drain of the PMOS tube P5 is respectively connected with the drain of the
NMOS tube N5 and the gate of the NMOS tube N6. The source of the NMOS tube NS is grounded, and the source of the NMOS tube N6 is grounded. The drain of the NMOS tube
N6 is respectively connected with the gate of the PMOS tube P86, the drain of the PMOS tube P8 and the drain of the PMOS tube P9, and the source of the PMOS tube P6 is connected with the VDD power supply. The drain of the PMOS tube P6 is respectively connected with the substrate of the PMOS tube P8, the source of the PMOS tube P8, the substrate of the PMOS tube P8, the substrate of the PMOS tube P9, the gate of the PMOS tube P7, the drain of the PMOS tube P7 and the substrate of the PMOS tube P7. The source of the PMOS tube P7 is connected with the VDD power supply. The drain of the PMOS tube
P7 is used as the output end of the substrate potential generator sub-circuit; The gate of the
PMOS tube P8 is connected with the gate of the PMOS tube P9 and one end of the resistor
R1, respectively, and the other end of the resistor R1 is connected with the VDD power supply.
The beneficial effect of the above further scheme is that the substrate potential generator sub-circuit will generate the substrate potential of the PMOS tube, thus avoiding the situation that the substrate potential of the PMOS tube directly adopts the supply voltage.
The invention relates to a CMOS process compatible interface chip power-failure protection method, including the following steps:
S1. When the power supply of the interface chip compatible with CMOS technology fails, the substrate voltage is generated through the substrate potential generator sub-circuit;
S2. According to the substrate voltage generated by the substrate potential generator sub- circuit, control the PMOS tube P4 to close and complete the power-failure protection of the interface chip.
Further: the Step S1 is specific as follows:
When the power supply of the interface chip compatible with CMOS process fails, and the output end of the power-failure protection circuit of the interface chip compatible with
CMOS process is connected to the external high level, the high level of the output end of the power-failure protection circuit of the interface chip compatible with CMOS process passes through the PMOS tube P8 and PMOS tube P9 according to the conduction of PMOS tube P8 and PMOS tube PS. A high level substrate voltage Vbias is obtained.
Further, the Step S2 is specific as follows:
According to the substrate voltage Vbias, provide the substrate potential for PMOS tube P4. According to the gate voltage Vy=0V of NMOS tube N3 and the gate voltage
Vz=Vbias of PMOS tube P4, control the non-conduction of PMOS tube P4, cut off the substrate of PMOS tube P4 to the power supply path, and realize the power-failure protection of the interface chip.
The beneficial effects of the invention are as follows: (1) The power-failure protection circuit of the interface chip compatible with CMOS process of the invention does not require the process to have special devices, and can be realized under the standard CMOS process, and the circuit structure is simple. (2) The substrate potential generator sub-circuit will generate the substrate potential of the PMOS tube, which can effectively reduce the current backflow when the output end has a high potential in the case of power-failure, and realize the leakage current lower than
TuA index. (3) The invention solves the problem of backflow current from the output end to the power port under the condition of power-failure of the interface circuit. No matter whether the output end DOUT is high or low, the current to the power supply end will not be generated on average, so as to realize the power-failure protection function of the chip.
Brief Description of the Drawings
Figure 1 shows the schematic diagram of the power-failure protection circuit of the interface chip compatible with CMOS process.
Figure 2 shows the flow chart of a CMOS process compatible interface chip power- failure protection method.
Specific Implementation Methods
The specific implementation methods of the invention are described below in order to facilitate the understanding of the invention by those skilled in the art. However, it should be clear that the invention is not limited to the scope of the specific implementation methods, and that the changes are obvious to ordinary technicians in the art as long as they are within the spirit and scope of the invention defined and determined by the attached claims. All inventions and creations using the ideas of the invention are protected.
Implementation Method 1 5 As shown in Drawing 1, in one implementation method of the invention, a CMOS process compatible interface chip power-failure protection circuit comprises a power supply chip protection sub-circuit and a substrate potential generator sub-circuit;
Wherein, the first input of the power supply chip protection sub-circuit is the input of the CMOS process compatible interface chip power-failure protection circuit, and the output of the power supply chip protection sub-circuit is the output of the CMOS process compatible interface chip power-failure protection circuit;
The input end of the substrate potential generator sub-circuit is connected with the output end of the power supply chip protection sub-circuit, the output end of the substrate potential generator sub-circuit is connected with the second input end and the third input end of the power supply chip protection sub-circuit respectively;
The power supply chip protection sub-circuit is used in CMOS process compatible interface chip power-failure case, to prevent CMOS process compatible interface chip power-failure protection circuit output current backflow to the power port; The substrate potential generator sub-circuit is used to output the substrate voltage.
The power supply chip protection sub-circuit comprises a power supply chip protection sub-circuit including PMOS tube PO, PMOS tube P1, PMOS tube P2, PMOS tube P3, PMOS tube P4, NMOS tube NO, NMOS tube N1, NMOS tube N2, NMOS tube N3 and NMOS tube
N4:
Wherein, the gate of the PMOS tube PO is connected with the gate of the NMOS tube
NO, the source of the PMOS tube PO is connected with the VDD power supply, the gate of the NMOS tube NO is the first input of the power supply chip protection sub-circuit, the source of the NMOS tube NO is grounded, The drain of the NMOS tube NO is respectively connected with the drain of the PMOS tube PO, the gate of the PMOS tube P1 and the gate of the
NMOS tube N1, and the source of the PMOS tube P1 is connected with the VDD power supply. The drain of the PMOS tube P1 is respectively connected with the drain of the NMOS tube N1, the gate of the PMOS tube P2, the gate of the PMOS tube P3, the gate of the
NMOS tube N2 and the gate of the NMOS tube N3. The source of the NMOS tube N1 is grounded, and the source of the PMOS tube P2 is connected with the VDD power supply.
The drain of the PMOS tube P2 is respectively connected with the drain of the NMOS tube
N2 and the gate of the NMOS tube N4. The source of the NMOS tube N2 is grounded, and the source of the PMOS tube P3 is used as the second input of the power supply chip protection sub-circuit. The drain of the PMOS tube P3 is respectively connected with the drain of the NMOS tube N3 and the gate of the PMOS tube P4, the source of the NMOS tube N3 is grounded, the source of the PMOS tube P4 is connected with the VDD power supply, and the substrate of the PMOS tube P4 is the third input of the power supply chip protection sub-circuit. The drain of the PMOS tube P4 is connected with the drain of the
NMOS tube N4 and serves as the output end of the power supply chip protection sub-circuit, and the source of the NMOS tube N4 is grounded.
The beneficial effects of this implementation method are as follows: The CMOS process compatible interface chip power-failure protection circuit of the invention does not require the process to have special devices, and can be realized under the standard CMOS process, and the circuit structure is simple. The output voltage Vbias of the substrate potential generator sub-circuit provides the substrate potential for PMOS tube P4. The substrate potential generated by this circuit cuts off the unidirectional path from the output end of the interface chip power-failure protection circuit to the power-failure, and the Vbias voltage provides the power supply for PMOS tube P3, so as to avoid the PMOS tube P4 to be opened under the condition of power-failure, so as to avoid the backflow current from the output end to the power supply end when the power-failure occurs.
Implementation Method 2
This implementation method is for the specific circuit structure of the substrate potential generator subcircuit.
The substrate potential generator sub-circuit comprises PMOS tube P5, PMOS tube
P6, PMOS tube P7, PMOS tube P8, PMOS tube P9, NMOS tube N5, NMOS tube N6 and resistor R1;
Wherein, the gate of PMOS tube P5 is respectively connected with the gate of NMOS tube N5 and the source of PMOS tube P9 and serves as the input end of the substrate potential generator sub-circuit. The source of PMOS tube P5 is connected with the VDD power supply. The drain of the PMOS tube P5 is respectively connected with the drain of the
NMOS tube N5 and the gate of the NMOS tube N6. The source of the NMOS tube N5 is grounded, and the source of the NMOS tube N6 is grounded. The drain of the NMOS tube
N6 is respectively connected with the gate of the PMOS tube P8, the drain of the PMOS tube P8 and the drain of the PMOS tube P9, and the source of the PMOS tube P6 is connected with the VDD power supply. The drain of the PMOS tube P6 is respectively connected with the substrate of the PMOS tube P6, the source of the PMOS tube P8, the substrate of the PMOS tube P8, the substrate of the PMOS tube P9, the gate of the PMOS tube P7, the drain of the PMOS tube P7 and the substrate of the PMOS tube P7. The source of the PMOS tube P7 is connected with the VDD power supply. The drain of the PMOS tube
P7 is used as the output end of the substrate potential generator sub-circuit; The gate of the
PMOS tube P8 is connected with the gate of the PMOS tube P9 and one end of the resistor
R1, respectively, and the other end of the resistor R1 is connected with the VDD power supply.
The beneficial effects of this implementation method are as follows: The substrate potential generator sub-circuit will generate the substrate potential of the PMOS tube, so as to avoid the situation that the substrate potential of the PMOS tube directly adopts the power supply voltage. By cutting off the channel from the output end to the power supply, the current backflow at the output end with high potential can be effectively reduced when the power supply fails, and the leakage current can be lower than 1uA.
The working principle of the power loss protection circuit of the interface chip compatible with CMOS process of the invention is as follows: When the power supply VDD is normally supplied, the power supply VDD provides the power supply voltage for the interface chip. When the input signal DIN at the input end of the power-failure protection circuit of the interface chip compatible with CMOS technology is low, the NMOS tube N4 is turned on and the PMOS tube P4 is turned off. The output end DOUT end of the power- failure protection circuit of the interface chip compatible with CMOS process is pulled to the ground potential by NMOS tube N4. The NMOS tube N6 in the substrate potential generator sub-circuit is turned on, then the drain voltage of NMOS tube N6 is Vx=0V, and the PMOS tube P6 is turned on, so the output substrate voltage of the substrate potential generator sub-circuit is Vbias=VDD; When the input signal DIN is high, NMOS tube N4 is turned off,
PMOS tube P4 is turned on, and the output end DOUT is pulled to high potential by PMOS tube P4.
When the power supply is off (VDD=0V), and the output end DOUT external low level, the output end DOUT to the power end and the ground port no pressure difference, no current; When the output end DOUT is connected with a high external level, there is a voltage difference between the output end DOUT and the power supply end and the ground port. Due to the power supply failure, the gate of NMOS tube N4 is the ground potential, and the NMOS tube N4 is closed, so the current from the output end DOUT to the ground port will not be generated. The output DOUT is high level, the power supply is ground potential,
PMOS tube P8 and PMOS tube P9 are on, and the high-level DOUT generates substrate voltage Vbias through PMOS tube P8 and PMOS tube P9, so the substrate voltage
Vbias=VDOUT (output DOUT voltage), And provide substrate potential for PMOS tube P4;
In addition, due to the power-failure, the gate voltage of NMOS tube N3 is Vy=0V, and the gate voltage of PMOS tube P4 is Vz=Vbias. PMOS tube P4 will not be turn-on. No matter the output terminal is high or low, the average current will not be generated to the power supply terminal, so the chip power-failure protection function is realized.
Implementation Method 3
This implementation method is based on a CMOS process compatible interface chip power-failure protection circuit method.
As shown in Figure 2, in this implementation method, a CMOS process compatible interface chip power-failure protection method includes the following steps:
S1. When the power supply of the interface chip compatible with CMOS technology fails, the substrate voltage is generated through the substrate potential generator sub-circuit;
S2. According to the substrate voltage generated by the substrate potential generator sub-circuit, control the PMOS tube P4 to close and complete the power-failure protection of the interface chip.
The Step S1 is specific as follows:
When the power supply of the interface chip compatible with CMOS process fails, and the output end of the power-failure protection circuit of the interface chip compatible with
CMOS process is connected to the external high level, the high level of the output end of the power-failure protection circuit of the interface chip compatible with CMOS process passes through the PMOS tube P8 and PMOS tube P9 according to the conduction of PMOS tube P8 and PMOS tube P3. A high level substrate voltage Vbias is obtained.
The Step S2 is specifically as follows:
According to the substrate voltage Vbias, provide the substrate potential for PMOS tube P4.
According to the gate voltage Vy=0V of NMOS tube N3 and the gate voltage Vz=Vbias of PMOS tube P4, control the non-conduction of PMOS tube P4, cut off the substrate of
PMOS tube P4 to the power supply path, and realize the power-failure protection of the interface chip.
The invention has the following advantages: the invention solves the problem of backflow current from the output end to the power supply port when the power supply of the interface circuit is off, and has the characteristics of simple circuit structure, convenient use and standard CMOS technology.
In the description of the invention, it should be understood that the bearing or positional relationships indicated by the terms "center", "thickness", "upper", "lower", "horizontal", "top", "bottom", "inside", "outside", "radial", etc., are based on the bearing or positional relationships shown in the attached drawings and are only for the convenience of describing the invention and simplifying the description. Rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operate in a specific orientation, and therefore cannot be construed as a limitation of the present invention. Additionally, the terms "first", "second", "third" are used only for descriptive purposes and cannot be understood to indicate or imply relative importance or the number of technical characteristics implicitly specified.
Therefore, a feature defined by "first", "second", "third" may explicitly or implicitly include one or more of these features.

Claims (6)

ConclusiesConclusions 1. Een met het CMOS-proces compatibele schakeling voor de beveiliging van een interfacechip tegen stroomuitval, met het kenmerk, dat deze schakeling een subschakeling voor de beveiliging van de voedingschip en een subschakeling voor het genereren van een substraatpotentiaal omvat, waarbij de eerste ingang van de subschakeling voor de beveiliging van de voedings- chip de ingang is voor de met het CMOS-proces compatibele schakeling voor de beveiliging van de interfacechip tegen stroomuitval, en de uitgang van de subschakeling voor de beveiliging van de voedingschip de uitgang is van de schakeling voor de beveiliging van de met het CMOS-proces compatibele interfacechip tegen stroomuitval; waarbij de ingang van de subschakeling voor het genereren van de substraat- potentiaal is verbonden met de uitgang van de subschakeling voor de beveiliging van de voedingschip, de uitgang van de substraatpotentiaalgenerator respectievelijk is verbonden met de tweede ingang en de derde ingang van de subschakeling voor de beveiliging van de voedingschip; waarbij de subschakeling voor de beveiliging van de voedingschip wordt gebruikt in het geval van stroomuitval van de met het CMOS-proces compatibele interfacechip, om te voorkomen dat bij stroomuitval de uitgangsstroom wordt teruggevoerd naar de voedings- poort; de subschakeling voor het genereren van de substraatpotentiaal wordt gebruikt om de substraatspanning af te geven.CLAIMS 1. A CMOS process compatible circuit for protecting an interface chip against power failure, characterized in that the circuit comprises a power supply chip protection subcircuit and a substrate potential generation subcircuit, the first input of which is the power chip protection subcircuit is the input to the CMOS process compatible interface chip protection circuit against power failure, and the output of the power chip protection subcircuit is the output of the power chip protection circuit the protection of the interface chip compatible with the CMOS process against power failure; wherein the input of the substrate potential generating subcircuit is connected to the output of the power chip protection subcircuit, the output of the substrate potential generator is respectively connected to the second input and the third input of the power chip protection subcircuit power chip security; wherein the power supply chip protection subcircuit is used in case of power failure of the CMOS process compatible interface chip to prevent the output current from being returned to the power port in the event of power failure; the subcircuit for generating the substrate potential is used to output the substrate voltage. 2. De met het CMOS-proces compatibele schakeling voor de beveiliging van een interfacechip tegen stroomuitval volgens conclusie 1, met het kenmerk, dat de sub- schakeling voor de beveiliging van de voedingschip een PMOS buis PO, een PMOS buis P1, een PMOS buis P2, een PMOS buis P3, een PMOS buis P4, een NMOS buis NO, een NMOS buis N1, een NMOS buis N2, een NMOS buis N3 en een NMOS buis N4 omvat; waarbij de poort van PMOS-buis PO is verbonden met de poort van NMOS-buis NO, de bron van PMOS-buis PO is verbonden met de VDD-voeding, de poort van NMOS-buis NO de eerste ingang van de subschakeling voor de bescherming van de voedingschip is, de bron van NMOS-buis NO is geaard, de afvoer van NMOS-buis NO respectievelijk is verbonden met de afvoer van PMOS-buis PO, de poort van PMOS-buis P1 en de poort van NMOS-buis N1, en de bron van PMOS-buis P1 is verbonden met de VDD-voeding, de afvoer van PMOS-buis P1 respectievelijk is verbonden met de afvoer van NMOS-buis N1, de poort van PMOS-buis P2, de poort van PMOS-buis P3, de poort van de NMOS-buis N2 en de poort van NMOS-buis N3, de bron van NMOS-buis N1 is geaard, en de bron van PMOS- buis P2 is verbonden met de VDD-voeding, de afvoer van PMOS-buis P2 respectievelijk is verbonden met de afvoer van NMOS-buis N2 en de poort van NMOS-buis N4, de bron vanThe CMOS process compatible interface chip protection circuit against power failure according to claim 1, characterized in that the power supply chip protection subcircuit comprises a PMOS tube PO, a PMOS tube P1, a PMOS tube P2, a PMOS tube P3, a PMOS tube P4, an NMOS tube NO, an NMOS tube N1, an NMOS tube N2, an NMOS tube N3 and an NMOS tube N4; where the gate of PMOS tube PO is connected to the gate of NMOS tube NO, the source of PMOS tube PO is connected to the VDD power supply, the gate of NMOS tube NO is the first input of the protection subcircuit of the power supply chip, the source of NMOS tube NO is grounded, the drain of NMOS tube NO is respectively connected to the drain of PMOS tube PO, the port of PMOS tube P1 and the port of NMOS tube N1, and the source of PMOS tube P1 is connected to the VDD power supply, the drain of PMOS tube P1 is respectively connected to the drain of NMOS tube N1, the port of PMOS tube P2, the port of PMOS tube P3 , the port of NMOS tube N2 and the port of NMOS tube N3, the source of NMOS tube N1 is grounded, and the source of PMOS tube P2 is connected to the VDD power supply, the drain of PMOS tube P2 is respectively connected to the drain of NMOS tube N2 and the gate of NMOS tube N4, the source of NMOS-buis N2 is geaard, en de bron van PMOS-buis P3 wordt gebruikt als tweede ingang van de subschakeling voor de beveiling van de voedingschip, de afvoer van PMOS-buis P3 respectievelijk is verbonden met de afvoer van NMOS-buis N3 en de poort van PMOS-buis P4, de bron van NMOS-buis N3 is geaard, de bron van PMOS-buis P4 is verbonden met de VDD-voeding, en het substraat van PMOS-buis P4 de derde ingang van de subschakeling voor de beveiliging van de voedingschip is, de afvoer van PMOS-buis P4 is verbonden met de afvoer van NMOS-buis N4 en als uitgang dient van de subschakeling voor de beveiliging van de voedingschip, en de bron van NMOS-buis N4 is geaard.NMOS tube N2 is grounded, and the source of PMOS tube P3 is used as the second input of the power chip protection subcircuit, the drain of PMOS tube P3 is respectively connected to the drain of NMOS tube N3 and the gate of PMOS tube P4, the source of NMOS tube N3 is grounded, the source of PMOS tube P4 is connected to the VDD power supply, and the substrate of PMOS tube P4 is the third input of the subcircuit for the protection of is the power chip, the drain of PMOS tube P4 is connected to the drain of NMOS tube N4 and outputs the power chip protection subcircuit, and the source of NMOS tube N4 is grounded. 3. De met het CMOS-proces compatibele schakeling voor de beveiliging van een interfacechip tegen stroomuitval volgens conclusie 2, met het kenmerk, dat de sub- schakeling voor het genereren van de substraatpotentiaal de PMOS-buis P5, de PMOS-buis P6, de PMOS-buis P7, de PMOS-buis P8, de PMOS-buis P9, de NMOS-buis N5, de NMOS- buis N6 en weerstand R1 omvat, waarbij de poort van de PMOS-buis P5 respectievelijk is verbonden met de poort van de NMOS-buis N5 en de bron van de PMOS-buis P9, en dient als ingang voor de sub- schakeling voor het genereren van de substraatpotentiaal, de bron van de PMOS-buis P5 is verbonden met de VDD-voeding, de afvoer van de PMOS-buis P5 respectievelijk is verbonden met de afvoer van de NMOS-buis N5 en de poort van de NMOS-buis N6, de bron van de NMOS-buis N5 is geaard, en de bron van de NMOS-buis N6 is geaard, de afvoer van de NMOS-buis N86 is respectievelijk verbonden met de poort van de PMOS-buis P6, de afvoer van de PMOS-buis P8 en de afvoer van de PMOS-buis P9, en de bron van de PMOS- buis P6 is verbonden met de VDD-voeding, de afvoer van de PMOS-buis P6 is respectievelijk verbonden met het substraat van de PMOS-buis P86, de bron van PMOS-buis P8, het substraat van PMOS-buis P8, het substraat van PMOS-buis P9, de poort van PMOS- buis P7, de afvoer van PMOS-buis P7 en het substraat van de PMOS-buis P7, de bron van PMOS-buis P7 is verbonden met de VDD-voeding, de afvoer van de PMOS-buis P7 wordt gebruikt als de uitgang van de subschakeling voor het genereren van de substraatpotentiaal, de poort van de PMOS-buis P8 is respectievelijk verbonden met de poort van de PMOS- buis P9 en éen uiteinde van weerstand R1, en het andere uiteinde van de weerstand R1 is verbonden met de VDD-voeding.The CMOS process compatible circuit for protecting an interface chip against power failure according to claim 2, characterized in that the subcircuit for generating the substrate potential includes the PMOS tube P5, the PMOS tube P6, the PMOS tube P7, the PMOS tube P8, the PMOS tube P9, the NMOS tube N5, the NMOS tube N6 and resistor R1, with the port of the PMOS tube P5 connected to the port of the NMOS tube N5 and the source of the PMOS tube P9, and serves as an input to the sub-circuit for generating the substrate potential, the source of the PMOS tube P5 is connected to the VDD power supply, the drain of the PMOS tube P5 is respectively connected to the drain of the NMOS tube N5 and the port of the NMOS tube N6, the source of the NMOS tube N5 is grounded, and the source of the NMOS tube N6 is grounded, the drain of the NMOS tube N86 is respectively connected to the gate of the PMOS tube P6, the drain of the PMOS tube P8 and the drain of the PMOS tube P9, and the source of the PMOS tube P6 is connected to the VDD power supply, the drain of PMOS tube P6 is respectively connected to the substrate of PMOS tube P86, the source of PMOS tube P8, the substrate of PMOS tube P8, the substrate of PMOS tube P9, the gate of PMOS tube P7, the drain of PMOS tube P7 and the substrate of PMOS tube P7, the source of PMOS tube P7 is connected to the VDD power supply, the drain of PMOS tube P7 is used as the output of the subcircuit for generating the substrate potential, the gate of the PMOS tube P8 is respectively connected to the gate of the PMOS tube P9 and one end of resistor R1, and the other end of the resistor R1 is connected with the VDD power supply. 4. Werkwijze voor de beveiliging van een interfacechip tegen stroomuitval, die compatibel is met het CMOS-proces, welke werkwijze de volgende stappen omvat:A method for protecting an interface chip against power failure, compatible with the CMOS process, comprising the steps of: S1. het genereren van een substraatspanning door middel van een subschakeling voor de substraatpotentiaalgenerator, wanneer de voeding van de met het CMOS-proces compatibele interfacechip uitvalt;S1. generating a substrate voltage by means of a subcircuit for the substrate potential generator when the power supply of the interface chip compatible with the CMOS process fails; S2. volgens de substraatspanning die door de subschakeling van de substraat- potentiaalgenerator wordt gegenereerd, wordt geregeld dat PMOS-buis P4 wordt gesloten en de stroomuitvalbeveiliging van de interfacechip wordt voltooid.S2. according to the substrate voltage generated by the subcircuit of the substrate potential generator, PMOS tube P4 is controlled to close and the interface chip power failure protection is completed. 5. Werkwijze volgens conclusie 4 voor de beveiliging van een interfacechip tegen stroom- uitval, die compatibel is met het CMOS-proces, met het kenmerk, dat stap S1 specifiek is wanneer de voeding van de interfacechip, die compatibel is met het CMOS-proces, uitvalt en de uitgang van de beveiliginsschakeling tegen stroomuitval van de interfacechip, die compatibel is met het CMOS-proces, is verbonden met het externe hoge niveau, waarbij het hoge niveau van de uitgang van de beveiligingsschakeling tegen stroomuitval van de met het CMOS-proces compatibele interfacechip door PMOS-buis P8 en PMOS-buis P9 loopt volgens de geleiding van PMOS-buis P8 en PMOS-buis P9, waardoor een substraat- spanning Vbias van hoog niveau wordt verkregen.A method according to claim 4 for protecting an interface chip compatible with the CMOS process against power failure, characterized in that step S1 is specific when the power supply of the interface chip compatible with the CMOS process , fails, and the output of the power failure protection circuit of the interface chip, which is compatible with the CMOS process, is connected to the external high level, the high level of the output of the power failure protection circuit of the CMOS process compatible interface chip through PMOS tube P8 and PMOS tube P9 follows the conduction of PMOS tube P8 and PMOS tube P9, thereby obtaining a high level substrate voltage V bias. 6. Werkwijze volgens conclusie 5 voor de beveiliging van een interfacechip tegen stroom- uitval, die compatibel is met het CMOS-proces, met het kenmerk, dat volgens de substraatspanning Vbias de substraatpotentiaal voor PMOS-buis P4 wordt verstrekt, volgens de poortspanning Vy=0V van NMOS-buis N3 en de poortspanning Vz=Vbias van PMOS-buis P4 wordt de niet-geleiding van PMOS-buis P4 geregeld, wordt het substraat van PMOS-buis P4 naar het voedingspad afgesneden en wordt de beveiliging van de interface- chip tegen stroomuitval gerealiseerd.A method according to claim 5 for protecting an interface chip against power failure, compatible with the CMOS process, characterized in that the substrate potential for PMOS tube P4 is supplied according to the substrate voltage Vbias, according to the gate voltage Vy= 0V of NMOS tube N3 and the gate voltage Vz=Vbias of PMOS tube P4, the non-conductivity of PMOS tube P4 is controlled, the substrate of PMOS tube P4 to the power path is cut off, and the protection of the interface chip is against power failure.
NL2034089A 2022-02-17 2023-02-03 A CMOS Process Compatible Interface Chip power-failure Protection Circuit and The Method Thereof NL2034089B1 (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN202210147343.5A CN114498572B (en) 2022-02-17 2022-02-17 CMOS process compatible interface chip power-down protection circuit and method

Publications (2)

Publication Number Publication Date
NL2034089A true NL2034089A (en) 2023-03-17
NL2034089B1 NL2034089B1 (en) 2024-01-18

Family

ID=81481875

Family Applications (1)

Application Number Title Priority Date Filing Date
NL2034089A NL2034089B1 (en) 2022-02-17 2023-02-03 A CMOS Process Compatible Interface Chip power-failure Protection Circuit and The Method Thereof

Country Status (2)

Country Link
CN (1) CN114498572B (en)
NL (1) NL2034089B1 (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN117749158B (en) * 2024-02-19 2024-04-19 北京中天星控科技开发有限公司成都分公司 Anti-backflow protection circuit for power failure of interface chip

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5844425A (en) * 1996-07-19 1998-12-01 Quality Semiconductor, Inc. CMOS tristate output buffer with having overvoltage protection and increased stability against bus voltage variations
EP0668658B1 (en) * 1994-02-16 2001-05-09 Kabushiki Kaisha Toshiba Output circuit for use in a semiconductor integrated circuit
CN208723866U (en) * 2018-09-13 2019-04-09 厦门安斯通微电子技术有限公司 A kind of power-down protection circuit for CMOS output

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6965264B1 (en) * 2003-06-30 2005-11-15 National Semiconductor Corporation Adaptive threshold scaling circuit
JP5338387B2 (en) * 2009-03-05 2013-11-13 ミツミ電機株式会社 Power supply switching device
CN105049029B (en) * 2015-07-06 2018-05-04 上海巨微集成电路有限公司 A kind of PMOS tube substrate switching circuit
CN106656148B (en) * 2016-12-20 2020-05-15 峰岹科技（深圳）有限公司 Bidirectional IO circuit for preventing current from flowing backwards
CN110868204A (en) * 2019-11-04 2020-03-06 深圳市国微电子有限公司 Anti-backflow circuit, bidirectional level converter and integrated circuit
CN210986074U (en) * 2019-11-04 2020-07-10 深圳市国微电子有限公司 Anti-backflow circuit, bidirectional level converter and integrated circuit
CN212305284U (en) * 2020-06-24 2021-01-05 上海芯跳科技有限公司 Substrate potential selection circuit for PMOS (P-channel metal oxide semiconductor) transistor

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0668658B1 (en) * 1994-02-16 2001-05-09 Kabushiki Kaisha Toshiba Output circuit for use in a semiconductor integrated circuit
US5844425A (en) * 1996-07-19 1998-12-01 Quality Semiconductor, Inc. CMOS tristate output buffer with having overvoltage protection and increased stability against bus voltage variations
CN208723866U (en) * 2018-09-13 2019-04-09 厦门安斯通微电子技术有限公司 A kind of power-down protection circuit for CMOS output

Also Published As

Publication number Publication date
CN114498572A (en) 2022-05-13
CN114498572B (en) 2022-10-04
NL2034089B1 (en) 2024-01-18

Similar Documents

Publication Publication Date Title
CN108494234B (en) Floating power rail suitable for GaN high-speed gate drive circuit
US8803580B2 (en) Power-on-reset (POR) circuit with zero steady-state current consumption and stable pull-up voltage
NL2034089B1 (en) A CMOS Process Compatible Interface Chip power-failure Protection Circuit and The Method Thereof
CN102709883B (en) Under-voltage protection circuit of switch power source
CN108667443B (en) Power-on reset circuit
CN114567837B (en) Sensor microphone output protection circuit and sensor microphone
CN104158516A (en) Voltage comparator
CN105511540B (en) Band-gap reference starting circuit with super-low leakage current
US9601995B1 (en) Low power radio frequency envelope detector
EP1034619B1 (en) Zero power power-on-reset circuit
CN107294516B (en) Power-on reset circuit without static power consumption
CN107885267B (en) Operating method for bandgap voltage reference circuit
JP2000306385A (en) Complementary differential input buffer for semiconductor memory
CN114499490A (en) Interface chip power-down protection circuit and method
US20130285703A1 (en) Asymmetrical bus keeper
CN101459424B (en) Output unit,input unit and input & output element
CN106374886B (en) Non-repeatable triggering CMOS integrated monostable circuit
CN202616756U (en) Undervoltage protecting circuit of switching power supply
CN108768362B (en) Pure enhancement type MOS tube static power consumption-free power-on reset circuit
CN208581212U (en) A amplifier negative port protects circuit
CN109974863B (en) Integration circuit applied to ultraviolet focal plane detector
CN210604769U (en) Undervoltage detection circuit with zero static power consumption
CN106301299A (en) Relevant delay circuit weak to temperature and supply voltage
CN108155901B (en) Parameter drift resistance inverter
CN103391082B (en) The replacement circuit of low threshold voltage diode