CN110417402B

CN110417402B - Anti-floating circuit

Info

Publication number: CN110417402B
Application number: CN201810389713.XA
Authority: CN
Inventors: 庄荣圳; 黄绍璋; 陈敬文; 庄介尧; 林宇彦
Original assignee: Vanguard International Semiconductor Corp
Current assignee: Vanguard International Semiconductor Corp
Priority date: 2018-04-27
Filing date: 2018-04-27
Publication date: 2023-04-25
Anticipated expiration: 2038-04-27
Also published as: CN110417402A

Abstract

The invention provides an anti-floating circuit, which comprises a pull-up circuit, a pull-down circuit and a control circuit. The pull-up circuit comprises a first P-type transistor and a second P-type transistor and is coupled with a first power end. The pull-down circuit comprises a first N-type transistor and a second N-type transistor, and is coupled to a second power supply terminal. A first path is formed between the first P-type transistor and the first N-type transistor. A second path is provided between the second P-type transistor and the second N-type transistor. A third path is provided between the first P-type transistor and the second power terminal. In the first mode, the control circuit turns on the first and second paths and turns off the third path. In the second mode, the control circuit does not conduct the first and second paths and conducts the third path. The anti-floating circuit provided by the invention can not cause the misoperation of the integrated circuit when the input signal is not an accurate signal.

Description

Anti-floating circuit

Technical Field

The present invention relates to an anti-floating circuit, and more particularly to an anti-floating circuit having a pull-up circuit and a pull-down circuit.

Background

With the advancement of technology, the size of integrated circuits is becoming smaller. Generally, each integrated circuit operates according to at least one input signal. However, when the input signal is not the correct signal, the integrated circuit is liable to malfunction.

Disclosure of Invention

The invention provides an anti-floating circuit, which generates a first output signal according to a first input signal in a first mode and sets the first output signal equal to a first preset value in a second mode, and comprises a first pull-up circuit, a first pull-down circuit and a first control circuit. The first pull-up circuit comprises a first P-type transistor and a second P-type transistor. The source of the first P-type transistor is coupled to a first power terminal. The drain of the first P-type transistor provides a first output signal. The source of the second P-type transistor is coupled to the first power terminal. The drain of the second P-type transistor is coupled to the gate of the first P-type transistor. The gate of the second P-type transistor is coupled to the drain of the first P-type transistor. The first pull-down circuit comprises a first N-type transistor and a second N-type transistor. The gate of the first N-type transistor receives a first inversion signal. The source of the first N-type transistor is coupled to a second power terminal. The gate of the second N-type transistor receives an input signal. The source of the second N-type transistor is coupled to the second power terminal. The first control circuit is coupled between the first pull-up circuit and the first pull-down circuit. In the first mode, the first control circuit turns on a first path between the first P-type transistor and the first N-type transistor, a second path between the second P-type transistor and the second N-type transistor, and a third path between the first P-type transistor and the second power supply terminal. In the second mode, the first control circuit does not conduct the first path and the second path, and conducts the third path. The anti-floating circuit provided by the invention can not cause the misoperation of the integrated circuit when the input signal is not an accurate signal.

Drawings

FIG. 1A is a schematic diagram of an anti-floating circuit according to the present invention.

FIG. 1B is a schematic diagram of an anti-floating circuit according to the present invention.

Fig. 2A is a schematic diagram of a signal generating circuit according to an embodiment of the invention.

Fig. 2B is a schematic diagram of another embodiment of the signal generating circuit of the present invention.

Fig. 3A is a schematic diagram of a pulse generating circuit according to one embodiment of the present invention.

Fig. 3B is a schematic diagram of another embodiment of the pulse generating circuit according to the present invention.

Fig. 4 is a schematic diagram of a delay circuit according to one embodiment of the present invention.

Fig. 5 is a schematic diagram of another embodiment of the delay circuit of the present invention.

Reference numerals and signs

100A, 100B: an anti-floating circuit;

110. 130, 200A, 200B: a signal generating circuit;

120: a core circuit;

PW1, PW2: a power supply terminal;

IN1, IN2, IN: inputting a signal;

OUT1, OUT2, OUT, OUTB: outputting a signal;

121. 123: a switch;

122: a load;

210: a pull-up circuit;

220: a control circuit;

230: a pull-down circuit;

211. 212, 251, 331, 413, 421, 433, 513, 523, 533, 543: a P-type transistor;

231. 232, 224-226, 252, 332, 414, 434, 441, 514, 524, 534, 544: an N-type transistor;

221-223: a control element;

240. 300A, 300B: a pulse generating circuit;

INB: an inverted signal;

PA1 to PA3: a path;

os_ N, OS _nb: a pulse signal;

250. 330, 410, 430, 510, 520, 530, 540: an inverter;

310. 400, 500: a delay circuit;

320: a logic circuit;

VPW1: a level;

VD: delaying the signal;

321: a NAND gate;

420. 440: a capacitor;

411. 431, 511, 521, 531, 541: an input end;

412. 432, 512, 522, 532, 542: and an output terminal.

Detailed Description

The present invention will be described in more detail with reference to the drawings, wherein the invention is not limited to the embodiments. The present description provides various examples to illustrate the features of various embodiments of the present invention. The arrangement of the elements in the embodiments is for illustration, and is not intended to limit the invention. In addition, the repetition of the reference numerals in the embodiments is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments.

FIG. 1A is a schematic diagram of an anti-floating circuit according to the present invention. As shown, the anti-floating circuit 100A includes a signal generating circuit 110 and a core circuit 120. The signal generating circuit 110 is coupled between the power supply terminals PW1 and PW2, and generates an output signal OUT1. In one possible embodiment, the signal generating circuit 110 is a level shifter (level shifter). IN this example, the signal generating circuit 110 converts a level of an input signal IN1 and takes the converted result as an output signal OUT1.

When the input signal IN1 is at a first level, the output signal OUT1 is at a second level. When the input signal IN1 is at a third level, the output signal OUT1 is at a fourth level. In one possible embodiment, the second level is higher than the first level. For example, the first level is about 3.3V and the second level is about 6V to 7V. In addition, the third level may be equal to the fourth level, which are all 0V.

In another possible embodiment, the first level is greater than the second level and the fourth level is greater than the third level. In this example, the fourth level may be greater than the first level. For example, the first level is about 3.3V and the fourth level is about 6V to 7V. In addition, the second level may be equal to the third level, both of which are 0V.

The core circuit 120 is coupled between the power supply terminals PW1 and PW2, and receives the output signal OUT1. In one possible embodiment, core circuit 120 is a non-volatile memory (NVM), but is not intended to limit the present invention. In other embodiments, core circuit 120 may be other kinds of integrated circuits. Generally, core circuit 120 has many elements, but for simplicity, FIG. 1A only shows some of the elements relevant to the present invention, with load 122 representing other elements within core circuit 120.

As shown, the core circuit 120 includes at least one switch 121. In the present embodiment, the switch 121 is coupled between the power source PW1 and the load 122. The switch 121 determines whether to transmit the power of the power source PW1 to the load 122 according to the output signal OUT1. For example, when the output signal OUT1 is in a first state (e.g. low level or high level), the switch 121 transmits the power of the power source PW1 to the load 122. In this example, when the output signal OUT1 is in the second state (e.g. high level or low level), the switch 121 does not transmit the power of the power source PW1 to the load 122. In one possible embodiment, the switch 121 is a P-type transistor, but is not intended to limit the present invention. In other embodiments, the switch 121 is an N-type transistor. In other embodiments, the switch 121 may be coupled between the power source PW2 and the load 122, and determines whether to transmit the power source PW2 to the load 122 according to the output signal OUT1.

Since the signal generating circuit 110 generates the output signal OUT1 according to the input signal IN1, the level of the output signal OUT1 may be IN a floating state (floating) when the input signal IN1 is not ready. Therefore, the switch 121 may be turned on by the erroneous output signal OUT1, resulting in malfunction of the core circuit 120. Furthermore, if an electrostatic discharge (electrostatic discharge; ESD) event occurs between the power supply terminals PW1 and PW2 while the switch 121 is turned on, an electrostatic discharge current flows from the switch 121 into the core circuit 120, thereby burning the core circuit 120.

Therefore, IN a non-ready mode, the signal generating circuit 110 sets the level of the output signal OUT1 equal to a predetermined value for turning off the switch 121 because the input signal IN1 is not ready. Therefore, the core circuit 120 does not malfunction. Furthermore, in this mode, if an esd event occurs between the power supply terminals PW1 and PW2, the switch 121 is not turned on, so that the esd current does not flow into the core circuit 120.

IN a ready mode, the signal generating circuit 110 generates the output signal OUT1 according to the input signal IN1 since the input signal IN1 is ready. In this mode, since the power supply terminals PW1 and PW2 have received the corresponding operating voltages (e.g., 6V and 0V), the signal generating circuit 110 sets the high level of the output signal OUT1 equal to the voltage of the power supply terminal PW1, and sets the low level of the output signal OUT1 equal to the voltage of the power supply terminal PW2.

Fig. 1B is a schematic diagram of another embodiment of an anti-floating circuit according to the present invention. FIG. 1B is similar to FIG. 1A, except that the anti-floating circuit 100B of FIG. 1B further includes a signal generating circuit 130. IN the present embodiment, the signal generating circuit 130 is also coupled between the power terminals PW1 and PW2, and generates an output signal OUT2 according to an input signal IN2. In one possible embodiment, the signal generating circuit 130 is a level shifter. IN this example, the signal generating circuit 130 converts the level of the input signal IN2 and takes the converted result as the output signal OUT2. IN other embodiments, the input signal IN1 may be the same or different from the input signal IN2. Since the operation of the signal generating circuit 130 is the same as that of the signal generating circuit 110, the description thereof will not be repeated.

In this embodiment, the core circuit 120 further includes a switch 123. The switch 123 is connected in series with the load 122 and determines whether to transmit the power of the power source PW2 to the load 122 according to the output signal OUT2. For example, when the output signal OUT2 is in a first state (e.g., low level or high level), the switch 123 does not transmit the power of the power source PW2 to the load 122. In this example, when the output signal OUT2 is in the second state (e.g. high level or low level), the switch 123 transmits the power of the power source PW2 to the load 122. In one possible embodiment, the switch 123 is an N-type transistor, but is not intended to limit the present invention. In other embodiments, the switch 123 is a P-type transistor.

In some embodiments, switches 121 and 123 are the same type of transistor, such as P-type transistors or N-type transistors. In another embodiment, switches 121 and 123 are different types of transistors. For example, when the switch 121 is a P-type transistor, the switch 123 is an N-type transistor; when the switch 121 is an N-type transistor, the switch 123 is a P-type transistor. In other embodiments, when switch 121 is on, switch 123 is also on. When switch 121 is not conductive, switch 123 is also not conductive.

IN an unready mode, since the input signals IN1 and IN2 have not reached the target level, the

signal generating circuits

110 and 130 respectively set the levels of the output signals OUT1 and OUT2 equal to a first preset value and a second preset value for turning off the

switches

121 and 123. Since the

switches

121 and 123 are not turned on, the core circuit 120 can be prevented from malfunctioning. Furthermore, since the

switches

121 and 123 are not turned on, when an esd event occurs between the power supply terminals PW1 and PW2, the esd current does not enter the core circuit 120.

When the input signals IN1 and IN2 reach a first target level and a second target level, respectively, the

signal generating circuits

110 and 130 enter a ready mode. IN this mode, the signal generating circuit 110 generates an output signal OUT1 according to the input signal IN1 for conducting or not conducting the switch 121. IN addition, the signal generating circuit 130 generates an output signal OUT2 according to the input signal IN2 to turn on or off the switch 123. Since the

signal generating circuits

110 and 130 generate the correct output signals OUT1 and OUT2, the core circuit 120 can be prevented from malfunctioning.

Fig. 2A is a schematic diagram of a signal generating circuit according to an embodiment of the invention. As shown, the signal generating circuit 200A includes a pull-up circuit 210, a control circuit 220, and a pull-down circuit 230. Pull-up circuit 210 includes P-

type transistors

211 and 212. The source of the P-type transistor 211 is coupled to the power source PW1, and the drain thereof provides the output signal OUT. The source of the P-type transistor 212 is coupled to the power source PW1, the drain thereof is coupled to the gate of the P-type transistor 211, and the gate thereof is coupled to the drain of the P-type transistor 211. In one possible embodiment, when the signal generating circuit 200A is used as the

signal generating circuit

110 or 130 in fig. 1B, the output signal OUT is used as the output signal OUT1 or OUT2.

Pull-down circuit 230 includes N-type transistors 231 and 232. The gate of the N-type transistor 231 receives an inversion signal INB, the source thereof is coupled to the power source PW2, and the drain thereof is coupled to the control circuit 220. The gate of the N-type transistor 232 receives the input signal IN, the source thereof is coupled to the power source PW2, and the drain thereof is coupled to the control circuit 220. IN the present embodiment, the inverted signal INB is an inverted signal of the input signal IN.

IN one possible embodiment, when the signal generating circuit 200A is used as the

signal generating circuit

110 or 130 IN fig. 1B, the input signal IN is the input signal IN1 or IN2. IN other embodiments, the signal generating circuit 200A further has an inverter (not shown) for inverting the input signal IN to generate the inverted signal INB. In some embodiments, the inverter is disposed outside of the signal generating circuit 200A.

The control circuit 220 is coupled between the pull-up circuit 210 and the pull-down circuit 230. IN a ready mode (i.e., the input signal IN is ready), the control circuit 220 turns on a path PA1 between the P-type transistor 211 and the N-type transistor 231 and a path PA2 between the P-type transistor 212 and the N-type transistor 232, and turns off a path PA3 between the P-type transistor 211 and the power source terminal PW2. IN this mode, the signal generating circuit 200A generates the output signal OUT according to the input signal IN.

When the input signal IN does not reach the target level or the input signal IN does not enter the signal generating circuit 200A, the signal generating circuit 200A enters an unready mode. In the not ready mode, the control circuit 220 does not turn on the paths PA1 and PA2 and turns on the path PA3. In this mode, the control circuit 220 sets the level of the output signal OUT equal to a predetermined value, so as to not turn on the switch (121 in FIG. 1A) in the core circuit, thereby avoiding the malfunction of the core circuit.

In the present embodiment, the control circuit 220 includes control elements 221 to 223. The control element 221 is coupled between the drain of the P-type transistor 211 and the drain of the N-type transistor 231. The control element 221 determines whether to turn on the path PA1 according to the pulse signal os_nb. IN a ready mode (i.e., the input signal IN is ready), the pulse signal osnb has a first level. Accordingly, the control element 221 turns on the path PA1. IN an unready mode (i.e., the input signal IN is not ready), the pulse signal osnb has a second level. Therefore, the control element 221 does not turn on the path PA1.

The present invention is not limited to the type of control element 221. In this embodiment, the control element 221 is an N-type transistor 224. The gate of the N-type transistor 224 receives the pulse signal OS_NB, the drain thereof is coupled to the drain of the P-type transistor 211, and the source thereof is coupled to the drain of the N-type transistor 231. In the ready mode, the pulse signal osnb is high, and the N-type transistor 224 is turned on. Thus, the path PA1 is turned on. In the not ready mode, the pulse signal osnb is low and the N-type transistor 224 is not turned on. Thus, path PA1 is non-conductive. In other embodiments, the control element 221 is a P-type transistor.

The control element 222 is coupled between the drain of the P-type transistor 212 and the drain of the N-type transistor 232. The control element 222 determines whether to turn on the path PA2 according to the pulse signal os_nb. IN a ready mode (e.g., the input signal IN has reached the target level), the pulse signal osnb is at the first level. Thus, the control element 222 turns on the path PA2. IN a non-ready mode (i.e., the input signal IN has not reached the target level), the pulse signal osnb is at the second level. Thus, the control element 222 does not turn on the path PA2.

The present invention is not limited to the type of control element 222. In this embodiment, the control element 222 is an N-type transistor 225. The gate of the N-type transistor 225 receives the pulse signal OS_NB, the drain thereof is coupled to the drain of the P-type transistor 212, and the source thereof is coupled to the drain of the N-type transistor 232. In the ready mode, the pulse signal osnb is high and the N-type transistor 225 is turned on. Thus, path PA2 is turned on. In the not ready mode, the pulse signal osnb is low and the N-type transistor 225 is not turned on. Thus, path PA2 is non-conductive. In other embodiments, the control element 222 is a P-type transistor.

The control device 223 is coupled between the gate of the P-type transistor 211 and the power source PW2. The control element 223 determines whether to turn on the path PA3 between the P-type transistor 211 and the power source PW2 according to the pulse signal osjv. In a non-ready mode, the pulse signal OS_N is at a third level. Thus, the control element 223 turns on the path PA3. In a ready mode, the pulse signal osn is at a fourth level. Therefore, the control element 223 does not conduct the path PA3.

The present invention is not limited to the kind of the control element 223. In this embodiment, the control device 223 is an N-type transistor 226. The gate of the N-type transistor 226 receives the pulse signal OS_N, the drain thereof is coupled to the gate of the P-type transistor 211, and the source thereof is coupled to the power source PW2. In the ready mode, the pulse signal osn is low and the N-type transistor 226 is not turned on. Therefore, the path PA3 is not turned on. In the not ready mode, the pulse signal osn is high, and the N-type transistor 226 is turned on. Thus, path PA3 is conductive. In other embodiments, the control element 223 is a P-type transistor.

In one possible embodiment, the pulse signal os_n is inverted from the pulse signal os_nb, but is not intended to limit the present invention. When the

control elements

221 and 222 are N-type transistors and the control element 223 is a P-type transistor, or when the

control elements

221 and 222 are P-type transistors and the control element 223 is an N-type transistor, the pulse generating circuit 240 only needs to generate a single pulse signal to control the control elements 221 to 223.

In the present embodiment, the pulse signals OS_NB and OS_N are generated by a pulse generating circuit 240. The pulse generating circuit 240 is coupled between the power supply terminals PW1 and PW2. The pulse generating circuit 240 generates pulse signals osnb and osn according to the levels of the power supply terminals PW1 and PW2. In some embodiments, different pulse generation circuits may generate different pulse signals.

Taking fig. 1B as an example, the number of pulse signals generated by the pulse generating circuits in the signal generating circuit 110 may be the same or different from the number of pulse signals generated by the pulse generating circuits in the signal generating circuit 130. In addition, the pulse signal generated by the pulse generating circuit in the signal generating circuit 110 may be the same or different from the pulse signal generated by the pulse generating circuit in the signal generating circuit 130. The pulse generation circuit 240 will be described later in fig. 3A and 3B.

Fig. 2B is a schematic diagram of another embodiment of the signal generating circuit of the present invention. FIG. 2B is similar to FIG. 2A, except that the signal generating circuit 200B of FIG. 2B further includes an inverter 250. Inverter 250 is coupled between power supply terminals PW1 and PW2. The input terminal of the inverter 250 is coupled to the drain of the P-type transistor 211 for receiving the output signal OUT, and the output terminal thereof is for generating the output signal OUTB. In one possible embodiment, the output signal OUTB may be the output signal OUT1 or OUT2 in fig. 1B.

In this embodiment, the inverter 250 includes a P-type transistor 251 and an N-type transistor 252. The source of the P-type transistor 251 is coupled to the power source PW1, the gate thereof is coupled to the drain of the P-type transistor 211, and the drain thereof provides the output signal OUTB. The gate of the N-type transistor 252 is coupled to the drain of the P-type transistor 211, the drain thereof is coupled to the drain of the P-type transistor 251, and the source thereof is coupled to the power source PW2.

Fig. 3A is a schematic diagram of a pulse generating circuit according to one embodiment of the present invention. As shown, the pulse generating circuit 300A includes a delay circuit 310 and a logic circuit 320. The delay circuit 310 and the logic circuit 320 are coupled between the power supply terminals PW1 and PW2, respectively, for taking the voltages received by the power supply terminals PW1 and PW2 as the own operation voltages.

The delay circuit 310 delays the voltage of the power source PW1 to generate a delay signal VD. The logic circuit 320 is based on the level V of the power source PW1 _PW1 And the delay signal VD generates a pulse signal osjn. In the present embodiment, when the level V of the power source PW1 is the same as the level V _PW1 And when the delay signal VD is at a high level, the pulse signal osjn is at a low level. When the level V of the power source PW1 is _PW1 And when one of the delay signals VD is at a low level, the pulse signal osjn is at a high level.

In one possible embodiment, the logic circuit 320 is a NAND gate 321. An input of the NAND gate 321 receives the level V of the power source PW1 _PW1 . The other input of the nand gate 321 receives the delay signal VD. The output of the nand gate 321 provides a pulse signal osjv. In other embodiments, logic 320 is other circuit architectures.

Taking fig. 2A as an example, it is assumed that the

control elements

221 and 222 of fig. 2A are both N-type transistors and the control element 223 is a P-type transistor. In this example, the pulse generating circuit 300A provides the pulse signal OS_N to the gates of the control elements 221-223. In a ready mode, the pulse signal OS_N is high to turn on the

control devices

221 and 222 and to turn off the control device 223. Thus, paths PA1 and PA2 are conductive, and path PA3 is non-conductive. At this time, the signal generating circuit 200A generates an output signal OUT from the input signal IN. In a not ready mode, the pulse signal OS_N is low to turn off the

control devices

221 and 222 and turn on the control device 223. Thus, paths PA1 and PA2 are non-conductive, and path PA3 is conductive. At this time, the signal generating circuit 200A sets the output signal OUT equal to a predetermined level, so as to not turn on the switch 121 in the core circuit 120, thereby avoiding the core circuit 120 from malfunction and preventing the esd current from entering the core circuit 120. In other embodiments, when the

control devices

221 and 222 are P-type transistors and the control device 223 is an N-type transistor, the pulse generating circuit 240 only needs to generate a single pulse signal to control the control devices 221 to 223 simultaneously.

Fig. 3B is a schematic diagram of a pulse generating circuit according to another embodiment of the present invention. FIG. 3B is similar to FIG. 3A, except that the pulse generating circuit 300B of FIG. 3B further includes an inverter 330. The inverter 330 inverts the pulse signal os_n to generate the pulse signal os_nb. Taking fig. 2A as an example, in an idle mode, the pulse signal osn is at a high level, and the pulse signal osnb is at a low level. Thus, paths PA1 and PA2 are non-conductive, and path PA3 is conductive. In this mode, the signal generating circuit 200A sets the level of the output signal OUT equal to a predetermined value. In a ready mode, the pulse signal osn is at a low level, and the pulse signal osnb is at a high level. Thus, paths PA1 and PA2 are conductive, and path PA3 is non-conductive. IN this mode, the signal generating circuit 200A generates the output signal OUT according to the input signal IN.

Fig. 4 is a schematic diagram of a delay circuit according to one embodiment of the present invention. As shown, the delay circuit 400 includes

inverters

410, 430 and

capacitors

420, 440. The present invention does not limit the number of inverters. In one possible embodiment, delay circuit 400 has an even number of inverters.

In the present embodiment, the inverter 410 is coupled between the power sources PW1 and PW2, and has an input 411 and an output 412. The input terminal 411 is coupled to the power source terminal PW1. In one possible embodiment, inverter 410 includes a P-type transistor 413 and an N-type transistor 414. The gate of the P-type transistor 413 is coupled to the input terminal 411, the source thereof is coupled to the power source PW1, and the drain thereof is coupled to the output terminal 412. The gate of the N-type transistor 414 is coupled to the input terminal 411, the source thereof is coupled to the power source PW2, and the drain thereof is coupled to the output terminal 412.

The capacitor 420 is coupled between the power source PW1 and the output 412. In this embodiment, the capacitor 420 is a P-type transistor 421. The gate of the P-type transistor 421 is coupled to the output terminal 421, and the drain and source thereof are coupled to the power source PW1.

The inverter 430 is coupled between the power sources PW1 and PW2, and has an input end 431 and an output end 432. The input terminal 431 is coupled to the output terminal 412. The output 432 is used for providing the delay signal VD. In one possible embodiment, inverter 430 includes a P-type transistor 433 and an N-type transistor 434. The gate of the P-type transistor 433 is coupled to the input terminal 431, the source thereof is coupled to the power source PW1, and the drain thereof is coupled to the output terminal 432. The gate of the N-type transistor 434 is coupled to the input terminal 431, the source thereof is coupled to the power source PW2, and the drain thereof is coupled to the output terminal 432.

The capacitor 440 is coupled between the power source PW2 and the output 432. In this embodiment, the capacitor 440 is an N-type transistor 441. The gate of the N-type transistor 441 is coupled to the output terminal 432, and the drain and source thereof are coupled to the power source PW2.

Fig. 5 is a schematic diagram of another embodiment of the delay circuit of the present invention. As shown, the delay circuit 500 includes at

least inverters

510 and 520. The inverter 510 is coupled between the power sources PW1 and PW2, and has an input terminal 511 and an output terminal 512. The input terminal 511 is coupled to the power source terminal PW1. In one possible embodiment, the inverter 510 includes a P-type transistor 513 and an N-type transistor 514. The gate of the P-type transistor 513 is coupled to the input terminal 511, the source is coupled to the power source PW1, and the drain is coupled to the output terminal 512. The gate of the N-type transistor 514 is coupled to the input terminal 511, the source is coupled to the power source PW2, and the drain is coupled to the output terminal 512.

The inverter 520 is coupled between the power sources PW1 and PW2, and has an input 521 and an output 522. The input 521 is coupled to the output 512. In one possible embodiment, the inverter 520 includes a P-type transistor 523 and an N-type transistor 524. The P-type transistor 523 has a gate coupled to the input terminal 521, a source coupled to the power source PW1, and a drain coupled to the output terminal 522. The gate of the N-type transistor 524 is coupled to the input terminal 521, the source thereof is coupled to the power source PW2, and the drain thereof is coupled to the output terminal 522. In one possible embodiment, when the delay circuit 500 has only the

inverters

510 and 520, the output 522 is used to provide the delay signal VD.

In other embodiments, the delay circuit 500 further has

inverters

530 and 540. The inverter 530 is coupled between the power sources PW1 and PW2, and has an input 531 and an output 532. Input 531 is coupled to output 522. In one possible embodiment, inverter 530 includes a P-type transistor 533 and an N-type transistor 534. The P-type transistor 533 has a gate coupled to the input 531, a source coupled to the power source PW1, and a drain coupled to the output 532. The gate of the N-type transistor 534 is coupled to the input terminal 531, the source is coupled to the power source PW2, and the drain is coupled to the output terminal 532.

The inverter 540 is coupled between the power sources PW1 and PW2, and has an input 541 and an output 542. Input 541 is coupled to output 532. In one possible embodiment, the inverter 540 includes a P-type transistor 543 and an N-type transistor 544. The P-type transistor 543 has a gate coupled to the input terminal 541, a source coupled to the power source PW1, and a drain coupled to the output terminal 542. The gate of the N-type transistor 544 is coupled to the input terminal 541, the source thereof is coupled to the power source PW2, and the drain thereof is coupled to the output terminal 542 for providing the delay signal VD. The present invention does not limit the number of inverters. In one possible embodiment, delay circuit 500 has an even number of inverters.

Unless otherwise defined, all terms (including technical and scientific terms) herein have the same meaning as commonly understood by one of ordinary skill in the art. Furthermore, unless explicitly indicated otherwise, the definition of a word in a general dictionary should be construed as meaning in its articles of related art and should not be interpreted as an ideal state or an excessively formal state.

Although the invention has been described with reference to preferred embodiments, it will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the spirit and scope of the invention. For example, the system, apparatus or method of embodiments of the present invention may be implemented in hardware, software or a combination of hardware and software. The protection scope of the present invention is therefore defined by the claims.

Claims

1. An anti-floating circuit is characterized in that in a first mode, a first output signal is generated according to a first input signal, and in a second mode, the first output signal is set to be equal to a first preset value, and the anti-floating circuit comprises:

a first pull-up circuit comprising:

a first P-type transistor, the source of which is coupled to a first power terminal and the drain of which provides the first output signal; and

a second P-type transistor, the source of which is coupled to the first power terminal, the drain of which is coupled to the gate of the first P-type transistor, and the gate of which is coupled to the drain of the first P-type transistor;

a first pull-down circuit comprising:

a first N-type transistor, the grid of which receives a first inversion signal, and the source of which is coupled with a second power supply end; and

a second N-type transistor, the grid of which receives the first input signal and the source of which is coupled with the second power supply end; and

a first control circuit coupled between the first pull-up circuit and the first pull-down circuit, and comprising:

a first control element coupled between the first P-type transistor and the first N-type transistor;

a second control element coupled between the second P-type transistor and the second N-type transistor;

a third control element coupled between the first P-type transistor and the second power supply terminal;

in the first mode, the first control element turns on a first path between the first P-type transistor and the first N-type transistor and the second control element turns on a second path between the second P-type transistor and the second N-type transistor, and the third control element turns off a third path between the second P-type transistor and the second power supply terminal;

in the second mode, the first control element does not conduct the first path and the second control element does not conduct the second path, and the third control element conducts the third path.

2. The anti-floating circuit of claim 1, wherein in the first mode, the first output signal is equal to a second level when the first input signal has a first level, and the first output signal is equal to a fourth level when the first input signal has a third level, the first level being lower than the second level, the third level being equal to the fourth level.

3. The anti-floating circuit of claim 1, wherein in the first mode, the first output signal is equal to a second level when the first input signal has a first level, the first output signal is equal to a fourth level when the first input signal has a third level, the first level is lower than the fourth level, and the second level is equal to the third level.

4. The anti-floating circuit of claim 1, wherein the first input signal is opposite to the first inverted signal.

5. The anti-floating circuit of claim 1, wherein in the first mode, the first control element turns on the first path according to a first pulse signal, the second control element turns on the second path according to the first pulse signal, and the third control element turns off the third path according to a second pulse signal;

in the second mode, the first control element does not conduct the first path according to the first pulse signal, the second control element does not conduct the second path according to the first pulse signal, and the third control element conducts the third path according to the second pulse signal.

6. The anti-floating circuit of claim 5, wherein the first control element, the second control element and the third control element are a third N-type transistor, a fourth N-type transistor and a fifth N-type transistor, respectively.

7. The anti-floating circuit of claim 6, wherein a drain of the third N-type transistor is coupled to a drain of the first P-type transistor, a source of the third N-type transistor is coupled to a drain of the first N-type transistor, and a gate of the third N-type transistor receives the first pulse signal;

the drain electrode of the fourth N-type transistor is coupled with the drain electrode of the second P-type transistor, the source electrode of the fourth N-type transistor is coupled with the drain electrode of the second N-type transistor, and the grid electrode of the fourth N-type transistor receives the first pulse signal;

the drain electrode of the fifth N-type transistor is coupled to the gate electrode of the first P-type transistor, the source electrode of the fifth N-type transistor is coupled to the second power supply end, and the gate electrode of the fifth N-type transistor receives the second pulse signal.

8. The anti-floating circuit of claim 5, further comprising:

and the pulse generating circuit is used for generating the first pulse signal and the second pulse signal, wherein the first pulse signal is opposite to the second pulse signal.

9. The anti-floating circuit of claim 8, wherein the pulse generating circuit comprises:

a delay circuit coupled to the first power terminal for generating a delay signal; and

and a logic circuit for generating the second pulse signal according to the level of the first power supply terminal and the delay signal.

10. The anti-floating circuit of claim 9, wherein the delay circuit comprises:

the first inverter is coupled between the first power end and the second power end and is provided with a first input end and a first output end, wherein the first input end is coupled with the first power end;

a first capacitor coupled between the first power terminal and the first output terminal;

the second inverter is coupled between the first power end and the second power end and is provided with a second input end and a second output end, wherein the second input end is coupled with the first output end, and the second output end is coupled with the logic circuit; and

and a second capacitor coupled between the second output terminal and the second power terminal.

11. The anti-floating circuit of claim 10, wherein the first capacitor is a third P-type transistor and the second capacitor is a third N-type transistor.

12. The anti-floating circuit of claim 11, wherein a gate of the third P-type transistor is coupled to the first output terminal, a drain and a source of the third P-type transistor are coupled to the first power terminal, a gate of the third N-type transistor is coupled to the second output terminal, and a drain and a source of the third N-type transistor are coupled to the second power terminal.

13. The anti-floating circuit of claim 9, wherein the delay circuit comprises:

the first inverter is coupled between the first power end and the second power end and is provided with a first input end and a first output end, wherein the first input end is coupled with the first power end; and

the second inverter is coupled between the first power end and the second power end, and is provided with a second input end and a second output end, wherein the second input end is coupled with the first output end, and the second output end is coupled with the logic circuit.

14. The anti-floating circuit of claim 9, wherein the logic circuit is a nand gate.

15. The anti-floating circuit of claim 9, wherein the pulse generating circuit further comprises:

an inverting circuit inverts the second pulse signal to generate the first pulse signal.

16. The anti-floating circuit of claim 1, further comprising:

a core circuit coupled between the first power terminal and the second power terminal; and

and a switch for providing the voltage at the first power supply terminal or the second power supply terminal to the core circuit according to the first output signal.

17. The anti-floating circuit of claim 1, further comprising:

an inverter for inverting the first output signal to generate a second output signal;

and a switch for providing the voltage at the first power supply terminal or the second power supply terminal to the core circuit according to the second output signal.

18. The anti-floating circuit of claim 1, further comprising:

a second pull-up circuit comprising:

a third P-type transistor having a source coupled to the first power terminal and a drain providing a second output signal; and

a fourth P-type transistor having a source coupled to the first power terminal, a drain coupled to the gate of the third P-type transistor, and a gate coupled to the drain of the third P-type transistor;

a second pull-down circuit comprising:

a third N-type transistor, the grid of which receives a second inverted signal, and the source of which is coupled with the second power supply end; and

a fourth N-type transistor having a gate receiving a second input signal and a source coupled to the second power supply terminal; and

a second control circuit coupled between the second pull-up circuit and the second pull-down circuit;

in the first mode, the second control circuit turns on a fourth path between the third P-type transistor and the third N-type transistor and a fifth path between the fourth P-type transistor and the fourth N-type transistor, and turns off a sixth path between the fourth P-type transistor and the second power supply terminal;

in the second mode, the second control circuit does not conduct the fourth path and the fifth path, and conducts the sixth path.

19. The anti-floating circuit of claim 18, wherein the second control circuit comprises:

a first control element coupled between the third P-type transistor and the third N-type transistor;

a second control element coupled between the fourth P-type transistor and the fourth N-type transistor; and

a third control element coupled between the third P-type transistor and the second power supply terminal;

in the first mode, the first control element conducts the fourth path according to a third pulse signal, the second control element conducts the fifth path according to the third pulse signal, and the third control element does not conduct the sixth path according to a fourth pulse signal;

in the second mode, the first control element does not conduct the fourth path according to the third pulse signal, the second control element does not conduct the fifth path according to the third pulse signal, and the third control element conducts the sixth path according to the fourth pulse signal.

20. The anti-floating circuit of claim 19, further comprising:

a core circuit coupled between the first power terminal and the second power terminal;

a first switch for providing the voltage on the first power supply terminal to the core circuit according to the first output signal; and

and a second switch for providing the voltage on the second power supply terminal to the core circuit according to the second output signal.