CN110417402A - Anti- suspension joint circuit - Google Patents
Anti- suspension joint circuit Download PDFInfo
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- CN110417402A CN110417402A CN201810389713.XA CN201810389713A CN110417402A CN 110417402 A CN110417402 A CN 110417402A CN 201810389713 A CN201810389713 A CN 201810389713A CN 110417402 A CN110417402 A CN 110417402A
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
- G11C7/1051—Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
- G11C7/1078—Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/0175—Coupling arrangements; Interface arrangements
- H03K19/0185—Coupling arrangements; Interface arrangements using field effect transistors only
- H03K19/018507—Interface arrangements
- H03K19/018521—Interface arrangements of complementary type, e.g. CMOS
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Abstract
The present invention provides a kind of anti-suspension joint circuit, which includes a pull-up circuit, a pull-down circuit and a control circuit.Pull-up circuit includes one first P-type transistor and one second P-type transistor, and couples one first power end.Pull-down circuit includes one first N-type transistor and one second N-type transistor, and couples a second source end.There is a first path between first P-type transistor and the first N-type transistor.There is one second path between second P-type transistor and the second N-type transistor.There is a third path between first P-type transistor and second source end.In the flrst mode, control circuit is connected first and second path and is not turned on third path.Under the second mode, control circuit is not turned on first and second path, and third path is connected.Anti- suspension joint circuit provided by the invention makes when input signal is not correct signal, not will cause integrated circuit malfunction.
Description
Technical field
The invention relates to a kind of anti-suspension joint circuit, in particular to a kind of with pull-up circuit and pull-down circuit
Anti- suspension joint circuit.
Background technique
With the development of science and technology the size of integrated circuit is more and more small.In general, each integrated circuit is according at least one
Input signal and act.However, when the input signal is not correct signal, it is easy to integrated circuit be caused to malfunction.
Summary of the invention
The present invention provides a kind of anti-suspension joint circuit, under a first mode, generates one first according to one first input signal
Output signal sets first output signal equal to one first preset value under a second mode, and including one first pull-up electricity
Road, one first pull-down circuit and a first control circuit.First pull-up circuit includes one first P-type transistor and one second
P-type transistor.The source electrode of first P-type transistor couples one first power end.The drain electrode of first P-type transistor provides the first output
Signal.The source electrode of second P-type transistor couples the first power end.Drain electrode the first P-type transistor of coupling of second P-type transistor
Grid.The grid of second P-type transistor couples the drain electrode of the first P-type transistor.First pull-down circuit includes one first N-type crystal
Pipe and one second N-type transistor.The grid of first N-type transistor receives one first inversion signal.The source of first N-type transistor
Pole couples a second source end.The grid of second N-type transistor receives input signal.The source electrode coupling the of second N-type transistor
Two power ends.First control circuit is coupled between the first pull-up circuit and the first pull-down circuit.In the flrst mode, the first control
A first path and the second P-type transistor and second between the first P-type transistor and the first N-type transistor is connected in circuit processed
One second path between N-type transistor, and the third road being not turned between the first P-type transistor and second source end
Diameter.Under the second mode, first control circuit is not turned on first path and the second path, and third path is connected.The present invention mentions
The anti-suspension joint circuit supplied makes when input signal is not correct signal, not will cause integrated circuit malfunction.
Detailed description of the invention
Figure 1A is the schematic diagram of anti-suspension joint circuit of the invention.
Figure 1B is another schematic diagram of anti-suspension joint circuit of the invention.
Fig. 2A is a possible embodiment of signal generating circuit of the invention.
Fig. 2 B is another possible embodiment of signal generating circuit of the invention.
Fig. 3 A is a possible embodiment of pulse-generating circuit of the invention.
Fig. 3 B is another possible embodiment of pulse-generating circuit of the invention.
Fig. 4 is a possible embodiment of delay circuit of the invention.
Fig. 5 is another possible embodiment of delay circuit of the invention.
Drawing reference numeral
100A, 100B: anti-suspension joint circuit；
110,130,200A, 200B: signal generating circuit；
120: core circuit；
PW1, PW2: power end；
IN1, IN2, IN: input signal；
OUT1, OUT2, OUT, OUTB: output signal；
121,123: switch；
122: load；
210: pull-up circuit；
220: control circuit；
230: pull-down circuit；
211,212,251,331,413,421,433,513,523,533,543:P transistor npn npn；
231,232,224~226,252,332,414,434,441,514,524,534,544:N transistor npn npn；
221~223: control element；
240,300A, 300B: pulse-generating circuit；
INB: inversion signal；
PA1~PA3: path；
OS_N, OS_NB: pulse signal；
250,330,410,430,510,520,530,540: phase inverter；
310,400,500: delay circuit；
320: logic circuit；
VPW1: level；
VD: postpones signal；
321: NAND gate；
420,440: capacitor；
411,431,511,521,531,541: input terminal；
412,432,512,522,532,542: output end.
Specific embodiment
For objects, features and advantages of the present invention can be clearer and more comprehensible, embodiment is cited below particularly out, and cooperate institute's attached drawing
Formula is described in detail.Description of the invention provides different embodiments to illustrate that the technology of different embodiments of the present invention is special
Sign.Wherein, the configuration of each element in embodiment is not intended to limit the invention for purposes of discussion.In addition, scheming in embodiment
The part of formula label repeats, and is the relevance being not meant as between different embodiments to simplify the explanation.
Figure 1A is the schematic diagram of anti-suspension joint circuit of the invention.As shown, anti-suspension joint circuit 100A is produced including a signal
Raw circuit 110 and a core circuit 120.Signal generating circuit 110 is coupled between power end PW1 and PW2, and it is defeated to generate one
Signal OUT1 out.In a possible embodiment, signal generating circuit 110 is a level converter (level shifter).Herein
In example, signal generating circuit 110 converts the level of an input signal IN1, and using the result after conversion as output signal OUT1.
When input signal IN1 is first level, output signal OUT1 is one second level.When input signal IN1 is
When one third level, output signal OUT1 is one the 4th level.In a possible embodiment, the second level is higher than the first level.
For example, the first level is about 3.3V, and the second level is about 6V~7V.In addition, third level is equally likely to the 4th level,
For 0V.
In another possible embodiment, the first level is greater than the second level, and the 4th level is greater than third level.In this example
In, the 4th level is likely larger than the first level.For example, the first level is about 3.3V, and the 4th level is about 6V~7V.Separately
Outside, second standard is equally likely to third level, is 0V.
Core circuit 120 is coupled between power end PW1 and PW2, and receives output signal OUT1.It may embodiment one
In, core circuit 120 is a non-volatility memorizer (non-volatile memory；NVM), but not to limit this hair
It is bright.In other embodiments, core circuit 120 may be the integrated circuit of other types.In general, core circuit 120 has
There are many element, but for simplicity, Figure 1A only display portion element related to the present invention, and core is indicated with load 122
Other elements in circuit 120.
As shown, core circuit 120 includes at least a switch 121.In the present embodiment, switch 121 is coupled to power supply
It holds between PW1 and load 122.Switch 121 decides whether that the power supply for transmitting power end PW1 gives load according to output signal OUT1
122.For example, when output signal OUT1 is first state (such as low level or high levels), switch 121 transmits power end
The power supply of PW1 gives load 122.In this instance, when output signal OUT1 is the second state (such as high levels or low level), switch
121 power supplys for not transmitting power end PW1 give load 122.In a possible embodiment, switch 121 is a P-type transistor, but simultaneously
It is non-to limit the present invention.In other embodiments, switch 121 is a N-type transistor.In other embodiments, switch 121 can
It can be coupled between power end PW2 and load 122, and decide whether the power supply of transmission power end PW2 according to output signal OUT1
Give load 122.
Due to signal generating circuit 110 be according to input signal IN1 generate output signal OUT1, when input signal IN1 still
When not ready, the level of output signal OUT1 is likely to be at quick condition (floating).Therefore, switch 121 may be because of mistake
Output signal OUT1 and be connected, cause core circuit 120 malfunction.Furthermore while switch 121 is connected, if one is quiet
Discharge of electricity (electrostatic discharge；ESD when) event is occurred between power end PW1 and PW2, a static discharge
Electric current will flow into core circuit 120 from switch 121, thus burn core circuit 120.
Therefore, under a non-ready mode, since input signal IN1 is not yet ready, therefore signal generating circuit 110 set it is defeated
The level of signal OUT1 is equal to a preset value out, to be not turned on switch 121.Therefore, core circuit 120 will not malfunction.Again
Person, in such a mode, if an electrostatic discharge event is occurred between power end PW1 and PW2, since switch 121 is not turned on,
Therefore static discharge current may not flow into core circuit 120.
Under a ready mode, since input signal IN1 is ready, therefore signal generating circuit 110 is according to input signal IN1
Generate output signal OUT1.In such a mode, due to power end PW1 and PW2 have received corresponding operation voltage (such as 6V and
0V), therefore signal generating circuit 110 sets voltage of the high levels equal to power end PW1 of output signal OUT1, and sets output letter
The low level of number OUT1 is equal to the voltage of power end PW2.
Figure 1B is another possible embodiment of anti-suspension joint circuit of the invention.Figure 1B similar diagram 1A, the difference is that figure
The anti-suspension joint circuit 100B of 1B further includes a signal generating circuit 130.In the present embodiment, signal generating circuit 130 is also coupled to
An output signal OUT2 is generated between power end PW1 and PW2, and according to an input signal IN2.In a possible embodiment,
Signal generating circuit 130 is a level converter.In this instance, the level of 130 converted input signal IN2 of signal generating circuit,
And using the result after conversion as output signal OUT2.In other embodiments, input signal IN1 may be same or different from defeated
Enter signal IN2.Since the movement of signal generating circuit 130 is identical as signal generating circuit 110, so it will not be repeated.
In the present embodiment, core circuit 120 further includes a switch 123.123 series load 122 of switch, and according to output
Signal OUT2 decides whether that the power supply for transmitting power end PW2 gives load 122.For example, when output signal OUT2 is the first shape
When state (such as low level or high levels), the power supply that switch 123 does not transmit power end PW2 gives load 122.In this instance, work as output
When signal OUT2 is the second state (such as high levels or low level), the power supply that switch 123 transmits power end PW2 gives load 122.In
In one possible embodiment, switch 123 is a N-type transistor, but is not intended to limit the invention.In other embodiments, it switchs
123 be a P-type transistor.
In some embodiments, switch 121 and 123 is the transistor for identical type, is such as P-type transistor or is
N-type transistor.In another embodiment, switch 121 and 123 is different types of transistor.For example, when switch 121 is
One P-type transistor, switch 123 are a N-type transistor；When switch 121 is a N-type transistor, switch 123 is a P-type transistor.
In other embodiments, when switch 121 is connected, switch 123 is also switched on.When switch 121 is not turned on, switch 123 is not also led
It is logical.
Under a non-ready mode, since input signal IN1 and IN2 not yet reach target level, therefore signal generating circuit 110
And 130 be set separately output signal OUT1 and OUT2 level be equal to one first preset value and one second preset value, to not
Switch 121 and 123 is connected.Since switch 121 and 123 is not turned on, therefore it can avoid core circuit 120 and malfunction.Furthermore due to opening
121 and 123 are closed to be not turned on, therefore when an electrostatic discharge event occurs between power end PW1 and PW2, electrostatic induced current will not
Into core circuit 120.
When input signal IN1 and IN2 respectively up to a first object level and one second target level when, signal generates electricity
Road 110 and 130 enters a ready mode.In such a mode, signal generating circuit 110 generates output letter according to input signal IN1
Number OUT1, to be connected or be not turned on switch 121.In addition, signal generating circuit 130 generates output letter according to input signal IN2
Number OUT2, to be connected or be not turned on switch 123.Since signal generating circuit 110 and 130 generates correct output signal OUT1
And OUT2, therefore can avoid core circuit 120 and malfunction.
Fig. 2A is a possible embodiment of signal generating circuit of the invention.As shown, signal generating circuit 200A packet
Include a pull-up circuit 210, a control circuit 220 and pull-down circuit 230.Pull-up circuit 210 include P-type transistor 211 and
212.The source electrode of P-type transistor 211 couples power end PW1, and drain electrode provides output signal OUT.The source electrode of P-type transistor 212
Power end PW1, the grid and control circuit 220 of drain electrode coupling P-type transistor 211 are coupled, grid couples P-type transistor
211 drain electrode.In a possible embodiment, when signal generating circuit 200A is as the signal generating circuit 110 or 130 in Figure 1B
When, then output signal OUT is as output signal OUT1 or OUT2.
Pull-down circuit 230 includes N-type transistor 231 and 232.The grid of N-type transistor 231 receives an inversion signal INB,
Its source electrode couples power end PW2, drain electrode coupling control circuit 220.The grid of N-type transistor 232 receives input signal IN,
Source electrode couples power end PW2, drain electrode coupling control circuit 220.In the present embodiment, inversion signal INB is for input signal
The inversion signal of IN.
In a possible embodiment, when signal generating circuit 200A is as the signal generating circuit 110 or 130 in Figure 1B
When, then input signal IN is input signal IN1 or IN2.In other embodiments, signal generating circuit 200A has more a reverse phase
Device (not shown), rp input signal IN, to generate inversion signal INB.In some embodiments, which is set to
Except signal generating circuit 200A.
220 coupling of control circuit is between pull-up circuit 210 and pull-down circuit 230.(the i.e. input signal under a ready mode
IN is ready), a path PA1 and P-type crystal between P-type transistor 211 and N-type transistor 231 is connected in control circuit 220
A path PA2 between pipe 212 and N-type transistor 232, and one be not turned between P-type transistor 211 and power end PW2
Path P A3.In such a mode, signal generating circuit 200A generates output signal OUT according to input signal IN.
When input signal IN does not reach target level or input signal IN not yet entering signal generation circuit 200A, signal
Generation circuit 200A enters a non-ready mode.Under non-ready mode, control circuit 220 is not turned on path P A1 and PA2, and
Guiding path PA3.In such a mode, the level that control circuit 220 sets output signal OUT is equal to a preset value, not lead
Switch (the 121 of such as Figure 1A) in logical core circuit, avoids core circuit from malfunctioning.
In the present embodiment, control circuit 220 includes control element 221~223.Control element 221 is coupled to P-type crystal
Between the drain electrode of pipe 211 and the drain electrode of N-type transistor 231.Control element 221 decides whether to be connected according to pulse signal OS_NB
Path P A1.Under a ready mode (i.e. input signal IN is ready), pulse signal OS_NB has the first level.Therefore, it controls
221 guiding path PA1 of element.Under a non-ready mode (i.e. input signal IN is not ready), pulse signal OS_NB has second
Level.Therefore, control element 221 is not turned on path P A1.
The present invention does not limit the type of control element 221.In the present embodiment, control element 221 is for a N-type crystal
Pipe 224.The grid return pulse signal OS_NB of N-type transistor 224, the drain electrode of drain electrode coupling P-type transistor 211, source electrode
Couple the drain electrode of N-type transistor 231.Under ready mode, pulse signal OS_NB is high levels, and N-type transistor 224 is connected.Cause
This, path P A1 is switched on.Under non-ready mode, pulse signal OS_NB is low level, and N-type transistor 224 is not turned on.Cause
This, path P A1 is not turned on.In other embodiments, control element 221 is a P-type transistor.
Control element 222 is coupled between the drain electrode of P-type transistor 212 and the drain electrode of N-type transistor 232.Control element
222 decide whether guiding path PA2 according to pulse signal OS_NB.(such as input signal IN has reached target position under a ready mode
It is quasi-), pulse signal OS_NB is the first level.Therefore, 222 guiding path PA2 of control element.It is (i.e. defeated under a non-ready mode
Enter signal IN and not yet reach target level), pulse signal OS_NB is the second level.Therefore, control element 222 is not turned on path
PA2。
The present invention does not limit the type of control element 222.In the present embodiment, control element 222 is a N-type transistor
225.The grid return pulse signal OS_NB of N-type transistor 225, the drain electrode of drain electrode coupling P-type transistor 212, source electrode coupling
Connect the drain electrode of N-type transistor 232.Under ready mode, pulse signal OS_NB is Gao Ping, and N-type transistor 225 is connected.Therefore,
Path P A2 is switched on.Under non-ready mode, pulse signal OS_NB is low level, and N-type transistor 225 is not turned on.Therefore, road
Diameter PA2 is not turned on.In other embodiments, control element 222 is a P-type transistor.
Control element 223 is coupled between the grid of P-type transistor 211 and power end PW2.Control element 223 is according to arteries and veins
Signal OS_N is rushed to decide whether that the path P A3 between P-type transistor 211 and power end PW2 is connected.Under a non-ready mode,
Pulse signal OS_N is a third level.Therefore, 223 guiding path PA3 of control element.Under a ready mode, pulse signal
OS_N is one the 4th level.Therefore, control element 223 is not turned on path P A3.
The present invention does not limit the type of control element 223.In the present embodiment, control element 223 is a N-type transistor
226.The grid return pulse signal OS_N of N-type transistor 226, the grid of drain electrode coupling P-type transistor 211, source electrode coupling
Meet power end PW2.Under ready mode, pulse signal OS_N is low level, and N-type transistor 226 is not turned on.Therefore, path P A3
It is not switched on.Under non-ready mode, pulse signal OS_N is high levels Gao Ping, and N-type transistor 226 is switched on.Therefore, path
PA3 conducting.In other embodiments, control element 223 is a P-type transistor.
In a possible embodiment, pulse signal OS_N reverse phase is not to limit this hair in pulse signal OS_NB
It is bright.When control element 221 and 222 is N-type transistor and control element 223 is a P-type transistor or control element
When 221 and 222 be P-type transistor and control element 223 is a N-type transistor, pulse-generating circuit 240 only needs to generate single
Pulse signal can control control element 221~223.
In the present embodiment, pulse signal OS_NB and OS_N is as produced by a pulse-generating circuit 240.Pulse generates
Circuit 240 is coupled between power end PW1 and PW2.Pulse-generating circuit 240 generates arteries and veins according to the level of power end PW1 and PW2
Rush signal OS_NB and OS_N.In some embodiments, there may be different pulse signals for different pulse-generating circuits.
By taking Figure 1B as an example, pulse signal quantity caused by the pulse-generating circuit in signal generating circuit 110 may phase
Together or different from pulse signal quantity caused by the pulse-generating circuit in signal generating circuit 130.In addition, signal generates electricity
Pulse signal caused by pulse-generating circuit in road 110 may be same or different from the pulse in signal generating circuit 130
Pulse signal caused by generation circuit.Later pulse-generating circuit 240 will be introduced in Fig. 3 A and Fig. 3 B.
Fig. 2 B is another possible embodiment of signal generating circuit of the invention.Fig. 2 B similar diagram 2A, the difference is that,
The signal generating circuit 200B of Fig. 2 B further includes a phase inverter 250.Phase inverter 250 is coupled between power end PW1 and PW2.Instead
The drain electrode of the input terminal coupling P-type transistor 211 of phase device 250, to receive output signal OUT, output end is defeated to generate
Signal OUTB out.In a possible embodiment, output signal OUTB can be used as output signal OUT1 or OUT2 in Figure 1B.
In the present embodiment, phase inverter 250 includes a P-type transistor 251 and a N-type transistor 252.P-type transistor
251 source electrode couples power end PW1, and grid couples the drain electrode of P-type transistor 211, and drain electrode provides output signal OUTB.N
The drain electrode of the grid coupling P-type transistor 211 of transistor npn npn 252, the drain electrode of drain electrode coupling P-type transistor 251, source electrode coupling
Meet power end PW2.
Fig. 3 A is a possible embodiment of pulse-generating circuit of the invention.As shown, pulse-generating circuit 300A packet
Include a delay circuit 310 and a logic circuit 320.Delay circuit 310 and logic circuit 320 are respectively coupled to power end PW1
Between PW2, to using voltage received by power end PW1 and PW2 as operation voltage itself.
Delay circuit 310 postpones the voltage of power end PW1, to generate a postpones signal VD.Logic circuit 320 is according to electricity
The level V of source PW1PW1And postpones signal VD generates pulse signal OS_N.In the present embodiment, when the level of power end PW1
VPW1And postpones signal VD, when being high levels, pulse signal OS_N is low level.As the level V of power end PW1PW1And prolong
When one of slow signal VD is low level, pulse signal OS_N is high levels.
In a possible embodiment, logic circuit 320 is a NAND gate (NAND) 321.One input termination of NAND gate 321
Receive the level V of power end PW1PW1.Another input terminal of NAND gate 321 receives postpones signal VD.The output end of NAND gate 321 mentions
For pulse signal OS_N.In other embodiments, logic circuit 320 is other circuit frameworks.
By taking Fig. 2A as an example, it is assumed that the control element 221 and 222 of Fig. 2A is N-type transistor and control element 223 is P
Transistor npn npn.In this instance, pulse-generating circuit 300A provides the pulse signal OS_N grid for giving control element 221~223.In
Under one ready mode, pulse signal OS_N is high levels, control element 221 and 222 is connected, and is not turned on control element
223.Therefore, path P A1 and PA2 conducting, and path P A3 is not turned on.At this point, signal generating circuit 200A is according to input signal
IN generates output signal OUT.Under a non-ready mode, pulse signal OS_N is low level, to be not turned on control element 221
And 222, and control element 223 is connected.Therefore, path P A1 and PA2 are not turned on, and path P A3 is connected.At this point, signal generates
Circuit 200A sets output signal OUT and is equal to a default level, to the switch 121 being not turned in core circuit 120, to avoid
Core circuit 120 malfunctions, and can avoid static discharge current and enter core circuit 120.In other embodiments, when control member
When part 221 and 222 is P-type transistor and control element 223 is N-type transistor, pulse-generating circuit 240 need to generate list
One pulse signal can control control element 221~223 simultaneously.
Fig. 3 B is another embodiment of pulse-generating circuit of the invention.Fig. 3 B similar diagram 3A, the difference is that, Fig. 3 B
Pulse-generating circuit 300B further include a phase inverter 330.330 rp pulse signal OS_N of phase inverter, to generate pulse letter
Number OS_NB.By taking this case Fig. 2A as an example, under a non-ready mode, pulse signal OS_N is high levels, and pulse signal OS_
NB is low level.Therefore, path P A1 and PA2 are not turned on, and path P A3 is connected.In such a mode, signal generating circuit
The level that 200A sets output signal OUT is equal to a preset value.Under a ready mode, pulse signal OS_N is low level, and
And pulse signal OS_NB is high levels.Therefore, path P A1 and PA2 conducting, and path P A3 is not turned on.In such a mode, believe
Number generation circuit 200A generates output signal OUT according to input signal IN.
Fig. 4 is a possible embodiment of delay circuit of the invention.As shown, delay circuit 400 includes phase inverter
410,430 and capacitor 420,440.The present invention does not limit the quantity of phase inverter.In a possible embodiment, delay circuit
400 have even number of inverters.
In the present embodiment, phase inverter 410 is coupled between power end PW1 and PW2, and have an input terminal 411 and
One output end 412.Input terminal 411 couples power end PW1.In a possible embodiment, phase inverter 410 includes a P-type transistor
413 and a N-type transistor 414.The grid of P-type transistor 413 couples input terminal 411, and source electrode couples power end PW1,
Drain electrode coupling output end 412.The grid of N-type transistor 414 couples input terminal 411, and source electrode couples power end PW2, drain electrode
Couple output end 412.
Capacitor 420 is coupled between power end PW1 and output end 412.In the present embodiment, capacitor 420 is a P-type crystal
Pipe 421.The grid of P-type transistor 421 couples output end 421, and drain electrode couples power end PW1 with source electrode.
Phase inverter 430 is coupled between power end PW1 and PW2, and has an input terminal 431 and an output end 432.It is defeated
Enter 431 coupling output end 412 of end.Output end 432 is to provide postpones signal VD.In a possible embodiment, phase inverter 430 is wrapped
Include a P-type transistor 433 and a N-type transistor 434.The grid of P-type transistor 433 couples input terminal 431, source electrode coupling
Power end PW1, drain electrode coupling output end 432.The grid of N-type transistor 434 couples input terminal 431, and source electrode couples power supply
Hold PW2, drain electrode coupling output end 432.
Capacitor 440 is coupled between power end PW2 and output end 432.In the present embodiment, capacitor 440 is a N-type crystal
Pipe 441.The grid of N-type transistor 441 couples output end 432, and drain electrode couples power end PW2 with source electrode.
Fig. 5 is another possible embodiment of delay circuit of the invention.As shown, delay circuit 500 includes at least instead
Phase device 510 and 520.Phase inverter 510 is coupled between power end PW1 and PW2, and has an input terminal 511 and an output end
512.Input terminal 511 couples power end PW1.In a possible embodiment, phase inverter 510 includes a P-type transistor 513 and one
N-type transistor 514.The grid of P-type transistor 513 couples input terminal 511, and source electrode couples power end PW1, and drain electrode coupling is defeated
Outlet 512.The grid of N-type transistor 514 couples input terminal 511, and source electrode couples power end PW2, drain electrode coupling output end
512。
Phase inverter 520 is coupled between power end PW1 and PW2, and has an input terminal 521 and an output end 522.It is defeated
Enter 521 coupling output end 512 of end.In a possible embodiment, phase inverter 520 includes that a P-type transistor 523 and a N-type are brilliant
Body pipe 524.The grid of P-type transistor 523 couples input terminal 521, and source electrode couples power end PW1, drain electrode coupling output end
522.The grid of N-type transistor 524 couples input terminal 521, and source electrode couples power end PW2, drain electrode coupling output end 522.
In a possible embodiment, when having phase inverter 510 and 520 for delay circuit 500, then output end 522 is to provide delay
Signal VD.
In other embodiments, delay circuit 500 has more phase inverter 530 and 540.Phase inverter 530 is coupled to power end
Between PW1 and PW2, and there is an input terminal 531 and an output end 532.Input terminal 531 couples output end 522.It may one
In embodiment, phase inverter 530 includes a P-type transistor 533 and a N-type transistor 534.The grid of P-type transistor 533 couples
Input terminal 531, source electrode couple power end PW1, drain electrode coupling output end 532.The grid of N-type transistor 534 couples input
End 531, source electrode couple power end PW2, drain electrode coupling output end 532.
Phase inverter 540 is coupled between power end PW1 and PW2, and has an input terminal 541 and an output end 542.It is defeated
Enter 541 coupling output end 532 of end.In a possible embodiment, phase inverter 540 includes that a P-type transistor 543 and a N-type are brilliant
Body pipe 544.The grid of P-type transistor 543 couples input terminal 541, and source electrode couples power end PW1, drain electrode coupling output end
542.The grid of N-type transistor 544 couples input terminal 541, and source electrode couples power end PW2, and drain electrode couples output end 542,
To provide postpones signal VD.The present invention does not limit the quantity of phase inverter.In a possible embodiment, delay circuit 500 has
There is even number of inverters.
Unless otherwise defined, all vocabulary (including technology and scientific terms) belong to the general of those skilled in the art herein
Understand.In addition, unless clear expression, definition of the vocabulary in general dictionary should be interpreted that in the article of technical field associated therewith
Meaning is consistent, and should not be construed as perfect condition or excessively formal voice.
Although the present invention has been disclosed as a preferred embodiment, however, it is not to limit the invention, any this field skill
Art personnel, without departing from the spirit and scope of the present invention, when can make some changes and embellishment.Citing comes, and the present invention is implemented
Example institute system, device or method can be realized with the combined physical embodiment of hardware, software or hardware and software.Cause
This protection scope of the present invention is subject to view as defined in claim.
Claims (20)
1. a kind of anti-suspension joint circuit, which is characterized in that under a first mode, it is defeated to generate one first according to one first input signal
Signal out sets first output signal equal to one first preset value, and include: under a second mode
One first pull-up circuit, comprising:
One first P-type transistor, source electrode couple one first power end, and drain electrode provides first output signal；And
One second P-type transistor, source electrode couple first power end, and drain electrode couples the grid of first P-type transistor,
Grid couples the drain electrode of first P-type transistor；
One first pull-down circuit, comprising:
One first N-type transistor, grid receive one first inversion signal, and source electrode couples a second source end；And
One second N-type transistor, grid receive first input signal, and source electrode couples the second source end；And
One first control circuit is coupled between first pull-up circuit and first pull-down circuit；
Wherein, in the first mode, the first control circuit be connected first P-type transistor and first N-type transistor it
Between a first path and second P-type transistor and second N-type transistor between one second path, and be not turned on
A third path between first P-type transistor and the second source end；
Wherein, in this second mode, which is not turned on the first path and second path, and be connected this
Three paths.
2. anti-suspension joint circuit as described in claim 1, which is characterized in that in the first mode, when first input signal
When with first level, which is equal to one second level, when first input signal has a third level
When, which is equal to one the 4th level, which is lower than second level, which is equal to the 4th
It is quasi-.
3. anti-suspension joint circuit as described in claim 1, which is characterized in that in the first mode, when first input signal
When with first level, which is equal to one second level, when first input signal has a third level
When, which is equal to one the 4th level, which is lower than the 4th level, which is equal to third position
It is quasi-.
4. anti-suspension joint circuit as described in claim 1, which is characterized in that first input signal is believed in contrast to first reverse phase
Number.
5. anti-suspension joint circuit as described in claim 1, which is characterized in that the first control circuit includes:
One first control element is coupled between first P-type transistor and first N-type transistor；
One second control element is coupled between second P-type transistor and second N-type transistor；
One third control element is coupled between first P-type transistor and the second source end；
Wherein, in the first mode, which is connected the first path according to one first pulse signal, this second
Second path is connected according to first pulse signal in control element, which does not lead according to one second pulse signal
Lead to the third path；
Wherein, in this second mode, which is not turned on the first path according to first pulse signal, this
Two control elements are not turned on second path according to first pulse signal, and the third control element is according to second pulse signal
The third path is connected.
6. anti-suspension joint circuit as claimed in claim 5, which is characterized in that first control element, the second control element and the
Three control elements are respectively a third N-type transistor, one the 4th N-type transistor and one the 5th N-type transistor.
7. anti-suspension joint circuit as claimed in claim 6, which is characterized in that the drain electrode of the third N-type transistor couples the first P
The drain electrode of transistor npn npn, the source electrode of the third N-type transistor couple the drain electrode of first N-type transistor, the third N-type transistor
Grid receive first pulse signal；
Wherein the drain electrode of the 4th N-type transistor couples the drain electrode of second P-type transistor, the source electrode of the 4th N-type transistor
The drain electrode of second N-type transistor is coupled, the grid of the 4th N-type transistor receives first pulse signal；
Wherein the drain electrode of the 5th N-type transistor couples the grid of first P-type transistor, the source electrode of the 5th N-type transistor
The second source end is coupled, the grid of the 5th N-type transistor receives second pulse signal.
8. anti-suspension joint circuit as claimed in claim 5, which is characterized in that further include:
One pulse-generating circuit, to generate first pulse signal and the second pulse signal, wherein first pulse signal is anti-
Mutually in second pulse signal.
9. anti-suspension joint circuit as claimed in claim 8, which is characterized in that the pulse-generating circuit includes:
One delay circuit couples first power end, to generate a postpones signal；And
One logic circuit generates second pulse signal according to the level of first power end and the postpones signal.
10. anti-suspension joint circuit as claimed in claim 9, which is characterized in that the delay circuit includes:
One first phase inverter is coupled between first power end and the second source end, and have a first input end and
One first output end, wherein the first input end couples first power end；
One first capacitor is coupled between first power end and first output end；
One second phase inverter is coupled between first power end and the second source end, and have one second input terminal and
One second output terminal, wherein second input terminal couples first output end, which couples the logic circuit；And
One second capacitor is coupled between the second output terminal and the second source end.
11. anti-suspension joint circuit as claimed in claim 10, which is characterized in that the first capacitor is a third P-type transistor, should
Second capacitor is a third N-type transistor.
12. anti-suspension joint circuit as claimed in claim 11, wherein the grid of the third P-type transistor couples first output
End, the drain electrode of the third P-type transistor and source electrode couple first power end, the grid of the third N-type transistor couple this
Two output ends, the drain electrode of the third N-type transistor and source electrode couple the second source end.
13. anti-suspension joint circuit as claimed in claim 9, which is characterized in that the delay circuit includes:
One first phase inverter is coupled between first power end and the second source end, and have a first input end and
One first output end, wherein the first input end couples first power end；And
One second phase inverter is coupled between first power end and the second source end, and have one second input terminal and
One second output terminal, wherein second input terminal couples first output end, which couples the logic circuit.
14. anti-suspension joint circuit as claimed in claim 9, which is characterized in that the logic circuit is a NAND gate.
15. anti-suspension joint circuit as claimed in claim 9, which is characterized in that the pulse-generating circuit further includes:
One inverter cricuit, reverse phase second pulse signal, to generate first pulse signal.
16. anti-suspension joint circuit as described in claim 1, which is characterized in that further include:
One core circuit is coupled between first power end and second source end；And
Voltage on first power end or second source end is provided according to first output signal and gives core electricity by one switch
Road.
17. anti-suspension joint circuit as described in claim 1, which is characterized in that further include:
One phase inverter, reverse phase first output signal, to generate one second output signal；
One core circuit is coupled between first power end and second source end；And
Voltage on first power end or second source end is provided according to second output signal and gives core electricity by one switch
Road.
18. anti-suspension joint circuit as described in claim 1, which is characterized in that further include:
One second pull-up circuit, comprising:
One third P-type transistor, source electrode couple first power end, and drain electrode provides one second output signal；And
One the 4th P-type transistor, source electrode couple first power end, and drain electrode couples the grid of the third P-type transistor,
Grid couples the drain electrode of the third P-type transistor；
One second pull-down circuit, comprising:
One third N-type transistor, grid receive one second inversion signal, and source electrode couples the second source end；And
One the 4th N-type transistor, grid receive one second input signal, and source electrode couples the second source end；And
One second control circuit, coupling is between second pull-up circuit and second pull-down circuit；
Wherein, in the first mode, the second control circuit be connected the third P-type transistor and the third N-type transistor it
Between one the 4th path and the 4th P-type transistor and the 4th N-type transistor between one the 5th path, and be not turned on
One the 6th path between the third P-type transistor and the second source end；
Wherein, in this second mode, which is not turned on the 4th path and the 5th path, and be connected this
Six paths.
19. anti-suspension joint circuit as claimed in claim 18, which is characterized in that the second control circuit includes:
One first control element is coupled between the third P-type transistor and the third N-type transistor；
One second control element, is coupled between the 4th P-type transistor and the 4th N-type transistor；And
One third control element is coupled between the third P-type transistor and the second source end；
Wherein, in the first mode, which is connected the 4th path according to a third pulse signal, this second
The 5th path is connected according to the third pulse signal in control element, which does not lead according to one the 4th pulse signal
Lead to the 6th path；
Wherein, in this second mode, which is not turned on the 4th path according to the third pulse signal, this
Two control elements are not turned on the 5th path according to the third pulse signal, and the third control element is according to the 4th pulse signal
The 6th path is connected.
20. anti-suspension joint circuit as claimed in claim 19, which is characterized in that further include:
One core circuit is coupled between first power end and second source end；
Voltage on first power end is provided according to first output signal and gives the core circuit by one first switch；And
Voltage on the second source end is provided according to second output signal and gives the core circuit by one second switch.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201810389713.XA CN110417402B (en) | 2018-04-27 | 2018-04-27 | Anti-floating circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201810389713.XA CN110417402B (en) | 2018-04-27 | 2018-04-27 | Anti-floating circuit |
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| CN110417402A true CN110417402A (en) | 2019-11-05 |
| CN110417402B CN110417402B (en) | 2023-04-25 |
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| CN201810389713.XA Active CN110417402B (en) | 2018-04-27 | 2018-04-27 | Anti-floating circuit |
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Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101459424A (en) * | 2007-09-06 | 2009-06-17 | 王朝钦 | Input output device for mixed-voltage tolerant |
| CN107204610A (en) * | 2016-03-18 | 2017-09-26 | 世界先进积体电路股份有限公司 | Drive circuit |
| US20180090924A1 (en) * | 2016-09-26 | 2018-03-29 | Infineon Technologies Ag | Power switch device |
-
2018
- 2018-04-27 CN CN201810389713.XA patent/CN110417402B/en active Active
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101459424A (en) * | 2007-09-06 | 2009-06-17 | 王朝钦 | Input output device for mixed-voltage tolerant |
| CN107204610A (en) * | 2016-03-18 | 2017-09-26 | 世界先进积体电路股份有限公司 | Drive circuit |
| US20180090924A1 (en) * | 2016-09-26 | 2018-03-29 | Infineon Technologies Ag | Power switch device |
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| Publication number | Publication date |
|---|---|
| CN110417402B (en) | 2023-04-25 |
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