JP2013219669A - Semiconductor integrated circuit device and level shift circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a level shift circuit with reduced jitter and a semiconductor integrated circuit device equipped with the level shift circuit.SOLUTION: A level shift circuit includes a first circuit and a second circuit including first and second withstand-voltage protection circuits. The first circuit is driven based on a voltage at a connection node between the first and second withstand-voltage protection circuits. The first circuit includes first and second transistors setting the amplitude of an output signal to a second logic level; and third and fourth transistors setting the amplitude of the output signal to a first logic level. The second circuit includes fifth and sixth transistors receiving the output signal and an inverted output signal in which the output signal is logically inverted and controlling whether to output a signal of the second logic level; and a seventh and eighth transistors driving the fifth and sixth transistors. The first withstand-voltage protection circuit is disposed between the fifth and sixth transistors and the seventh and eighth transistors, and the second withstand-voltage protection circuit is disposed between the first withstand-voltage protection circuit and the seventh and eighth transistors.

Description

  The present invention relates to a semiconductor integrated circuit device, and more particularly to a level shift circuit for driving a high voltage output driver that outputs a signal to the outside of the semiconductor integrated circuit device.

  Transistors used in semiconductor integrated circuits include low withstand voltage elements and high withstand voltage elements. The low withstand voltage element has, for example, a single oxide (SOX) structure with a thin gate oxide film and a small transistor size. Here, the transistor having the SOX structure is referred to as a SOX transistor. The high breakdown voltage element has, for example, a multi-oxide (MOX) structure in which the gate oxide film is thicker than the low breakdown voltage element and the transistor size is large. Here, the MOX transistor is referred to as a MOX transistor. Semiconductor integrated circuits have been miniaturized year by year, and internal transistors mainly using SOX transistors are scaled in consideration of performance and power density. On the other hand, the external transistor using the MOX transistor is designed mainly considering the interface standard between devices. In a semiconductor integrated circuit corresponding to a plurality of interface standards between devices, there has been a method of manufacturing with triple oxide (SOX + MOX for 1.8 volts + MOX for 3.3 volts). There is an increasing demand for a plurality of standards including an interface standard of 3 V to support external transistors with only 1.8V MOX transistors.

  Japanese Patent Laid-Open No. 9-172368 discloses a technique of a semiconductor output circuit that drives an internal circuit with a low voltage power supply, converts an output signal of the internal circuit into a level of a high voltage power supply that drives an external circuit, and outputs the converted signal. It is disclosed. In this technique, the semiconductor output circuit includes a series connection circuit, a clamp circuit, a latch circuit, and a latch inversion circuit. The series connection circuit includes a first p-channel MOS transistor whose source is connected to a high-voltage power supply and a second p-channel MOS transistor whose drain is connected to the output terminal. The clamp circuit clamps the intermediate voltage. The latch circuit operates between the high voltage power supply and the clamp voltage. The latch inversion circuit operates between the clamp voltage and the ground voltage. The output terminal of the latch circuit is connected to the gate of the first p-channel MOS transistor.

  Japanese Patent Laid-Open No. 9-148915 discloses that the power supply voltage of the external LSI is not applied to the gate oxide film of each MOS transistor even if the power supply voltage of the external LSI is higher than the gate oxide film breakdown voltage of the MOS transistor. A technique of an output circuit capable of outputting a signal having a voltage as an amplitude is disclosed. This output circuit receives an output signal of one circuit having the first voltage as the power supply voltage as an input, and outputs a signal from the output unit to another circuit using the second voltage as the power supply voltage in accordance with the output signal of the one circuit. Is output. The output circuit includes a signal generation circuit, a voltage conversion circuit, a pull-up circuit, and a pull-down circuit. The signal generation circuit generates first and second control signals whose amplitude is a voltage difference between the first voltage and the ground voltage based on the input output signal of the one circuit. The voltage conversion circuit receives the first control signal generated by the signal generation circuit as input, and generates and outputs a pull-up control signal by converting the amplitude of the first control signal. The pull-up circuit includes a first P-type MOS transistor and a second P-type MOS transistor. In the first P-type MOS transistor, a second voltage is applied to the source, and a pull-up control signal is input to the gate. In the second P-type MOS transistor, the source is connected to the drain of the first P-type MOS transistor, the drain is connected to the output section, and the third voltage is applied to the gate. That is, the pull-up circuit receives the pull-up control signal output from the voltage conversion circuit, and controls whether or not the voltage of the output unit is raised to the second voltage according to the instruction of the pull-up control signal. The pull-down circuit includes a first N-type MOS transistor and a second N-type MOS transistor. In the first N-type MOS transistor, the source is grounded and the pull-down control signal is input to the gate. In the second N-type MOS transistor, the source is connected to the drain of the first N-type MOS transistor, the drain is connected to the output unit, and the first voltage is applied to the gate. That is, the pull-down circuit inputs the second control signal generated by the signal generation circuit as a pull-down control signal, and controls whether or not the voltage of the output unit is lowered to the ground voltage in accordance with an instruction of the pull-down control signal. When the voltage conversion circuit instructs the pull-up circuit to raise the voltage of the output unit to the second voltage, the voltage of the pull-up control signal is changed from the second voltage to the threshold voltage of the first P-type MOS transistor. The voltage is equal to or lower than the subtracted voltage and equal to or higher than the voltage obtained by subtracting the voltage equivalent to the gate oxide film breakdown voltage of the first P-type MOS transistor from the second voltage. Further, when the pull-up circuit is not instructed to raise the voltage of the output unit to the second voltage, the voltage conversion circuit sets the voltage of the pull-up control signal to the second voltage.

  In such a circuit, since the intermediate voltage generated by the intermediate voltage generation circuit is used, jitter is large.

Japanese Patent Laid-Open No. 9-172368 Japanese Patent Laid-Open No. 9-148915

In such a circuit, since the intermediate voltage generated by the intermediate voltage generation circuit is used, jitter is large. Therefore, a level shift circuit with less jitter and a semiconductor integrated circuit device equipped with the level shift circuit are provided.
Other problems and novel features will become apparent from the description of the specification and the accompanying drawings.

  According to an embodiment, the level shift circuit includes a first circuit and a second circuit including a first withstand voltage protection circuit and a second withstand voltage protection circuit, and the first circuit includes the first withstand voltage protection circuit. And the second breakdown voltage protection circuit are driven based on the voltage of the connection node. The first circuit sets the amplitude of the output signal based on the first power supply voltage that determines the first logic level of the output signal and the second power supply voltage that determines the second logic level of the output signal. 1 and a second transistor, and a third and a fourth transistor. The first power supply voltage indicates a voltage value between the second power supply voltage and the reference power supply voltage. The first and second transistors set the amplitude of the output signal to the second logic level. The third and fourth transistors set the amplitude of the output signal to the first logic level. The second circuit includes fifth and sixth transistors, seventh and eighth transistors, a first breakdown voltage protection circuit, and a second breakdown voltage protection circuit. The fifth and sixth transistors control whether or not the output signal and the inverted output signal obtained by logically inverting the output signal are input and the signal of the second logic level is output. The seventh and eighth transistors receive an input signal indicating a voltage value between the first power supply voltage and the reference power supply voltage, and drive the fifth and sixth transistors. The first withstand voltage protection circuit is disposed between the fifth and sixth transistors and the seventh and eighth transistors, and protects the withstand voltages of the fifth and sixth transistors. The second breakdown voltage protection circuit is disposed between the first breakdown voltage protection circuit and the seventh and eighth transistors, and protects the breakdown voltage of the seventh and eighth transistors.

  The semiconductor integrated circuit device includes the level shift circuit and an output buffer circuit driven in response to an output signal of the level shift circuit.

  According to the embodiment, it is possible to provide a level shift circuit with less jitter and a semiconductor integrated circuit device equipped with the level shift circuit.

FIG. 1 is a block diagram illustrating a configuration of an output circuit of a semiconductor integrated circuit device. FIG. 2 is a block diagram showing a schematic configuration of the level shift circuit according to the first embodiment. FIG. 3 is a circuit diagram showing a circuit configuration of the level shift circuit according to the first embodiment. FIG. 4 is a block diagram showing a schematic configuration of the level shift circuit according to the second embodiment. FIG. 5 is a circuit diagram showing a circuit configuration of the level shift circuit according to the second embodiment. FIG. 6A is a diagram illustrating a voltage applied to each transistor when the voltage of the input signal is the reference power supply voltage (0 volt). FIG. 6B is a diagram illustrating a voltage applied to each transistor when the voltage of the input signal is the first power supply voltage (VCCL). FIG. 7 is a diagram illustrating the voltage of each node. FIG. 8 is a diagram showing a result of simulating the operation.

  Embodiments will be described with reference to the drawings.

  FIG. 1 is a diagram illustrating a configuration of a semiconductor integrated circuit. As shown in FIG. 1A, the semiconductor integrated circuit 50 includes a pad 53 to which an external terminal is connected and an internal circuit 55 that is the core of the semiconductor integrated circuit 50 and performs the main function of the semiconductor integrated circuit. An internal logic area 51 and an interface area 52 having an input / output circuit arranged between the internal logic area 51 and the outside for matching electrical characteristics are provided. When an output signal is connected to the pad 53, a level shift circuit 56 and a driver circuit 57 are arranged in the interface region 52 as shown in FIG. The level shift circuit 56 converts the level of the signal output from the internal circuit 55 arranged in the internal logic area 51 so that the driver circuit 57 can be driven.

  Usually, the internal circuit 55 arranged in the internal logic region 51 is configured by a low breakdown voltage transistor, and the driver circuit 57 for driving the external circuit is configured by a high breakdown voltage transistor. Therefore, although it is preferable to use a high breakdown voltage transistor for the level shift circuit 56, as described above, it is required to be configured using only a low breakdown voltage transistor.

(First embodiment)
FIG. 2 is a block diagram showing a configuration of the level shift circuit 56 that outputs a high voltage level signal using the low breakdown voltage transistor according to the first embodiment. The level shift circuit 56 includes a first circuit 10 and a second circuit. Here, the reference power supply voltage GND is 0 (volt), the low power supply voltage (for example, 1.8 volts) is the first power supply voltage VCCL, and the high power supply voltage (for example, 3.3 volts) is the second power supply voltage VCCH. The first circuit inputs a signal having an amplitude in the range of 0 volt to the second power supply voltage VCCH and converts the signal from the first power supply voltage VCCL, which is a desired signal level, to a signal having an amplitude in the range of the second power supply voltage VCCH. And output. The second circuit 20 inputs a signal having an amplitude in the range of 0 volt to the first power supply voltage VCCL output from the internal circuit 55, and converts the signal to a signal having an amplitude in the range of 0 volt to the second power supply voltage VCCH. Output. In addition, the second circuit 20 inputs a signal having an amplitude in the range from the first power supply voltage VCCL output from the first circuit 10 to the second power supply voltage VCCH.

  FIG. 3 is a circuit diagram showing a specific circuit configuration of the level shift circuit 56 including the first circuit 10 and the second circuit 20. The level shift circuit 56 according to the first embodiment includes a first circuit 10, a second circuit 20, and an inverter circuit 40 that generates an inverted signal of the input signal IN. The first circuit 10 includes P-channel MOS transistors (hereinafter abbreviated as P transistors) P15, P16, P25, and P26. The second circuit 20 includes P transistors P13, P14, P23, and P24, and N channel type MOS transistors (hereinafter abbreviated as N transistors) N11, N12, N21, and N22.

  In the first circuit 10, P transistors P15 and P16 are connected in series between the second power supply voltage VCCH and the first power supply voltage VCCL, and P transistors P25 and P26 are connected in series in parallel therewith. That is, the source of the P transistor P15 is connected to the second power supply voltage VCCH, the drain of the P transistor P15 and the source of the P transistor P16 are connected to the node OUTB, and the drain of the P transistor P16 is connected to the first power supply voltage VCCL. The The source of the P transistor P25 is connected to the second power supply voltage VCCH, the drain of the P transistor P25 and the source of the P transistor P26 are connected to the node OUTP, and the drain of the P transistor P26 is connected to the first power supply voltage VCCL. The gate of P transistor P15 is connected to node OUTP, and the gate of P transistor P25 is connected to node OUTB. The gate of P transistor P16 is connected to node a2, and the gate of P transistor P26 is connected to node b2. The back gates of the P transistors P15, P16, P25, and P26 are connected to the second power supply voltage VCCH.

  In the second circuit 20, P transistors P14 and P13 and N transistors N12 and N11 are connected in series in this order between the second power supply voltage VCCH and the reference power supply voltage GND. In parallel with this, P transistors P24 and P23 and N transistors N22 and N21 are connected in series in this order between the second power supply voltage VCCH and the reference power supply voltage GND. The gate of the N transistor N11 is connected to the node INP, and the input signal IN is applied. The gate of the N transistor N21 is connected to the node INB, and a signal obtained by logically inverting the input signal IN by the inverter circuit 40 is applied. The sources of the N transistors N11 and N21 are connected to the reference power supply voltage GND. The drain of the N transistor N11 and the source of the N transistor N12 are connected to the node a1. The drain of the N transistor N21 and the source of the N transistor N22 are connected to the node b1. The back gates of the N transistors N11, N12, N21, and N22 are connected to the reference power supply voltage GND.

  The drain of the N transistor N12 and the drain of the P transistor P13 are connected to the node a2 and further to the gate of the P transistor P16. The node a2 is one of output nodes of the second circuit 20. The drain of the N transistor N22 and the drain of the P transistor P23 are connected to the node b2, and the node b2 connected to the gate of the P transistor P26 is one of the output nodes of the second circuit 20. The source of the P transistor P13 and the drain of the P transistor P14 are connected to the node a3, and the source of the P transistor P14 is connected to the second power supply voltage VCCH. The source of the P transistor P23 and the drain of the P transistor P24 are connected to the node b3, and the source of the P transistor P24 is connected to the second power supply voltage VCCH. The gates of the N transistors N12 and N22 and the gates of the P transistors P13 and P23 are connected to the first power supply voltage VCCL. Therefore, the N transistors N12 and N22 and the P transistors P13 and P23 are always on and function as a withstand voltage protection transistor. The back gates of the P transistors P13, P14, P23, and P24 are connected to the second power supply voltage VCCH.

  The operation of the level shift circuit according to the first embodiment will be described.

  First, the operation when the input signal IN falls will be described. When the input signal IN transitions from the first power supply voltage VCCL (high level) to the reference power supply voltage GND = 0 volts (low level), the N transistor N11 is turned off. The input signal IN is logically inverted by the inverter circuit 40, the node INB becomes the first power supply voltage VCCL (high level), and the N transistor N21 is turned on. When the N transistor N21 is turned on, the voltage at the node b1 drops, and the voltage at the node b2 connected to the node b1 through the N transistor N22 which is always on is also lowered. When the voltage at the node b2 decreases, the P transistor P26 is turned on.

  When the P transistor P26 is turned on, the voltage at the node OUTP decreases toward the first power supply voltage VCCL. The P transistors P14 and P15 whose gates are connected to the node OUTP are turned on, and the voltages of the nodes a3 and OUTB rise toward the second power supply voltage VCCH. The voltage of the node a2 connected to the node a3 via the normally-on P transistor P13 also rises, and the P transistor P16 whose gate is connected to the node a2 is almost turned off or weakly turned on. The voltage of the node a1 connected to the node a2 via the N transistor N12 that is always on increases to “VCCL−Vtn”. Here, Vtn is the threshold voltage of the N transistor. Since the P transistor P16 is almost turned off, the voltage of the node OUTB becomes the second power supply voltage VCCH, and the P transistors P24 and P25 are turned off. Since the P transistor P25 is turned off, the voltage of the node OUTP becomes the first power supply voltage VCCL. Further, when the voltage at the node OUTB becomes the second power supply voltage VCCH, the P transistor P14 also applies the second power supply voltage VCCH to the node a2 via the node a3, so that the P transistor P16 is completely turned off.

  When the input signal IN rises, that is, when the input signal IN transits from the reference power supply voltage GND = 0 volt (low level) to the first power supply voltage VCCL (high level), the N transistor N11 is turned on and an inverted signal is input The N transistor N21 to be turned off is turned off. When the N transistor N11 is turned on, the voltage at the node a1 drops, and the voltage at the node a2 connected to the node a1 via the N transistor N12 that is always on also drops. When the voltage at the node a2 decreases, the P transistor P16 is turned on.

  When the P transistor P16 is turned on, the voltage of the node OUTB decreases toward the first power supply voltage VCCL. The P transistors P24 and P25 whose gates are connected to the node OUTB are turned on, and the voltages of the nodes b3 and OUTP rise toward the second power supply voltage VCCH. The voltage of the node b2 connected to the node b3 through the normally-on P transistor P23 also rises, and the P transistor P26 whose gate is connected to the node b2 is almost turned off or weakly turned on. The voltage of the node b1 connected to the node b2 through the N transistor N22 that is always on increases to “VCCL−Vtn”. Since the P transistor P26 is almost turned off, the voltage of the node OUTP becomes the second power supply voltage VCCH, and a signal having the level of the second power supply voltage VCCH is output as the output signal OUT. When the voltage at the node OUTP becomes the second power supply voltage VCCH, the P transistors P14 and P15 are turned off. Since the P transistor P15 is turned off, the voltage of the node OUTB becomes the first power supply voltage VCCL. When the voltage of the node OUTP becomes the second power supply voltage VCCH, the P transistor P24 also applies the second power supply voltage VCCH to the node a1 via the node a4, so that the P transistor P26 is completely turned off. The breakdown voltage conditions of each transistor will be described later.

(Second Embodiment)
FIG. 4 is a block diagram showing a configuration of a level shift circuit 56 that outputs a high voltage level signal using the low breakdown voltage transistor according to the second embodiment. The level shift circuit 56 according to the second embodiment includes a first circuit 10, a second circuit 20, and a third circuit 30. The first circuit 10 and the second circuit 20 are the same as the first circuit 10 and the second circuit 20 of the level shift circuit 56 according to the first embodiment, and the level according to the second embodiment. The shift circuit is a circuit to which the third circuit 30 is added, and will be described redundantly.

  When the reference power supply voltage GND is 0 volt, the low power supply voltage is the first power supply voltage VCCL, and the high power supply voltage is the second power supply voltage VCCH, the first circuit 10 has an amplitude in the range of 0 volt to the second power supply voltage VCCH. It is a level conversion circuit that inputs a signal, converts it into a signal having an amplitude in the range of the first power supply voltage VCCL, which is a desired signal level, and the second power supply voltage VCCH, and outputs the signal.

  The second circuit 20 is a level conversion circuit that receives a signal in the range of 0 volt to the first power supply voltage VCCL output from the internal circuit 55 and outputs a signal having an amplitude of the second power supply voltage VCCH from 0 volt. . The second circuit 20 inputs the output signal of the first circuit 10 and the output signal of the third circuit 30.

  The third circuit 30 inputs a signal having an amplitude in the range of 0 volt to the first power supply voltage VCCL and a signal having an amplitude in the range of 0 volt to the second power supply voltage VCCH, and the operation speed of the second circuit 20 It is a circuit that improves the above. The first circuit 10, the second circuit 20, and the third circuit 30 transmit and receive signals having amplitudes ranging from 0 volts to the second power supply voltage VCCH, but the withstand voltage condition is satisfied.

  FIG. 5 is a circuit diagram showing a specific circuit configuration of the level shift circuit 56 according to the second embodiment. The level shift circuit 56 according to the second embodiment includes a first circuit 10, a second circuit 20, a third circuit 30, and an inverter circuit 40 that generates an input inverted signal. The first circuit 10 includes P transistors P15, P16, P25, and P26. The second circuit 20 includes P transistors P13, P14, P23, and P24, and N transistors N11, N12, N21, and N22. The third circuit 30 includes P transistors P17, P18, P27, and P28.

  In the first circuit 10, P transistors P15 and P16 are connected in series between the second power supply voltage VCCH and the first power supply voltage VCCL, and P transistors P25 and P26 are connected in series in parallel therewith. That is, the source of the P transistor P15 is connected to the second power supply voltage VCCH, the drain of the P transistor P15 and the source of the P transistor P16 are connected to the node OUTB, and the drain of the P transistor P16 is connected to the first power supply voltage VCCL. The The source of the P transistor P25 is connected to the second power supply voltage VCCH, the drain of the P transistor P25 and the source of the P transistor P26 are connected to the node OUTP, and the drain of the P transistor P26 is connected to the first power supply voltage VCCL. The gate of P transistor P15 is connected to node OUTP, and the gate of P transistor P25 is connected to node OUTB. The gate of P transistor P16 is connected to node a2, and the gate of P transistor P26 is connected to node b2. The back gates of the P transistors P15, P16, P25, and P26 are connected to the second power supply voltage VCCH.

  In the second circuit 20, P transistors P14 and P13 and N transistors N12 and N11 are connected in series in this order between the second power supply voltage VCCH and the reference power supply voltage GND. In parallel with this, P transistors P24 and P23 and N transistors N22 and N21 are connected in series in this order between the second power supply voltage VCCH and the reference power supply voltage GND. The gate of the N transistor N11 is connected to the node INP, and the input signal IN is applied. The gate of the N transistor N21 is connected to the node INB, and a signal obtained by logically inverting the input signal IN by the inverter circuit 40 is applied. The sources of the N transistors N11 and N21 are connected to the reference power supply voltage GND. The drain of the N transistor N11 and the source of the N transistor N12 are connected to the node a1. The drain of the N transistor N21 and the source of the N transistor N22 are connected to the node b1. The back gates of the N transistors N11, N12, N21, and N22 are connected to the reference power supply voltage GND.

  The drain of the N transistor N12 and the drain of the P transistor P13 are connected to the node a2 and further to the gate of the P transistor P16. The node a2 is one of output nodes of the second circuit 20. The drain of the N transistor N22 and the drain of the P transistor P23 are connected to the node b2, and the node b2 connected to the gate of the P transistor P26 is one of the output nodes of the second circuit 20. The source of the P transistor P13 and the drain of the P transistor P14 are connected to the node a3, and the source of the P transistor P14 is connected to the second power supply voltage VCCH. The source of the P transistor P23 and the drain of the P transistor P24 are connected to the node b3, and the source of the P transistor P24 is connected to the second power supply voltage VCCH. The gates of the N transistors N12 and N22 and the gates of the P transistors P13 and P23 are connected to the first power supply voltage VCCL. Therefore, the N transistors N12 and N22 and the P transistors P13 and P23 are always on and function as a withstand voltage protection transistor. The back gates of the P transistors P13, P14, P23, and P24 are connected to the second power supply voltage VCCH.

  In the third circuit 30, P transistors P17 and P18 are connected in series between the first power supply voltage VCCL and the node a1, and P transistors P27 and P28 are connected in series between the first power supply voltage VCCL and the node b1. Is done. That is, the source of the P transistor P17 is connected to the first power supply voltage VCCL, and the drain of the P transistor P18 is connected to the node a1. The drain of the P transistor P17 and the source of the P transistor P18 are connected to the node a4. The gate of the P transistor P17 is connected to the node a2, and the gate of the P transistor P18 is connected to the node INP. The source of the P transistor P27 is connected to the first power supply voltage VCCL, and the drain of the P transistor P28 is connected to the node b1. The drain of the P transistor P27 and the source of the P transistor P28 are connected to the node b4. The gate of P transistor P27 is connected to node b2, and the gate of P transistor P28 is connected to node INB. The back gates of the P transistors P17, P18, P27, and P28 are connected to the first power supply voltage VCCL.

  The operation of the level shift circuit according to the second embodiment will be described.

  First, the operation when the input signal IN falls will be described. When the input signal IN transitions from the first power supply voltage VCCL (high level) to the reference power supply voltage GND = 0 volt (low level), the N transistor N11 is turned off and the P transistor P18 is turned on. At this time, the P transistor P17 connected to the source of the P transistor P18 maintains the state when the input signal IN is the first power supply voltage VCCL (high level). That is, since the voltage of the node a2 is 0 volt (low level), the P transistor P17 is in the on state, and the voltage of the node a1 increases.

  Since the gate of the P transistor P17 is connected to the node a1 through the N transistor N12 that is always on, the voltage at the node a1 and the node a2 is changed from 0 volt to “VCCL-Vtn” or “VCCL-Vtp”. Asymptotically. Here, Vtn is the threshold voltage of the N transistor, and Vtp is the threshold voltage of the P transistor.

  The voltage at the node a2 rises until the P transistors P17 and P16 connected to the first power supply voltage VCCL are substantially turned off or weakly turned on. Therefore, the P transistor P16 connected to the gate of the node a2 is turned off or weakly turned on.

  When the input signal IN transits from the first power supply voltage VCCL (high level) to 0 volt (low level), the voltage of the node INB becomes high level, and the N transistor N21 is turned on. Therefore, the voltage at the node b1 drops from “VCCL−Vtn” to 0 volts. At this time, the voltage of the node b2 maintains the state when the input signal IN is the first power supply voltage VCCL (high level), and indicates the second power supply voltage VCCH. When the N transistor N21 is turned on, the voltage at the node b2 drops toward 0 volt which is the same as the voltage at the node b1 via the N transistor N22.

  When the voltage of the node b2 drops below “VCCL−Vtp”, the P transistor P26 is turned on. When the P transistor P26 is turned on, the output signal OUT drops from the second power supply voltage VCCH.

  When the output signal OUT drops below “VCCH−Vtp”, the P transistors P14 and P15 whose gates are connected to the node OUTP are turned on. When the P transistor P14 is turned on, the voltage of the node a3 increases toward the second power supply voltage VCCH. When the voltage of the node a3 exceeds “VCCL + Vtp”, the voltage of the node a2 connected to the node a3 via the P transistor P13 becomes equal to the voltage of the node a3.

  When the voltage of the node a2 reaches the first power supply voltage VCCL, the P transistor P16 whose gate is connected to the node a2 is almost turned off (or weakly turned on), and the P transistor P17 is turned off. When the P transistor P16 is turned off, the voltage of the node OUTB becomes the second power supply voltage VCCH because the P transistor P15 is turned on. When the voltage of the node OUTB becomes the second power supply voltage VCCH, the P transistors P24 and P25 whose gates are connected to the node OUTB are turned off. Since the P transistor P26 is in the on state, the output signal OUT becomes the first power supply voltage VCCL.

  Next, the operation when the input signal IN rises will be described. When the input signal IN transits from the reference power supply voltage GND = 0 volts (low level) to the first power supply voltage VCCL (high level), the voltage of the node INB connected via the inverter circuit 40 becomes low level. When the voltage of the node INB becomes low level, the N transistor N21 is turned off and the P transistor P28 is turned on.

  The P transistor P27 connected to the source of the P transistor P28 maintains the state when the input signal IN is 0V (low level). That is, since the voltage of the node b2 is 0 volt (low level), the P transistor P27 is in the on state, and the voltage of the node b1 rises.

  Since the gate of the P-transistor P27 is connected to the node b1 via the N-transistor N22 that is always on, the voltages at the node b1 and the node b2 gradually approach “VCCL-Vtp” or “VCCL-Vtn”.

  The voltage of the node b2 rises until the P transistors P27 and P26 connected to the first power supply voltage VCCL are substantially turned off or weakly turned on. Therefore, the P transistor P26 connected to the gate of the node b2 is turned off or weakly turned on.

  When the input signal IN transits from 0 volts (low level) to the first power supply voltage VCCL (high level), the N transistor N11 is turned on and the P transistor P18 is turned off. Therefore, the voltage at the node a1 drops from “VCCL−Vtn” to 0 volts. At this time, the voltage of the node a2 maintains the state when the input signal IN is 0 volt (low level), and indicates the second power supply voltage VCCH. When the N transistor N11 is turned on, the voltage of the node a2 drops toward 0 volt which is the same as the voltage of the node a1 via the N transistor N12.

  When the voltage at the node a2 drops below “VCCL−Vtp”, the P-transistor P16 is turned on. When the P transistor P16 is turned on, the voltage of the node OUTB drops from the second power supply voltage VCCH.

  When the voltage of the node OUTB drops below “VCCH−Vtp”, the P transistors P24 and P25 whose gates are connected to the node OUTB are turned on. When the P transistor P24 is turned on, the voltage at the node b3 rises toward the second power supply voltage VCCH. When the voltage of the node b3 exceeds “VCCL + Vtp”, the voltage of the node b2 connected to the node b3 through the P transistor P23 becomes equal to the voltage of the node b3.

  When the voltage of the node b2 reaches the first power supply voltage VCCL, the P transistor P26 is almost turned off (or weakly turned on), and the P transistor P27 is turned off. When the P transistor P26 is turned off, the voltage of the node OUTP (output signal OUT) becomes the second power supply voltage VCCH because the P transistor P25 is turned on. When the voltage of the node OUTP becomes the second power supply voltage VCCH, the P transistors P14 and P15 whose gates are connected to the node OUTP are turned off. Since the P transistor P16 is in the on state, the voltage at the node OUTB becomes the first power supply voltage VCCL.

  Next, withstand voltage conditions of each transistor will be described with reference to FIGS. 6A, 6B, and 7. FIG.

  FIG. 6A is a list of voltages between nodes of each transistor when the input signal IN of the level shift circuit according to the second embodiment is the reference power supply voltage GND = 0 volts (low level), and FIG. It is a list of voltages between nodes of each transistor when the signal IN is the first power supply voltage VCCL (high level). FIG. 7 is a list of voltages at each node corresponding to the state of the input signal IN of the level shift circuit according to the second embodiment. Here, the second power supply voltage VCCH is, for example, 3.3 volts, and the first power supply voltage VCCL is, for example, 1.8 volts. Vtp is the threshold voltage of the P transistor, and Vtpn is the threshold voltage of the N transistor. The input signal IN changes in a range from the reference power supply voltage GND (0 V) to the first power supply voltage VCCL. Assuming that Vb is a voltage within an allowable withstand voltage range of the low withstand voltage transistor, it is assumed that the following relationship is satisfied for each voltage.

VCCH> Vb
Vb> VCCL
Vb> VCCH-VCCL
Vb> VCCL + Vtp
As shown in FIG. 7, when the input signal IN is the reference power supply voltage GND = 0 volts (low level), the node INB is logically inverted by the inverter circuit 40 and thus becomes “VCCL”. The nodes a1 and a4 are “VCCL-Vtn to VCCL”, and the nodes a2 and a3 are “VCCH”. The node OUTP becomes “VCCL”. The nodes b1 and b2 are “0”, the node b3 is “VCCL + Vtp”, the node b4 is “VCCL”, and the node OUTB is “VCCH”.

  When the input signal IN is the first power supply voltage VCCL (high level), the node INB is logically inverted by the inverter circuit 40, so that the node INB becomes “0”, and the nodes a1 and a2 become “0”. The node a3 becomes “VCCL + Vtp”. The node a4 becomes “VCCL”, and the node OUTP becomes “VCCH”. The node b1 is “VCCL-Vtn to VCCL”, the nodes b2 and b3 are “VCCH”, the node b4 is “VCCL-Vtn to VCCL”, and the node OUTB is “VCCL”.

  As shown in FIG. 6A, when the input signal IN is the reference power supply voltage GND = 0 volts (low level), in the N transistor N11, Vgs is “0”, Vds is “VCCL−Vtn”, and Vgd is “ VCCL-Vtn ". In the N transistor N12, Vgs is “Vtn”, Vds is “VCCH− (VCCL−Vtn)”, and Vgd is “VCCH−VCCL”. In the P transistor P13, Vgs is “VCCH-VCCL”, Vds is “0”, and Vgd is “VCCH-VCCL”. In the P transistor P14, Vgs is “VCCH− (VCCL + Vtp)”, Vds is “0”, and Vgd is “0”.

  When the input signal IN is 0 volt (low level), the node INB indicates a high level, and in the N transistor N21, Vgs is “VCCL”, Vds is “0”, and Vgd is “VCCL”. In the N transistor N22, Vgs is “VCCL”, Vgd is “VCCL”, and Vds is “0”. In the P transistor P23, Vgs becomes “Vtp”, Vgd becomes “VCCL + Vtp”, and Vds becomes “0”. In the P transistor P24, Vgs is “0”, Vgd is “VCCH− (VCCL + Vtp)”, and Vds is “VCCH− (VCCL + Vtp)”.

  In the P transistor P16, Vgs is “VCCH−VCCL”, Vgd is “0”, and Vds is “VCCH-VCCL”. In the P transistor P26, Vgs becomes “VCCL”, Vgd becomes “VCCL”, and Vds becomes “0”. In the P transistor P15, Vgs is “VCCH-VCCL”, Vgd is “VCCH-VCCL”, and Vds is “0”. In the P transistor P25, Vgs is “0”, Vgd is “VCCH-VCCL”, and Vds is “VCCH-VCCL”.

  In the P transistor P18, Vgs is “Vtn”, Vgd is “Vtn”, and Vds is “0”. In the P transistor P28, Vgs is “0”, Vgd is “VCCL”, and Vds is “VCCL”. In the P transistor P17, Vgs is “VCCH-VCCL”, Vgd is “VCCH- (VCCL-Vtn)”, and Vds is “Vtn”. In the P transistor P27, Vgs becomes “VCCL”, Vgd becomes “VCCL”, and Vds becomes “0”.

  Next, as shown in FIG. 6B, when the input signal IN is the first power supply voltage VCCL (high level), the gate-source voltage (hereinafter referred to as Vgs) of the N transistor N11 becomes “VCCL”, and the drain-source The inter-voltage (hereinafter Vds) is “0”, and the gate-drain voltage (hereinafter Vgd) is “VCCL”. Similarly, in the N transistor N12, Vgs is “VCCL”, Vds is “0”, and Vgd is “VCCL”. Since “VCCL” is applied to the gate of the P-transistor P13, the source voltage does not drop below “VCCL + Vtp”. Therefore, in the P transistor P13, Vgs is “Vtp”, Vds is “VCCL + Vtp”, and Vgd is “VCCL”. In the P transistor P14, Vgs becomes “0”, Vds becomes “VCCH− (VCCL + Vtp)”, and Vgd becomes “VCCH− (VCCL + Vtp)”.

  When the input signal IN is the first power supply voltage VCCL (high level), the voltage of the node INB indicates a low level, and in the N transistor N21, Vgs is “0” and Vds is “(VCCL−Vtn)”. Vgd is “(VCCL−Vtn)”. In the N transistor N22, Vgs is “Vtn”, Vgd is “VCCH−VCCL”, and Vds is “VCCH− (VCCL−Vtn)”. In the P transistor P23, Vgs becomes “VCCH-VCCL”, Vgd becomes “VCCH-VCCL”, and Vds becomes “0”. In the P transistor P24, Vgs becomes “VCCH− (VCCL + Vtp)”, Vgd becomes “0”, and Vds becomes “0”.

  In the P transistor P16, Vgs is “VCCL”, Vgd is “VCCL”, and Vds is “0”. In the P transistor P26, Vgs is “VCCH-VCCL”, Vgd is “0”, and Vds is “VCCH-VCCL”. In the P transistor P15, Vgs is “0”, Vgd is “VCCH-VCCL”, and Vds is “VCCH-VCCL”. In the P transistor P25, Vgs becomes “VCCH-VCCL”, Vgd becomes “VCCH-VCCL”, and Vds becomes “0”.

  In the P transistor P18, Vgs is “0”, Vgd is “VCCL”, and Vds is “VCCL”. In the P transistor P28, Vgs is “Vtn”, Vgd is “Vtn”, and Vds is “0”. In the P transistor P17, Vgs becomes “VCCL”, Vgd becomes “VCCL”, and Vds becomes “0”. In the P transistor P27, Vgs is “VCCH−VCCL”, Vgd is “VCCH− (VCCL−Vtn)”, and Vds is “Vtn”.

FIG. 8 shows a SPICE (Simulation Program with Integrated) level shift circuit according to the second embodiment.
The result of having simulated operation | movement by Circuit Emphasis) is shown. It can be seen that it operates as explained above. The input signal IN is a signal indicating a random pattern of 50 MHz (FIG. 8 “input IN (Vin)”), and the output signal OUT (output 8 in FIG. 8) is described in Japanese Patent Laid-Open No. 9-172368 as a comparison signal. The result is shown together with the result of simulation of the circuit (“output Vg11” in FIG. 8). In the circuit described in Japanese Patent Laid-Open No. 9-172368, since the voltage when the output signal Vg11 is output at a low level is an intermediate potential, jitter occurs in response to a response to a random pattern with an operating frequency of 50 MHz. In the level shift circuit according to the embodiment, the swing level of the output signal OUT is stable between the first power supply voltage VCCL and the second power supply voltage VCCH with respect to a random pattern with an operating frequency of 50 MHz, and jitter is reduced. It turns out that it is very few.

  As described above, since the gate voltage of each transistor becomes a power supply voltage without the node to which the gate is connected being in a floating state, jitter is reduced. Further, since the voltage between nodes of each transistor in the circuit is only the combination shown in FIGS. 6A and 6B and does not exceed the withstand voltage range Vb, there is no problem in terms of withstand voltage. Therefore, the withstand voltage can be guaranteed regardless of the input state (low level / high level).

  As mentioned above, the invention made by the present inventor has been specifically described based on the embodiment. However, the present invention is not limited to the embodiment, and various modifications can be made without departing from the scope of the invention. Needless to say.

DESCRIPTION OF SYMBOLS 10 1st circuit 20 2nd circuit 30 3rd circuit 50 Semiconductor integrated circuit 51 Internal logic area | region 52 Interface area | region 53 Pad 55 Internal circuit 56 Level shift circuit 57 Driver circuit N11, N12, N21, N22 N channel type MOS transistors P13-P18 , P23-P28 P-channel MOS transistors

Claims (9)

Based on a first power supply voltage that determines a first logic level of the output signal and a second power supply voltage that determines a second logic level of the output signal, the amplitude of the output signal is set to the second logic level. The first and second transistors to be set to the first power supply voltage indicate a voltage value between the second power supply voltage and a reference power supply voltage;
A first circuit comprising: third and fourth transistors for setting the amplitude of the output signal to the first logic level;
Fifth and sixth transistors for controlling whether to output the second logic level signal by inputting the output signal and an inverted output signal obtained by logically inverting the output signal;
Seventh and eighth transistors that input an input signal indicating a voltage value between the first power supply voltage and the reference power supply voltage and drive the fifth and sixth transistors;
A first withstand voltage protection circuit disposed between the fifth and sixth transistors and the seventh and eighth transistors to protect the withstand voltages of the fifth and sixth transistors;
A second circuit comprising: the first withstand voltage protection circuit; and a second withstand voltage protection circuit disposed between the seventh and eighth transistors and protecting the withstand voltage of the seventh and eighth transistors,
The first circuit is a level shift circuit driven based on a voltage at a connection node between the first withstand voltage protection circuit and the second withstand voltage protection circuit. The first transistor and the third transistor are first conductivity type transistors, and are connected in series between the second power supply voltage and the first power supply voltage,
The second transistor and the fourth transistor are transistors of the first conductivity type, and are connected in series between the second power supply voltage and the first power supply voltage,
The source of the first transistor is connected to the second power supply voltage, the drain of the third transistor is connected to the first power supply voltage, and a connection node between the drain of the first transistor and the source of the third transistor. The output signal is output;
The source of the second transistor is connected to the second power supply voltage, the drain of the fourth transistor is connected to the first power supply voltage, and a connection node between the drain of the second transistor and the source of the fourth transistor. The inverted output signal is output;
The inverted output signal is applied to the gate of the first transistor, the output signal is applied to the gate of the second transistor, and the first withstand voltage protection circuit and the second withstand voltage protection circuit are applied to the gate of the third transistor. 2. The level according to claim 1, wherein a voltage of a first connection node of the first connection node is applied, and a voltage of a second connection node of the first breakdown voltage protection circuit and the second breakdown voltage protection circuit is applied to a gate of the fourth transistor. Shift circuit. The fifth transistor and the seventh transistor are connected in series via the first connection node,
The sixth transistor and the eighth transistor are connected in series via the second connection node,
The fifth transistor is a transistor of the first conductivity type, the source is connected to the second power supply voltage, the drain is connected to the first withstand voltage protection circuit, and the inverted output signal is applied to the gate,
The sixth transistor is the first conductivity type transistor, the source is connected to the second power supply voltage, the drain is connected to the first withstand voltage protection circuit, and the output signal is applied to the gate.
The seventh transistor is a transistor of a second conductivity type complementary to the first conductivity type, a source connected to the reference power supply voltage, a drain connected to the second withstand voltage protection circuit, and a gate connected to the input An inverted input signal with the logic inverted of the signal is applied,
The eighth transistor is a transistor of the second conductivity type, the source is connected to the reference power supply voltage, the drain is connected to the second withstand voltage protection circuit, and the input signal is applied to the gate. 3. The level shift circuit according to 2. The first withstand voltage protection circuit includes:
A ninth transistor of the first conductivity type connected between the fifth transistor and the first connection node and operating as a current source;
A tenth transistor of the first conductivity type connected between the sixth transistor and the second connection node and operating as a current source;
The second breakdown voltage protection circuit is:
An eleventh transistor of the second conductivity type connected between the first connection node and the seventh transistor and operating as a current source;
The level shift circuit according to claim 2, further comprising: a twelfth transistor of the second conductivity type that is connected between the second connection node and the eighth transistor and operates as a current source. The level shift circuit according to claim 4, wherein gates of the ninth to twelfth transistors are connected to the first power supply voltage. The third circuit for applying the first power supply voltage in response to the input signal to a connection node between the seventh and eighth transistors and the second withstand voltage protection circuit. The level shift circuit according to any one of the above. The third circuit includes:
13th and 14th transistors of the first conductivity type connected in series between the first power supply voltage and a third connection node to which the 7 transistors and the second withstand voltage circuit are connected;
15th and 16th transistors of the first conductivity type connected in series between the first power supply voltage and a fourth connection node to which the 8 transistors and the second breakdown voltage circuit are connected,
The thirteenth transistor has a source connected to the first power supply voltage, a gate connected to one connection node of the first withstand voltage protection circuit and the second withstand voltage protection circuit,
The fourteenth transistor has a source connected to the drain of the thirteenth transistor, a drain connected to the third connection node, and a gate applied with a signal obtained by logically inverting the input signal.
The fifteenth transistor has a source connected to the first power supply voltage and a gate connected to the other connection node of the first withstand voltage protection circuit and the second withstand voltage protection circuit,
The level shift circuit according to claim 6, wherein the sixteenth transistor has a source connected to a drain of the fifteenth transistor, a drain connected to the fourth connection node, and a gate applied with the input signal. The level shift circuit according to any one of claims 1 to 7, further comprising an inverter circuit that generates the inverted input signal based on the input signal IN. A level shift circuit according to any one of claims 1 to 7,
An output buffer circuit driven in response to an output signal of the level shift circuit. A semiconductor integrated circuit device.

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