CN101977046A - Bootstrap sampling switch circuit and bootstrap circuit - Google Patents
Bootstrap sampling switch circuit and bootstrap circuit Download PDFInfo
- Publication number
- CN101977046A CN101977046A CN 201010291312 CN201010291312A CN101977046A CN 101977046 A CN101977046 A CN 101977046A CN 201010291312 CN201010291312 CN 201010291312 CN 201010291312 A CN201010291312 A CN 201010291312A CN 101977046 A CN101977046 A CN 101977046A
- Authority
- CN
- China
- Prior art keywords
- nmos pass
- pass transistor
- pmos
- connects
- grid
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Images
Abstract
The invention provides a bootstrap sampling switch circuit and a bootstrap circuit. The bootstrap circuit comprises a diode D1, a charging capacitor C1, a phase inverter, a third P-channel metal oxide semiconductor (PMOS) tube M3, a fourth N-channel metal oxide semiconductor (NMOS) tube M4, a fifth NMOS tube M5, a sixth NMOS tube M6, a seventh PMOS tube M7 and an eighth NMOS tube M8, wherein the input end of the phase inverter is connected with a clock (CLK), while the output end is connected with the grid of the M3 and the grid of the M4; the source of the M3 is connected with a virtual device driver (VDD); the source of the M4 is connected with Vin; the drain of the M3 is connected with the drain of the M4; the source of the M5 is connected with the Vin; the grid of the M5 is connected with Vboot; the drain of the M5 is connected with the drain of the M6 and one plate of the capacitor; the grid of the M6 is connected with the CLK, while the source is connected with the ground (GND); the positive end of the D1 is connected with the VDD, while the negative end is connected with a second plate of the C1 and the source of the M7; the grid of the M7 is connected with the drain of the M3; the drain of the M7 and the source of the M8 are connected with the Vboot; and the grid of the M8 is connected with the VDD, while the drain is connected with the output end of the phase inverter.
Description
Technical field
The present invention relates to circuit design field, be meant a kind of bootstrapping sampling switch circuit and boostrap circuit especially.
Background technology
Along with the development of modern communications technology and signal processing technology, increasing to the demand of high speed, high-precision semiconductor integrated circuit.In the simulation process field, usually needing analog signal conversion is digital signal, is further processed by digital signal processing module again.In the process of digital signal, usually need to use sampling switch in analog signal conversion, to satisfy requirement to performance of analog-to-digital convertor.
Based on to the sampling switch performance demands, commonly used to the bootstrapping sampling switch.This technology is mainly used in sampling hold circuit.The structure of bootstrapped switch as shown in Figure 1, the bootstrapping sampling switch mainly comprise: grid voltage boostrap circuit 20 and nmos pass transistor 10 switches.The grid voltage boostrap circuit has two input CLK and Vin, an output Vout.
The grid voltage boostrap circuit of conventional art promotes circuit by a charging capacitor C, ten MOS transistor M1-M10 and a clock voltage and forms as shown in Figure 2.Clock CLK connects the grid of nmos pass transistor M1 and PMOS transistor M2, and the source electrode of M1 and M2 meets supply voltage VDD and GND respectively, and the drain electrode of M1 and M2 links to each other, and is designated as node 1, and in fact M1 and M2 have formed an inverter, and the output of direction device is node 1.Node 1 is as the input of clock voltage lifting circuit, and node 2 is the output that clock voltage promotes circuit.Node 2 connects the grid of nmos pass transistor M5, and the drain electrode of M5 meets supply voltage VDD, and source electrode connects the pole plate of charging capacitor C, links to each other with the source electrode of PMOS transistor M9 simultaneously.Node 1 connects the grid of nmos pass transistor M6, and the source electrode of M6 meets GND, and drain electrode connects another pole plate of charging capacitor C, links to each other with the source electrode of nmos pass transistor M4, M7 and M8 simultaneously.The grid of the grid of M4 and nmos pass transistor M3 all meets clock CLK, and the drain electrode of M4 connects the drain electrode of grid and the M8 of the drain electrode of M3, M9.The drain electrode of M9 links to each other with the grid of the grid of M8, M7 and the drain electrode of nmos pass transistor M10, as the output Vboot of grid voltage boostrap circuit.The source electrode of M10 meets GND, and grid connects node 1.The drain electrode of M7 meets the input Vin of grid voltage boostrap circuit.
When clock CLK was low level GND, node 1 and node 2 made M5, M6 conducting, and C charges to charging capacitor, and making C go up the voltage that keeps is VDD, M10 conducting this moment, and output voltage V boot is GND.When clock CLK was high level VDD, node 1 and node 2 disconnected M5, M6, M10, and M4 drags down the grid voltage of M9, make M7, M8, M9 conducting, so just make Vboot equal Vin and add that C goes up the voltage that keeps, promptly Vboot=Vin+VDD has finished the function that grid voltage is booted.M8 surpasses VDD for fear of the gate source voltage of M9, thereby improves device reliability.
Can see that traditional grid voltage boostrap circuit needs extra clock voltage to promote circuit, this circuit increases fixing value (being generally VDD) with the voltage of input clock.This extra clock voltage promotes the complexity that circuit has increased circuit.
Summary of the invention
The technical problem to be solved in the present invention provides a kind of bootstrapping sampling switch circuit and boostrap circuit that reduces circuit complexity.
For solving the problems of the technologies described above, embodiments of the invention provide technical scheme as follows:
A kind of bootstrapping sampling switch circuit comprises:
Boostrap circuit and the 9th nmos pass transistor;
Described boostrap circuit input clock signal CLK and treat sampled signal Vin exports the first signal Vboot; The source electrode of the 9th nmos pass transistor connects treats that sampled signal Vin, the grid of the 9th nmos pass transistor connect the described first signal Vboot, the drain electrode output secondary signal Vout of the 9th nmos pass transistor;
Described boostrap circuit comprises:
Diode, charging capacitor, inverter, the 3rd PMOS transistor, the 4th nmos pass transistor, the 5th nmos pass transistor, the 6th nmos pass transistor, the 7th PMOS transistor and the 8th nmos pass transistor;
The input of described inverter connects clock signal clk, and the output of described inverter connects the grid of transistorized grid of the 3rd PMOS and the 4th nmos pass transistor respectively;
The transistorized source electrode of the 3rd PMOS connects supply voltage VDD, and the source electrode of the 4th nmos pass transistor connects treats sampled signal Vin, and the drain electrode of the 3rd PMOS transistor drain and the 4th nmos pass transistor links to each other;
The source electrode of the 5th nmos pass transistor connects treats that sampled signal Vin, the grid of the 5th nmos pass transistor connect the first signal Vboot, and the drain electrode of the 5th nmos pass transistor connects the drain electrode of the 6th nmos pass transistor and first pole plate of charging capacitor respectively;
The grid of the 6th nmos pass transistor connects clock signal clk, and the source electrode of the 6th nmos pass transistor connects earth signal GND;
The forward end of diode connects supply voltage VDD, and the negative end of diode connects second pole plate and the transistorized source electrode of the 7th PMOS of charging capacitor respectively;
The transistorized grid of the 7th PMOS links to each other with the 3rd PMOS transistor drain, and the source electrode of the 7th PMOS transistor drain and the 8th nmos pass transistor all is connected the first signal Vboot;
The grid of the 8th nmos pass transistor connects supply voltage VDD, and the drain electrode of the 8th nmos pass transistor links to each other with the output of inverter.
Described inverter comprises: a PMOS transistor and second nmos pass transistor;
The grid of the transistorized grid of the one PMOS and second nmos pass transistor all is connected clock signal clk, as the input of inverter;
The transistorized source electrode of the one PMOS connects supply voltage VDD;
The source electrode of second nmos pass transistor connects earth signal GND;
The drain electrode of the one PMOS transistor drain and second nmos pass transistor links to each other, as the output of inverter.
Described bootstrapping sampling switch circuit is a semiconductor integrated circuit.
On the other hand, provide a kind of boostrap circuit, comprising:
Diode, charging capacitor, inverter, the 3rd PMOS transistor, the 4th nmos pass transistor, the 5th nmos pass transistor, the 6th nmos pass transistor, the 7th PMOS transistor and the 8th nmos pass transistor;
The input of described inverter connects clock signal clk, and the output of described inverter connects the grid of transistorized grid of the 3rd PMOS and the 4th nmos pass transistor respectively;
The transistorized source electrode of the 3rd PMOS connects supply voltage VDD, and the source electrode of the 4th nmos pass transistor connects treats sampled signal Vin, and the drain electrode of the 3rd PMOS transistor drain and the 4th nmos pass transistor links to each other;
The source electrode of the 5th nmos pass transistor connects treats that sampled signal Vin, the grid of the 5th nmos pass transistor connect the first signal Vboot, and the drain electrode of the 5th nmos pass transistor connects the drain electrode of the 6th nmos pass transistor and first pole plate of charging capacitor respectively;
The grid of the 6th nmos pass transistor connects clock signal clk, and the source electrode of the 6th nmos pass transistor connects earth signal GND;
The forward end of diode connects supply voltage VDD, and the negative end of diode connects second pole plate and the transistorized source electrode of the 7th PMOS of charging capacitor respectively;
The transistorized grid of the 7th PMOS links to each other with the 3rd PMOS transistor drain, and the source electrode of the 7th PMOS transistor drain and the 8th nmos pass transistor all is connected the first signal Vboot;
The grid of the 8th nmos pass transistor connects supply voltage VDD, and the drain electrode of the 8th nmos pass transistor links to each other with the output of inverter.
Described inverter comprises: a PMOS transistor and second nmos pass transistor;
The grid of the transistorized grid of the one PMOS and second nmos pass transistor all is connected clock signal clk, as the input of inverter;
The transistorized source electrode of the one PMOS connects supply voltage VDD;
The source electrode of second nmos pass transistor connects earth signal GND;
The drain electrode of the one PMOS transistor drain and second nmos pass transistor links to each other, as the output of inverter.
Described boostrap circuit is a semiconductor integrated circuit.
Embodiments of the invention have following beneficial effect:
In the such scheme, when clock signal clk was high level VDD, Vboot was low level GND.When clock signal clk is low level GND, Vboot be treat sampled signal Vin and charging capacitor voltage VDD-Vd and, Vd is the threshold voltage of diode, thereby has reached the function of grid voltage bootstrapping.Do not need extra clock voltage to promote circuit, reduced the complexity of circuit.
Description of drawings
Fig. 1 is the schematic diagram of bootstrapping sampling switch circuit in the prior art;
Fig. 2 is the schematic diagram of boostrap circuit in the prior art;
Fig. 3 is the schematic diagram of boostrap circuit of the present invention.
Embodiment
For technical problem, technical scheme and advantage that embodiments of the invention will be solved is clearer, be described in detail below in conjunction with the accompanying drawings and the specific embodiments.
The invention provides a kind of bootstrapping sampling switch circuit, comprising:
Boostrap circuit and the 9th nmos pass transistor M0;
Described boostrap circuit input clock signal CLK and treat sampled signal Vin exports the first signal Vboot; The source electrode of the 9th nmos pass transistor M0 connects treats that sampled signal Vin, the grid of the 9th nmos pass transistor M0 connect the described first signal Vboot, the drain electrode output secondary signal Vout of the 9th nmos pass transistor M0;
As shown in Figure 3, described boostrap circuit comprises:
Diode, charging capacitor, inverter, the 3rd PMOS (P-channel metal oxide semiconductor FET, the P-channel metal-oxide-semiconductor field-effect transistor) transistor M3, the 4th NMOS (N-channel metal oxide semiconductor FET, n channel metal oxide semiconductor field effect transistor) transistor M4, the 5th nmos pass transistor M5, the 6th nmos pass transistor M6, the 7th PMOS transistor M7 and the 8th nmos pass transistor M8;
The input of described inverter connects clock signal clk, and the output of described inverter connects the grid of the 3rd PMOS transistor M3 and the grid of the 4th nmos pass transistor M4 respectively;
The source electrode of the 3rd PMOS transistor M3 connects supply voltage VDD, and the source electrode of the 4th nmos pass transistor M4 connects treats sampled signal Vin, and the drain electrode of the 3rd PMOS transistor M3 links to each other with the drain electrode of the 4th nmos pass transistor M4;
The source electrode of the 5th nmos pass transistor M5 connects treats that sampled signal Vin, the grid of the 5th nmos pass transistor M5 connect the first signal Vboot, and the drain electrode of the 5th nmos pass transistor M5 connects the drain electrode of the 6th nmos pass transistor M6 and first pole plate of charging capacitor respectively;
The grid of the 6th nmos pass transistor M6 connects clock signal clk, and the source electrode of the 6th nmos pass transistor M6 connects earth signal GND;
The forward end of diode connects supply voltage VDD, and the negative end of diode connects second pole plate of charging capacitor and the source electrode of the 7th PMOS transistor M7 respectively;
The grid of the 7th PMOS transistor M7 links to each other with the drain electrode of the 3rd PMOS transistor M3, and the drain electrode of the 7th PMOS transistor M7 all is connected the first signal Vboot with the source electrode of the 8th nmos pass transistor M8;
The grid of the 8th nmos pass transistor M8 connects supply voltage VDD, and the drain electrode of the 8th nmos pass transistor M8 links to each other with the output of inverter.
Described inverter comprises: the 8th PMOS transistor M1 and the second nmos pass transistor M2;
The grid of the 8th PMOS transistor M1 all is connected clock signal clk with the grid of the second nmos pass transistor M2, as the input of inverter;
The source electrode of the 8th PMOS transistor M1 connects supply voltage VDD;
The source electrode of the second nmos pass transistor M2 connects earth signal GND;
The drain electrode of the 8th PMOS transistor M1 links to each other with the drain electrode of the second nmos pass transistor M2, as the output of inverter.
Described bootstrapping sampling switch circuit is a semiconductor integrated circuit.
In the foregoing circuit, the drain electrode of the 8th PMOS transistor M1 links to each other with the drain electrode of the second nmos pass transistor M2, is designated as node 1; The drain electrode of the 3rd PMOS transistor M3 links to each other with the drain electrode of the 4th nmos pass transistor M4, is designated as node 2.
On the other hand, as shown in Figure 3, provide a kind of boostrap circuit, comprising:
Diode, charging capacitor, inverter, the 3rd PMOS transistor M3, the 4th nmos pass transistor M4, the 5th nmos pass transistor M5, the 6th nmos pass transistor M6, the 7th PMOS transistor M7 and the 8th nmos pass transistor M8;
The input of described inverter connects clock signal clk, and the output of described inverter connects the grid of the 3rd PMOS transistor M3 and the grid of the 4th nmos pass transistor M4 respectively;
The source electrode of the 3rd PMOS transistor M3 connects supply voltage VDD, and the source electrode of the 4th nmos pass transistor M4 connects treats sampled signal Vin, and the drain electrode of the 3rd PMOS transistor M3 links to each other with the drain electrode of the 4th nmos pass transistor M4;
The source electrode of the 5th nmos pass transistor M5 connects treats that sampled signal Vin, the grid of the 5th nmos pass transistor M5 connect the first signal Vboot, and the drain electrode of the 5th nmos pass transistor M5 connects the drain electrode of the 6th nmos pass transistor M6 and first pole plate of charging capacitor respectively;
The grid of the 6th nmos pass transistor M6 connects clock signal clk, and the source electrode of the 6th nmos pass transistor M6 connects earth signal GND;
The forward end of diode connects supply voltage VDD, and the negative end of diode connects second pole plate of charging capacitor and the source electrode of the 7th PMOS transistor M7 respectively;
The grid of the 7th PMOS transistor M7 links to each other with the drain electrode of the 3rd PMOS transistor M3, and the drain electrode of the 7th PMOS transistor M7 all is connected the first signal Vboot with the source electrode of the 8th nmos pass transistor M8;
The grid of the 8th nmos pass transistor M8 connects supply voltage VDD, and the drain electrode of the 8th nmos pass transistor M8 links to each other with the output of inverter.
Described inverter comprises: the 8th PMOS transistor M1 and the second nmos pass transistor M2;
The grid of the 8th PMOS transistor M1 all is connected clock signal clk with the grid of the second nmos pass transistor M2, as the input of inverter;
The source electrode of the 8th PMOS transistor M1 connects supply voltage VDD;
The source electrode of the second nmos pass transistor M2 connects earth signal GND;
The drain electrode of the 8th PMOS transistor M1 links to each other with the drain electrode of the second nmos pass transistor M2, as the output of inverter.
The invention solves the problem of implementation of bootstrapped switch in the sampling hold circuit, overcome the deficiency of existing bootstrapping sampling switch circuit, a kind of bootstrapping sampling switch circuit that does not need extra clock signal to promote circuit is provided, effectively reduced the area of bootstrapping sampling switch circuit, reduce the chip manufacturing cost, effectively realize the function of high speed, high-precision bootstrapping sampling switch.
The present invention uses a diode, under the control of clock signal, periodically charges to charging capacitor, and the voltage on the charging capacitor is added on the input signal, to realize the function of gate voltage bootstrapping.
The 9th metal-oxide-semiconductor that is used as switch is operated in dark linear zone (also claiming dark triode region), and at this moment metal-oxide-semiconductor satisfies condition:
V
ds＝V
gs-V
th (1)
V wherein
DsBe the drain-source voltage of metal-oxide-semiconductor, V
GsBe the gate source voltage of metal-oxide-semiconductor, V
ThBe the threshold voltage of metal-oxide-semiconductor, V
Gs-V
ThBe the overdrive voltage of metal-oxide-semiconductor, at this moment metal-oxide-semiconductor is approximate can equivalence be a resistance, its resistance R
OnBe about:
Wherein μ is the metal-oxide-semiconductor carrier mobility, C
OxBe current potential area gate oxide electric capacity,
Breadth length ratio for metal-oxide-semiconductor.
Can see that conducting resistance can be along with gate source voltage V
GsVariation and change, and the variation of conducting resistance can bring the reduction of the linearity, influences the performance of switching circuit.
In order to reach the better linearity degree, need make the gate source voltage V of metal-oxide-semiconductor
GsRemain unchanged.Generally be to give certain electric capacity charging earlier, again with voltage on the electric capacity and input signal addition, connect the grid of metal-oxide-semiconductor, input signal connects the source electrode of metal-oxide-semiconductor, and the gate source voltage of metal-oxide-semiconductor will equal the voltage on the electric capacity like this.
The present invention's sampling switch of booting comprises grid voltage boostrap circuit and the 9th nmos pass transistor M0 switch.The grid voltage boostrap circuit has CLK and two input signals of Vin, and output signal of Vout is arranged.
The present invention uses the grid voltage boostrap circuit, makes the grid voltage of the 9th nmos pass transistor M9 remain constant voltage when switch conduction, eliminates the nonlinear purpose of conducting resistance to reach.This circuit can use technologies such as CMOS, BiCMOS to realize.The present invention is applicable to the bootstrapped switch circuit of semiconductor integrated circuit, has solved the excessive problem of existing bootstrapped switch circuit area.
Among the present invention, the negative sense termination supply voltage of diode, forward termination charging capacitor.Under the control of clock signal, periodically charge, and the voltage on the charging capacitor is added on the input signal, to realize the function of gate voltage bootstrapping to charging capacitor.The voltage Vboot that connects the 9th nmos pass transistor M0 switch gate changes under the control of clock signal clk.When CLK was high level, Vboot was output as low-voltage GND; When CLK was low level, Vboot was output as the bootstrap voltage mode for the treatment of sampled signal Vin.
The present invention charges to electric capacity by diode, utilizes turn-offing certainly of diode to reach the purpose of turn-offing the charging path again.When clock signal clk was high level VDD, the voltage of node 1 was moved to low level GND by the second nmos pass transistor M2, because the grid of the 8th nmos pass transistor M8 meets VDD, was low level GND so can make Vboot.Simultaneously, the CLK of high level can make the 6th nmos pass transistor M6 conducting, with supply voltage charging capacitor is charged, and is charged to VDD-Vd, and Vd is the threshold voltage of diode.
When clock signal clk was low level GND, the voltage of node 1 was mentioned high level VDD by the 8th PMOS transistor M1.At this moment low level CLK can make the 6th nmos pass transistor M6 turn-off.The voltage of node 2 is moved to level Vin by the 4th nmos pass transistor M4.The voltage of Vin can make the 7th PMOS transistor M7 conducting, thereby Vboot is uprised, after uprising, Vboot can make the 5th nmos pass transistor M5 conducting, make Vin receive an end of charging capacitor, and Vboot receives the other end of charging capacitor, and diode D1 is oppositely ended, at this moment Vboot be treat sampled signal Vin and charging capacitor voltage VDD-Vd and, be Vin+Vdd-Vd, thereby reached the function of grid voltage bootstrapping.
Described method embodiment is corresponding with described device embodiment, the description of relevant portion gets final product among the part comparable device embodiment that does not describe in detail in method embodiment, and the description of relevant portion gets final product among the part reference method embodiment that does not describe in detail in device embodiment.
One of ordinary skill in the art will appreciate that, realize that all or part of step in the foregoing description method is to instruct relevant hardware to finish by program, described program can be stored in the computer read/write memory medium, this program is when carrying out, comprise step as above-mentioned method embodiment, described storage medium, as: magnetic disc, CD, read-only storage memory body (Read-Only Memory, ROM) or at random store memory body (Random Access Memory, RAM) etc.
In each method embodiment of the present invention; the sequence number of described each step can not be used to limit the sequencing of each step; for those of ordinary skills, under the prerequisite of not paying creative work, the priority of each step is changed also within protection scope of the present invention.
The above is a preferred implementation of the present invention; should be pointed out that for those skilled in the art, under the prerequisite that does not break away from principle of the present invention; can also make some improvements and modifications, these improvements and modifications also should be considered as protection scope of the present invention.
Claims (6)
1. a bootstrapping sampling switch circuit is characterized in that, comprising:
Boostrap circuit and the 9th nmos pass transistor;
Described boostrap circuit input clock signal CLK and treat sampled signal Vin exports the first signal Vboot; The source electrode of the 9th nmos pass transistor connects treats that sampled signal Vin, the grid of the 9th nmos pass transistor connect the described first signal Vboot, the drain electrode output secondary signal Vout of the 9th nmos pass transistor;
Described boostrap circuit comprises:
Diode, charging capacitor, inverter, the 3rd PMOS transistor, the 4th nmos pass transistor, the 5th nmos pass transistor, the 6th nmos pass transistor, the 7th PMOS transistor and the 8th nmos pass transistor;
The input of described inverter connects clock signal clk, and the output of described inverter connects the grid of transistorized grid of the 3rd PMOS and the 4th nmos pass transistor respectively;
The transistorized source electrode of the 3rd PMOS connects supply voltage VDD, and the source electrode of the 4th nmos pass transistor connects treats sampled signal Vin, and the drain electrode of the 3rd PMOS transistor drain and the 4th nmos pass transistor links to each other;
The source electrode of the 5th nmos pass transistor connects treats that sampled signal Vin, the grid of the 5th nmos pass transistor connect the first signal Vboot, and the drain electrode of the 5th nmos pass transistor connects the drain electrode of the 6th nmos pass transistor and first pole plate of charging capacitor respectively;
The grid of the 6th nmos pass transistor connects clock signal clk, and the source electrode of the 6th nmos pass transistor connects earth signal GND;
The forward end of diode connects supply voltage VDD, and the negative end of diode connects second pole plate and the transistorized source electrode of the 7th PMOS of charging capacitor respectively;
The transistorized grid of the 7th PMOS links to each other with the 3rd PMOS transistor drain, and the source electrode of the 7th PMOS transistor drain and the 8th nmos pass transistor all is connected the first signal Vboot;
The grid of the 8th nmos pass transistor connects supply voltage VDD, and the drain electrode of the 8th nmos pass transistor links to each other with the output of inverter.
2. bootstrapping sampling switch circuit according to claim 1 is characterized in that, described inverter comprises: a PMOS transistor and second nmos pass transistor;
The grid of the transistorized grid of the one PMOS and second nmos pass transistor all is connected clock signal clk, as the input of inverter;
The transistorized source electrode of the one PMOS connects supply voltage VDD;
The source electrode of second nmos pass transistor connects earth signal GND;
The drain electrode of the one PMOS transistor drain and second nmos pass transistor links to each other, as the output of inverter.
3. bootstrapping sampling switch circuit according to claim 1 is characterized in that, described bootstrapping sampling switch circuit is a semiconductor integrated circuit.
4. a boostrap circuit is characterized in that, comprising:
Diode, charging capacitor, inverter, the 3rd PMOS transistor, the 4th nmos pass transistor, the 5th nmos pass transistor, the 6th nmos pass transistor, the 7th PMOS transistor and the 8th nmos pass transistor;
The input of described inverter connects clock signal clk, and the output of described inverter connects the grid of transistorized grid of the 3rd PMOS and the 4th nmos pass transistor respectively;
The transistorized source electrode of the 3rd PMOS connects supply voltage VDD, and the source electrode of the 4th nmos pass transistor connects treats sampled signal Vin, and the drain electrode of the 3rd PMOS transistor drain and the 4th nmos pass transistor links to each other;
The source electrode of the 5th nmos pass transistor connects treats that sampled signal Vin, the grid of the 5th nmos pass transistor connect the first signal Vboot, and the drain electrode of the 5th nmos pass transistor connects the drain electrode of the 6th nmos pass transistor and first pole plate of charging capacitor respectively;
The grid of the 6th nmos pass transistor connects clock signal clk, and the source electrode of the 6th nmos pass transistor connects earth signal GND;
The forward end of diode connects supply voltage VDD, and the negative end of diode connects second pole plate and the transistorized source electrode of the 7th PMOS of charging capacitor respectively;
The transistorized grid of the 7th PMOS links to each other with the 3rd PMOS transistor drain, and the source electrode of the 7th PMOS transistor drain and the 8th nmos pass transistor all is connected the first signal Vboot;
The grid of the 8th nmos pass transistor connects supply voltage VDD, and the drain electrode of the 8th nmos pass transistor links to each other with the output of inverter.
5. boostrap circuit according to claim 4 is characterized in that, described inverter comprises: a PMOS transistor and second nmos pass transistor;
The grid of the transistorized grid of the one PMOS and second nmos pass transistor all is connected clock signal clk, as the input of inverter;
The transistorized source electrode of the one PMOS connects supply voltage VDD;
The source electrode of second nmos pass transistor connects earth signal GND;
The drain electrode of the one PMOS transistor drain and second nmos pass transistor links to each other, as the output of inverter.
6. boostrap circuit according to claim 4 is characterized in that, described boostrap circuit is a semiconductor integrated circuit.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2010102913124A CN101977046B (en) | 2010-09-25 | 2010-09-25 | Bootstrap sampling switch circuit and bootstrap circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2010102913124A CN101977046B (en) | 2010-09-25 | 2010-09-25 | Bootstrap sampling switch circuit and bootstrap circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN101977046A true CN101977046A (en) | 2011-02-16 |
| CN101977046B CN101977046B (en) | 2012-07-04 |
Family
ID=43576899
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN2010102913124A Active CN101977046B (en) | 2010-09-25 | 2010-09-25 | Bootstrap sampling switch circuit and bootstrap circuit |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN101977046B (en) |
Cited By (18)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102270981A (en) * | 2011-06-28 | 2011-12-07 | 上海宏力半导体制造有限公司 | Sampling switch circuit |
| CN102592655A (en) * | 2011-11-30 | 2012-07-18 | 中国科学院微电子研究所 | Bootstrap precharged fast amplitude-limiting word line biasing circuit |
| CN102832919A (en) * | 2012-09-13 | 2012-12-19 | 中国科学院半导体研究所 | Grid voltage bootstrapped switch circuit |
| CN103095302A (en) * | 2012-12-19 | 2013-05-08 | 天津大学 | Sampling holding circuit applied to high-speed high-precision circuit |
| CN105049048A (en) * | 2015-09-10 | 2015-11-11 | 中国电子科技集团公司第二十四研究所 | Sampling NMOS tube and generation method thereof, voltage bootstrapping sampling switch and analogue-digital converter |
| CN106411302A (en) * | 2015-07-28 | 2017-02-15 | 无锡华润上华半导体有限公司 | Switching control circuit |
| WO2017190652A1 (en) * | 2016-05-04 | 2017-11-09 | The Hong Kong University Of Science And Technology | Power device with integrated gate driver |
| WO2018036475A1 (en) * | 2016-08-26 | 2018-03-01 | 无锡华润上华科技有限公司 | Clock voltage step-up circuit |
| CN107896110A (en) * | 2017-12-15 | 2018-04-10 | 上海贝岭股份有限公司 | Boot sampling switch circuit, sampling hold circuit and time-interleaved type ADC |
| CN108155899A (en) * | 2017-12-25 | 2018-06-12 | 电子科技大学 | A kind of boot-strapped switch circuit |
| CN108599751A (en) * | 2018-04-27 | 2018-09-28 | 中国电子科技集团公司第二十四研究所 | A kind of boostrap circuit |
| CN108777579A (en) * | 2018-09-07 | 2018-11-09 | 广西师范大学 | Boot-strapped switch |
| CN110535471A (en) * | 2018-05-23 | 2019-12-03 | 联发科技股份有限公司 | Boostrap circuit and relevant analog to digital conversion circuit |
| CN110915137A (en) * | 2017-07-14 | 2020-03-24 | 弗劳恩霍夫应用研究促进协会 | Switching device for switching an analog electrical input signal |
| CN111614356A (en) * | 2020-04-22 | 2020-09-01 | 北方工业大学 | Grid voltage bootstrap sampling circuit |
| CN112764011A (en) * | 2020-12-25 | 2021-05-07 | 武汉万集信息技术有限公司 | Output circuit and method compatible with source type and drain type interface circuit and laser radar |
| CN113206659A (en) * | 2021-05-10 | 2021-08-03 | 西安电子科技大学重庆集成电路创新研究院 | High-speed high-linearity grid voltage bootstrap switch for pipeline ADC |
| CN116027840A (en) * | 2023-02-21 | 2023-04-28 | 成都明夷电子科技有限公司 | Adjusting circuit, resistor and electronic equipment |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20080218141A1 (en) * | 2007-02-08 | 2008-09-11 | Sao-Hung Lu | Circuit for charging a bootstrap capacitor in a voltage converter |
| US7538531B2 (en) * | 2006-02-07 | 2009-05-26 | Panasonic Corporation | Drive circuit and switching regulator comprising the same |
| CN101540600A (en) * | 2009-04-09 | 2009-09-23 | 复旦大学 | Double bootstrapped switch applied in switching capacitive circuit |
| CN101577545A (en) * | 2008-05-07 | 2009-11-11 | 中国科学院电子学研究所 | Dual bootstrap and voltage compensation technology-based A/D converter sampling switch |
-
2010
- 2010-09-25 CN CN2010102913124A patent/CN101977046B/en active Active
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7538531B2 (en) * | 2006-02-07 | 2009-05-26 | Panasonic Corporation | Drive circuit and switching regulator comprising the same |
| US20080218141A1 (en) * | 2007-02-08 | 2008-09-11 | Sao-Hung Lu | Circuit for charging a bootstrap capacitor in a voltage converter |
| CN101577545A (en) * | 2008-05-07 | 2009-11-11 | 中国科学院电子学研究所 | Dual bootstrap and voltage compensation technology-based A/D converter sampling switch |
| CN101540600A (en) * | 2009-04-09 | 2009-09-23 | 复旦大学 | Double bootstrapped switch applied in switching capacitive circuit |
Cited By (37)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102270981A (en) * | 2011-06-28 | 2011-12-07 | 上海宏力半导体制造有限公司 | Sampling switch circuit |
| CN102592655A (en) * | 2011-11-30 | 2012-07-18 | 中国科学院微电子研究所 | Bootstrap precharged fast amplitude-limiting word line biasing circuit |
| CN102592655B (en) * | 2011-11-30 | 2014-01-29 | 中国科学院微电子研究所 | Bootstrap precharged fast amplitude-limiting word line biasing circuit |
| CN102832919A (en) * | 2012-09-13 | 2012-12-19 | 中国科学院半导体研究所 | Grid voltage bootstrapped switch circuit |
| CN102832919B (en) * | 2012-09-13 | 2014-08-20 | 中国科学院半导体研究所 | Grid voltage bootstrapped switch circuit |
| CN103095302A (en) * | 2012-12-19 | 2013-05-08 | 天津大学 | Sampling holding circuit applied to high-speed high-precision circuit |
| CN103095302B (en) * | 2012-12-19 | 2016-04-13 | 天津大学 | A kind of sampling hold circuit being applied to high-speed, high precision circuit |
| CN106411302A (en) * | 2015-07-28 | 2017-02-15 | 无锡华润上华半导体有限公司 | Switching control circuit |
| US10236876B2 (en) | 2015-07-28 | 2019-03-19 | Csmc Technologies Fab2 Co., Ltd. | Switch control circuit with booster |
| CN106411302B (en) * | 2015-07-28 | 2019-03-15 | 无锡华润上华科技有限公司 | ON-OFF control circuit |
| CN105049048B (en) * | 2015-09-10 | 2018-07-20 | 中国电子科技集团公司第二十四研究所 | Sample NMOS tube and its generation method, voltage bootstrapping sampling switch and analog-digital converter |
| CN105049048A (en) * | 2015-09-10 | 2015-11-11 | 中国电子科技集团公司第二十四研究所 | Sampling NMOS tube and generation method thereof, voltage bootstrapping sampling switch and analogue-digital converter |
| WO2017190652A1 (en) * | 2016-05-04 | 2017-11-09 | The Hong Kong University Of Science And Technology | Power device with integrated gate driver |
| US10404251B2 (en) | 2016-05-04 | 2019-09-03 | The Hong Kong University Of Science And Technology | Power device with integrated gate driver |
| WO2018036475A1 (en) * | 2016-08-26 | 2018-03-01 | 无锡华润上华科技有限公司 | Clock voltage step-up circuit |
| US10659040B2 (en) | 2016-08-26 | 2020-05-19 | Csmc Technologies Fab2 Co., Ltd. | Clock voltage step-up circuit |
| CN107786187B (en) * | 2016-08-26 | 2020-04-07 | 无锡华润上华科技有限公司 | Clock voltage boosting circuit |
| CN107786187A (en) * | 2016-08-26 | 2018-03-09 | 无锡华润上华科技有限公司 | Clock voltage lifts circuit |
| CN110915137A (en) * | 2017-07-14 | 2020-03-24 | 弗劳恩霍夫应用研究促进协会 | Switching device for switching an analog electrical input signal |
| CN110915137B (en) * | 2017-07-14 | 2023-09-08 | 弗劳恩霍夫应用研究促进协会 | Switching device for switching an analog electrical input signal |
| CN107896110A (en) * | 2017-12-15 | 2018-04-10 | 上海贝岭股份有限公司 | Boot sampling switch circuit, sampling hold circuit and time-interleaved type ADC |
| CN107896110B (en) * | 2017-12-15 | 2020-11-10 | 上海贝岭股份有限公司 | Bootstrap sampling switch circuit, sample-and-hold circuit, and time-interleaved ADC |
| CN108155899B (en) * | 2017-12-25 | 2020-07-31 | 电子科技大学 | Grid voltage bootstrap switch circuit |
| CN108155899A (en) * | 2017-12-25 | 2018-06-12 | 电子科技大学 | A kind of boot-strapped switch circuit |
| CN108599751A (en) * | 2018-04-27 | 2018-09-28 | 中国电子科技集团公司第二十四研究所 | A kind of boostrap circuit |
| CN108599751B (en) * | 2018-04-27 | 2021-10-08 | 中国电子科技集团公司第二十四研究所 | Bootstrap circuit |
| CN110535471A (en) * | 2018-05-23 | 2019-12-03 | 联发科技股份有限公司 | Boostrap circuit and relevant analog to digital conversion circuit |
| CN110535471B (en) * | 2018-05-23 | 2023-05-30 | 联发科技股份有限公司 | Bootstrap circuit and related analog-to-digital conversion circuit |
| CN108777579A (en) * | 2018-09-07 | 2018-11-09 | 广西师范大学 | Boot-strapped switch |
| CN108777579B (en) * | 2018-09-07 | 2023-08-11 | 广西师范大学 | Grid voltage bootstrapping switch |
| CN111614356A (en) * | 2020-04-22 | 2020-09-01 | 北方工业大学 | Grid voltage bootstrap sampling circuit |
| CN111614356B (en) * | 2020-04-22 | 2023-05-02 | 北方工业大学 | Grid voltage bootstrapping sampling circuit |
| CN112764011A (en) * | 2020-12-25 | 2021-05-07 | 武汉万集信息技术有限公司 | Output circuit and method compatible with source type and drain type interface circuit and laser radar |
| CN113206659B (en) * | 2021-05-10 | 2022-05-10 | 西安电子科技大学重庆集成电路创新研究院 | High-speed high-linearity grid voltage bootstrap switch for pipeline ADC |
| CN113206659A (en) * | 2021-05-10 | 2021-08-03 | 西安电子科技大学重庆集成电路创新研究院 | High-speed high-linearity grid voltage bootstrap switch for pipeline ADC |
| CN116027840A (en) * | 2023-02-21 | 2023-04-28 | 成都明夷电子科技有限公司 | Adjusting circuit, resistor and electronic equipment |
| CN116027840B (en) * | 2023-02-21 | 2023-05-23 | 成都明夷电子科技有限公司 | Adjusting circuit, resistor and electronic equipment |
Also Published As
| Publication number | Publication date |
|---|---|
| CN101977046B (en) | 2012-07-04 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN101977046B (en) | Bootstrap sampling switch circuit and bootstrap circuit | |
| CN110149111A (en) | A kind of bootstrap switch circuit and its control method | |
| CN103152029A (en) | Flexible low power slew-rate controlled output buffer | |
| CN103532534A (en) | Grid voltage bootstrapping switch circuit | |
| CN101001085B (en) | Signal sampling hold circuit | |
| CN112383292B (en) | High-speed high-linearity grid voltage bootstrapping switch circuit | |
| CN108777579B (en) | Grid voltage bootstrapping switch | |
| CN105187039A (en) | CMOS gate voltage bootstrapping switch circuit | |
| CN111900986B (en) | Follow-up hold switch circuit | |
| CN112671382B (en) | Grid voltage bootstrapping switch circuit | |
| CN112953503B (en) | High-linearity grid voltage bootstrap switch circuit | |
| CN102332921A (en) | Successive approximation type analog to digital converter applicable to automatic gain control loop | |
| EP0689736A1 (en) | Semiconductor device | |
| CN209748522U (en) | Voltage level shifter | |
| CN113726321A (en) | Bootstrap switch circuit and analog-to-digital converter | |
| US4609836A (en) | CMOS transmission circuit | |
| CN102571091B (en) | Analog-to-digital converter and electronic equipment | |
| CN207200679U (en) | A kind of earth leakage protective type bootstrapping sampling switch circuit | |
| CN101944847B (en) | Bootstrap switch circuit | |
| CN111614356B (en) | Grid voltage bootstrapping sampling circuit | |
| CN109818485A (en) | Reconfigurable low-power and low-power grid guide circuit | |
| CN104883052A (en) | Lifting capacitance circuit and charge pump | |
| CN104539292A (en) | Low-voltage high-speed sampling holding circuit | |
| JPH0763138B2 (en) | Preload circuit for logic data transmission bus | |
| CN110690900B (en) | Time domain ADC full-swing front-end circuit |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| ASS | Succession or assignment of patent right |
Owner name: ZHU ZHANGMING Free format text: FORMER OWNER: XIDIAN UNIVERSITY Effective date: 20130129 |
|
| C41 | Transfer of patent application or patent right or utility model | ||
| TR01 | Transfer of patent right |
Effective date of registration: 20130129 Address after: Xi'an City, Shaanxi province Taibai Road 710071 No. 2 Patentee after: Zhu Zhangming Address before: Xi'an City, Shaanxi province Taibai Road 710071 No. 2 Patentee before: Xidian University |
|
| ASS | Succession or assignment of patent right |
Owner name: KUNSHAN QIDA MICROELECTRONICS CO., LTD. Free format text: FORMER OWNER: ZHU ZHANGMING Effective date: 20130314 |
|
| C41 | Transfer of patent application or patent right or utility model | ||
| COR | Change of bibliographic data |
Free format text: CORRECT: ADDRESS; FROM: 710071 XI AN, SHAANXI PROVINCE TO: 215300 SUZHOU, JIANGSU PROVINCE |
|
| TR01 | Transfer of patent right |
Effective date of registration: 20130314 Address after: High tech Zone Kunshan city Jiangsu province 215300 Dengyun Road No. 268, room 508 Patentee after: KUNSHAN QIDA MICROELECTRONIC CO., LTD. Address before: Xi'an City, Shaanxi province Taibai Road 710071 No. 2 Patentee before: Zhu Zhangming |