CN102592655A - Bootstrap precharged fast amplitude-limiting word line biasing circuit - Google Patents
Bootstrap precharged fast amplitude-limiting word line biasing circuit Download PDFInfo
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- CN102592655A CN102592655A CN2011103896559A CN201110389655A CN102592655A CN 102592655 A CN102592655 A CN 102592655A CN 2011103896559 A CN2011103896559 A CN 2011103896559A CN 201110389655 A CN201110389655 A CN 201110389655A CN 102592655 A CN102592655 A CN 102592655A
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- nmos pipe
- preliminary filling
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Abstract
The invention provides a bootstrap precharged fast amplitude-limiting word line biasing circuit, which comprises a reference voltage generation circuit, a static clamping circuit supplying initial setting potential, a precharge control signal generation circuit receiving enable signals, a boost voltage generation circuit supplying Vboost, a N-channel metal oxide semiconductor (NMOS) transistor M1 serving as an output transistor, an enable control P-channel Metal Oxide Semiconductor (PMOS) transistor M2 serving as receiving enable signals, a precharge control NMOS transistor M3 and a grounded switch NMOS transistor M4. The Vboost is applied to a capacitor Cb of the MNOS transistor and a phase inverter I5. According to the bootstrap precharged fast amplitude-limiting word line biasing circuit, a reference voltage of a load supplied by the static clamping circuit can be boosted rapidly to a predetermined voltage value. Amplitude-limiting precharge is utilized, so that over-charge is avoided.
Description
Technical field
The present invention relates to the memory circuitry technical field, the precharge quick amplitude limit word line biasing circuit of particularly a kind of bootstrapping.
Background technology
The word line biasing circuit is the circuit that provides burning voltage to setover to word line in the memory circuitry.The tradition biasing circuit is by a burning voltage control efferent duct, and enable signal is controlled the shutoff or the unlatching of output branch road, and efferent duct strengthens output branch current fan-out capability during unlatching, thereby reaches the effect that predetermined bias is provided to load.Conventional word line biasing adopts a biasing circuit that reference voltage is provided, and improves load capacity through the export structure that source class is followed.But the fan-out capability of this structure is limited, can not satisfy the requirement that biasing circuit starts fast,
Summary of the invention
Technical matters to be solved by this invention provides a kind of precharge quick amplitude limit word line biasing circuit of bootstrapping of preliminary filling safely and fast.
According to an aspect of the present invention; Provide a kind of precharge quick amplitude limit word line biasing circuit of booting comprise reference voltage generating circuit, provide initial set current potential static clamping circuit, receive enable signal the preliminary filling control signal generation circuit, the boost voltage generation circuit of voltage Vboost is provided, as the NMOS pipe M1 of efferent duct, receive the switch NMOS pipe M4 that enables to control PMOS pipe M2, preliminary filling control NMOS pipe M3, ground connection of enable signal, capacitor C b and phase inverter I5;
Said reference voltage generating circuit is connected with the grid of said NMOS pipe M1 with said capacitor C b respectively;
The output terminal of said preliminary filling control signal generation circuit is connected with the grid of said preliminary filling control NMOS pipe M3, also is connected with the grid of the switch NMOS pipe M4 of said ground connection through phase inverter I5; The source electrode of said preliminary filling control NMOS pipe M3 is connected with said boost voltage generation circuit;
Said capacitor C b one end is connected between the grid of said reference voltage generating circuit and said NMOS pipe M1, and the other end is connected with the drain electrode that said preliminary filling control NMOS manages M3 with the drain electrode of the switch NMOS pipe M4 of said ground connection respectively;
The drain electrode of said NMOS pipe M1 enables to control the drain electrode that PMOS manages M2 and is connected with said, and source electrode is connected with said static clamping circuit; Be provided with the back output potential that powers between the drain electrode of said NMOS pipe M1 and the said static clamping circuit;
The said source electrode that enables to control PMOS pipe M2 meets power vd D.
Further, said reference voltage generating circuit comprises current source I1 and resistance R 1; Said current source I1 is through said resistance R 1 ground connection, and grid and the said capacitor C b of said NMOS pipe M1 are parallelly connected with said current source I1 and said resistance R 1 respectively.
Further, said static clamping circuit comprises diode I6, I7; Said diode I7 one end ground connection, the other end is connected with the source electrode of said NMOS pipe M1 through said diode I6.
Further, said preliminary filling control signal generation circuit comprises phase inverter I2, I3, Sheffer stroke gate I4, capacitor C 1;
Said phase inverter I2 is parallelly connected with the input end of said Sheffer stroke gate I4, said phase inverter I3 respectively; Said I3 is parallelly connected with another input end, the said capacitor C 1 of said Sheffer stroke gate I4 respectively; Said capacitor C 1 ground connection; The output terminal of said Sheffer stroke gate I4 is connected with grid, the said phase inverter I5 of said preliminary filling control NMOS pipe M3 respectively.
Further, said boost voltage generation circuit comprises PMOS pipe M5 and current source I2;
The grid of said PMOS pipe M5 links to each other with drain electrode;
The grid of said PMOS pipe M5 is connected with the source electrode of said preliminary filling control NMOS pipe M3 with said current source I2 respectively with drain electrode; Said current source I2 ground connection; The source electrode of said PMOS pipe M5 links to each other with power vd D.
The precharge quick amplitude limit word line biasing circuit of bootstrapping provided by the invention is with preliminary filling control signal generation circuit control preliminary filling control tube M3; The voltage Vboost that the boost voltage generation circuit is produced with electric capacity Cb is loaded into the grid that output NMOS manages M1; Can fast load be elevated to predetermined magnitude of voltage from the given reference voltage of static clamping circuit; And because the amplitude limit preliminary filling that adopts has prevented the generation of the situation of overcharging.
Description of drawings
The structured flowchart of the precharge quick amplitude limit word line biasing circuit of bootstrapping that Fig. 1 provides for the embodiment of the invention;
The circuit theory synoptic diagram of the precharge quick amplitude limit word line biasing circuit of bootstrapping that Fig. 2 provides for the embodiment of the invention.
Fig. 3 is the waveform synoptic diagram of main signal in the circuit shown in Figure 2, and wherein, ENb is an enable signal, and PC is a pulse signal, and VB is the voltage signal that B is ordered, and VA is the voltage signal that A is ordered.
Embodiment
Referring to Fig. 1; The precharge quick amplitude limit word line biasing circuit of the bootstrapping that the embodiment of the invention provides comprise reference voltage generating circuit 10, the static clamping circuit 20 of initial set current potential be provided, receive enable signal preliminary filling control signal generation circuit 30, the boost voltage generation circuit 40 of voltage Vboost is provided, as the NMOS pipe M1 of efferent duct, receive the switch NMOS pipe M4, capacitor C b and the phase inverter I5 that enable to control PMOS pipe M2, preliminary filling control NMOS pipe M3, ground connection of enable signal.Reference voltage generating circuit 10 is used to provide a stable voltage Vref.Reference voltage generating circuit 10 is connected with the grid of NMOS pipe M1 with capacitor C b respectively.Preliminary filling control signal generation circuit 30 is controlled by enable signal ENb, and a pulse signal PC is provided.The output terminal of preliminary filling control signal generation circuit 30 is connected with the grid of preliminary filling control NMOS pipe M3, also is connected with the grid of the switch NMOS pipe M4 of ground connection through phase inverter I5.The source electrode of preliminary filling control NMOS pipe M3 is connected with boost voltage generation circuit 40.Capacitor C b one end is connected between the grid of reference voltage generating circuit 10 and NMOS pipe M1, and the other end is connected with the drain electrode that preliminary filling control NMOS manages M3 with the drain electrode of the switch NMOS pipe M4 of ground connection respectively.The drain electrode of NMOS pipe M1 with enable to control the drain electrode that PMOS manages M2 and be connected, source electrode is connected with static clamping circuit 20; Be provided with the back output potential A that powers between the drain electrode of NMOS pipe M1 and the static clamping circuit 20, to current potential A an initial set voltage be provided after static clamping circuit 20 powers on.The source electrode that enables to control PMOS pipe M2 meets power vd D.
Below in conjunction with Fig. 2 the structure of the precharge quick amplitude limit word line biasing circuit of booting is specified further.Reference voltage generating circuit 10 comprises current source I1 and resistance R 1; Current source I1 is through resistance R 1 ground connection, and grid and the capacitor C b of NMOS pipe M1 are connected in the B point with current source I1 and resistance R 1 respectively.
Preliminary filling control signal generation circuit 30 comprises phase inverter I2, I3, Sheffer stroke gate I4, capacitor C 1.Phase inverter I2 is parallelly connected with an input end, the phase inverter I3 of Sheffer stroke gate I4 respectively; I3 is parallelly connected with another input end, the capacitor C 1 of Sheffer stroke gate I4 respectively; Capacitor C 1 ground connection; The output terminal of Sheffer stroke gate I4 is connected with grid, the phase inverter I5 of preliminary filling control NMOS pipe M3 respectively.
Boost voltage generation circuit 40 comprises PMOS pipe M5 and current source I2.The grid of PMOS pipe M5 links to each other with drain electrode; The grid of PMOS pipe M5 is connected with the source electrode of preliminary filling control NMOS pipe M3 with current source I2 respectively with drain electrode; Current source I2 ground connection; The source electrode of PMOS pipe M5 links to each other with power vd D.
Preliminary filling control NMOS pipe M3 is controlled by pulse signal PC, and voltage Vboost is delivered to capacitor C 1.Grounding switch NMOS pipe M4 is controlled by signal PC, with 1 one sections ground connection of capacitor C.The character that capacitor C b can not suddenly change because of effect and the electric capacity voltage difference of voltage Vboost is loaded into the B point with Vboost.
Reference voltage generating circuit 10 provides a stable voltage Vref grid to NMOS pipe M1, makes the conducting of NMOS pipe M1 pipe.Static clamping circuit 20 provides an initial set voltage, and the back output potential A that powers on is placed in a suitable original state.Enable signal ENb is connected on the grid of PMOS pipe M2, the switch of control PMOS pipe M2, the switch of control circuit output.Under the triggering of enable signal ENb; Preliminary filling control signal generation circuit 30 produces a pulse signal PC and opens preliminary filling control tube M3; (the designature PCb control NMOS pipe M4 of signal PC pulse signal, effect is to the capacity earth discharge) is so preliminary filling control tube M3 is added to voltage Vboost the lower end of capacitor C b.Because electric capacity has the characteristic that the voltage difference is not suddenlyd change; Can be with the voltage lifting of going up step Vboost and be added to the B point; Be VB=Vref+Vboost, make the gate source voltage Vgs of NMOS pipe M1 increase Vboost during this preliminary filling, strengthened the electric current fan-out capability of M1; Make M1 carry out big pre-charge to the A point during this period, quicken the A point voltage near predetermined magnitude of voltage; M3 turn-offs behind the end-of-pulsing, through the less quiescent current that PMOS manages M2, NMOS pipe M1 circulation A is continued more slowly charging from power vd D, up to reaching predetermined voltage.The capacitor C b of enough capacity, suitable Vboost value and suitable pulse signal PC pulsewidth can limit A point preliminary filling to magnitude of voltage be no more than the upper voltage limit of being scheduled to.
Below in conjunction with each main signal schematic representation shown in Figure 3, quick amplitude limit preliminary filling process is described.Static clamping circuit work after circuit powers on, the A point voltage is initial static clamp voltage V1; T1 constantly pulse signal PC opens preliminary filling control NMOS and manages M3 between high period, voltage Vboost is added to the end of capacitor C b, and electric capacity has not mutability of voltage difference; Voltage Vboost is loaded into the B point; The B point links to each other with the grid of NMOS pipe M1, and the gate voltage of M1 rises, and quickens A point preliminary filling; Make the A point voltage reach a value V2 fast, last till t2 (RS section among the figure) constantly near predetermined voltage; Preliminary filling control tube M3 turn-offs subsequently; Ground connection control tube M4 opens; Capacity earth discharge (PQ section among the figure; VB voltage returns to Vref gradually), from the flow through less electric current of PMOS pipe M2, NMOS pipe M1 of power vd D A is charged, continue rising A point voltage and finally reach predetermined magnitude of voltage V3 (ST section among the figure).
The precharge quick amplitude limit word line biasing circuit of bootstrapping provided by the invention; With preliminary filling control signal generation circuit control preliminary filling control tube M3; The voltage Vboost that the boost voltage generation circuit is produced with electric capacity Cb is loaded into the grid that output NMOS manages M1, can fast load be elevated to predetermined magnitude of voltage from the given reference voltage of static clamping circuit, saves pre-charging time; And since the amplitude limit preliminary filling that adopts, the generation of the situation of overcharging when preventing rapid charge.
It should be noted last that; Above embodiment is only unrestricted in order to technical scheme of the present invention to be described; Although with reference to instance the present invention is specified, those of ordinary skill in the art should be appreciated that and can make amendment or be equal to replacement technical scheme of the present invention; And not breaking away from the spirit and the scope of technical scheme of the present invention, it all should be encompassed in the middle of the claim scope of the present invention.
Claims (5)
1. the precharge quick amplitude limit word line biasing circuit of bootstrapping is characterized in that, comprising:
Reference voltage generating circuit, provide initial set current potential static clamping circuit, receive enable signal the preliminary filling control signal generation circuit, the boost voltage generation circuit of voltage Vboost is provided, as the NMOS pipe M1 of efferent duct, receive the switch NMOS pipe M4 that enables to control PMOS pipe M2, preliminary filling control NMOS pipe M3, ground connection of enable signal, said voltage Vboost is loaded into capacitor C b and the phase inverter I5 of said NMOS pipe M1;
Said reference voltage generating circuit is connected with the grid of said NMOS pipe M1 with said capacitor C b respectively;
The output terminal of said preliminary filling control signal generation circuit is connected with the grid of said preliminary filling control NMOS pipe M3, also is connected with the grid of the switch NMOS pipe M4 of said ground connection through phase inverter I5; The source electrode of said preliminary filling control NMOS pipe M3 is connected with said boost voltage generation circuit;
Said capacitor C b one end is connected between the grid of said reference voltage generating circuit and said NMOS pipe M1, and the other end is connected with the drain electrode that said preliminary filling control NMOS manages M3 with the drain electrode of the switch NMOS pipe M4 of said ground connection respectively;
The drain electrode of said NMOS pipe M1 enables to control the drain electrode that PMOS manages M2 and is connected with said, and source electrode is connected with said static clamping circuit; Be provided with the back output potential that powers between the drain electrode of said NMOS pipe M1 and the said static clamping circuit;
The said source electrode that enables to control PMOS pipe M2 meets power vd D.
2. biasing circuit according to claim 1 is characterized in that, said reference voltage generating circuit comprises:
Current source I1 and resistance R 1; Said current source I1 is through said resistance R 1 ground connection, and grid and the said capacitor C b of said NMOS pipe M1 are parallelly connected with said current source I1 and said resistance R 1 respectively.
3. biasing circuit according to claim 1 is characterized in that, said static clamping circuit comprises:
Diode I6, I7; Said diode I7 one end ground connection, the other end is connected with the source electrode of said NMOS pipe M1 through said diode I6.
4. biasing circuit according to claim 1 is characterized in that, said preliminary filling control signal generation circuit comprises:
Phase inverter I2, I3, Sheffer stroke gate I4, capacitor C 1;
Said phase inverter I2 is parallelly connected with the input end of said Sheffer stroke gate I4, said phase inverter I3 respectively; Said I3 is parallelly connected with another input end, the said capacitor C 1 of said Sheffer stroke gate I4 respectively; Said capacitor C 1 ground connection; The output terminal of said Sheffer stroke gate I4 is connected with grid, the said phase inverter I5 of said preliminary filling control NMOS pipe M3 respectively.
5. biasing circuit according to claim 1 is characterized in that, said boost voltage generation circuit comprises:
PMOS pipe M5 and current source I2;
The grid of said PMOS pipe M5 links to each other with drain electrode;
The grid of said PMOS pipe M5 is connected with the source electrode of said preliminary filling control NMOS pipe M3 with said current source I2 respectively with drain electrode; Said current source I2 ground connection; The source electrode of said PMOS pipe M5 links to each other with power vd D.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201110389655.9A CN102592655B (en) | 2011-11-30 | 2011-11-30 | Bootstrap precharged fast amplitude-limiting word line biasing circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201110389655.9A CN102592655B (en) | 2011-11-30 | 2011-11-30 | Bootstrap precharged fast amplitude-limiting word line biasing circuit |
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| Publication Number | Publication Date |
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| CN102592655A true CN102592655A (en) | 2012-07-18 |
| CN102592655B CN102592655B (en) | 2014-01-29 |
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| Application Number | Title | Priority Date | Filing Date |
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| CN201110389655.9A Active CN102592655B (en) | 2011-11-30 | 2011-11-30 | Bootstrap precharged fast amplitude-limiting word line biasing circuit |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110661401A (en) * | 2018-06-29 | 2020-01-07 | 戴泺格半导体股份有限公司 | Bootstrap capacitor for charging switching power converter |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1106550A (en) * | 1993-11-09 | 1995-08-09 | 三星电子株式会社 | Word line driving circuit of a semiconductor memory device |
| US5579268A (en) * | 1993-04-06 | 1996-11-26 | Samsung Electronics Co., Ltd. | Semiconductor memory device capable of driving word lines at high speed |
| CN1213139A (en) * | 1997-09-19 | 1999-04-07 | 西门子公司 | Apparatus and method for high-speed wordline driving with low area overheat |
| CN101977046A (en) * | 2010-09-25 | 2011-02-16 | 西安电子科技大学 | Bootstrap sampling switch circuit and bootstrap circuit |
-
2011
- 2011-11-30 CN CN201110389655.9A patent/CN102592655B/en active Active
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5579268A (en) * | 1993-04-06 | 1996-11-26 | Samsung Electronics Co., Ltd. | Semiconductor memory device capable of driving word lines at high speed |
| CN1106550A (en) * | 1993-11-09 | 1995-08-09 | 三星电子株式会社 | Word line driving circuit of a semiconductor memory device |
| CN1213139A (en) * | 1997-09-19 | 1999-04-07 | 西门子公司 | Apparatus and method for high-speed wordline driving with low area overheat |
| CN101977046A (en) * | 2010-09-25 | 2011-02-16 | 西安电子科技大学 | Bootstrap sampling switch circuit and bootstrap circuit |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110661401A (en) * | 2018-06-29 | 2020-01-07 | 戴泺格半导体股份有限公司 | Bootstrap capacitor for charging switching power converter |
| CN110661401B (en) * | 2018-06-29 | 2022-08-05 | 戴泺格半导体股份有限公司 | Bootstrap capacitor for charging switching power converter |
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| Publication number | Publication date |
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| CN102592655B (en) | 2014-01-29 |
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