CN103824597A - Memory as well as readout circuit and reading method of memory cell - Google Patents
Memory as well as readout circuit and reading method of memory cell Download PDFInfo
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- CN103824597A CN103824597A CN201410083749.7A CN201410083749A CN103824597A CN 103824597 A CN103824597 A CN 103824597A CN 201410083749 A CN201410083749 A CN 201410083749A CN 103824597 A CN103824597 A CN 103824597A
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Abstract
The invention provides a memory as well as a readout circuit and a reading method of a memory cell. The readout circuit of the memory cell comprises a first PMOS (positive channel metal oxide semiconductor) tube, a pre-charging unit and a comparing unit, wherein grids of the first PMOS tube are suitable for inputting of an on-off control signal, and a drain electrode of the first PMOS tube is coupled with a drain electrode of the memory cell; the pre-charging unit is used for charging a source electrode of the first PMOS tube to pre-charging voltage when receiving a pre-charging signal; and when receiving an enable signal, the comparing unit is used for comprising first reference voltage with the source electrode voltage of the first PMOS tube and outputting data stored in the memory cell according to a comparison result, wherein the pre-charging voltage is larger than the first reference voltage, and the first reference voltage is larger than threshold voltage of the first PMOS tube. According to the memory as well as the readout circuit and the reading method of the memory cell, power consumption for reading the memory cell is reduced.
Description
Technical field
The present invention relates to memory technology field, particularly the reading circuit of a kind of storer, storage unit and read method.
Background technology
EEPROM (Electrically Erasable Programmable Read Only Memo) (EEPROM, Electrically Erasable Programmable Read-Only Memory) be a kind of take byte as minimal modifications unit, the semiconductor memory apparatus that can repeatedly make carbon copies by electronics mode.Compare EPROM (Erasable Programmable Read Only Memory) (EPROM, Erasable Programmable Read-Only Memory), EEPROM does not need to irradiate with ultraviolet ray, do not need to take off yet, just can use specific voltage, the information of erasing on chip, to write new data.Due to the excellent in performance of EEPROM and on line operation facility, it is widely used in BIOS chip and the flash chip that need to often wipe, and progressively Substitute For Partial has power-off to retain the random access memory (RAM needing, Random Access Memory) chip, the hard disk function that even replaces part, becomes 21st century two kinds of memory technologies the most frequently used and with fastest developing speed with high-speed RAM.
Fig. 1 is the cross-sectional view of existing a kind of EEPROM storage unit.With reference to figure 1, described storage unit comprises: substrate 100; Be positioned at the target 103 of described substrate 100 tops; Be symmetrically distributed in the first bank bit and second bank bit of described target 103 both sides.Wherein, described the first bank bit comprises drain electrode 101, the first control grid 104 and the first floating boom 105; The second bank bit comprises source electrode 102, the second control grid 106 and the second floating boom 107.Described drain electrode 101 and described source electrode 102 are positioned at described substrate 100 inside, and described first controls grid 104, described the first floating boom 105, described the second control grid 106 and described the second floating boom 107 is positioned at described substrate 100 tops.As a rule, while adopting the storage unit stores data shown in Fig. 1, only use bank bit storage data in described the first bank bit and described the second bank bit, another bank bit is as for subsequent use.
Multiple storage unit are as shown in Figure 1 arranged in array and form EEPROM storage array, and control grid, target, source electrode and the drain electrode of each storage unit are connected to respectively controls grid line, word line, source line and bit line.By described control grid line, word line, source line and bit line are applied to different operating voltages, realize read operation, write operation and erase operation to described storage unit.To adopt described the first bank bit storage data, described the second bank bit as for subsequent use as example, when described storage unit is carried out to write operation, be by the first floating boom 105 described in electronic injection, what carry out reading after write operation is binary data " 0 "; When described storage unit is carried out to erase operation, be the electronics that discharges storage in described the first floating boom 105, what carry out reading after erase operation is binary data " 1 ".
Fig. 2 is the structural representation that adopts existing a kind of reading circuit to read the storage unit shown in Fig. 1.With reference to figure 2, take reading cells M20 as example, first of described storage unit M20 controls grid and connects the first control grid line CG1, second of described storage unit M20 controls grid and connects the second control grid line CG2, the target connective word line WL of described storage unit M20, the source electrode of described storage unit M20 connects source line SL, and the drain electrode of described storage unit M20 connects bit line BL.Described reading circuit comprises NMOS pipe N1, a reference current source Ir, voltage comparator Comp, amplifier A1 and the 2nd NMOS pipe N2.
Particularly, one end of described reference current source Ir is suitable for connecting the power supply Vdd of described reading circuit 12, and the other end of described reference current source Ir connects the drain electrode of first input end and described the 2nd NMOS pipe N2 of described voltage comparator Comp; The second input end of described voltage comparator Comp is suitable for input reference voltage Vr, and the output terminal of described voltage comparator Comp is suitable for exporting the data Dout of described storage unit M20 storage; The grid of described the 2nd NMOS pipe N2 connects the output terminal of described amplifier A1, and the source electrode of described the 2nd NMOS pipe N2 connects the drain electrode of input end and a described NMOS pipe N1 of described amplifier A1; The grid of a described NMOS pipe N1 is suitable for input switch control signal sel, and the drain electrode of a described NMOS pipe N1 couples the drain electrode of described storage unit M20, i.e. the drain electrode of a described NMOS pipe N1 connects the drain electrode of described storage unit M20 by described bit line BL.
While reading described storage unit M20, apply first by described word line WL to the target of described storage unit M20 and read voltage, controlling grid line CG1 and described second by described first controls grid line CG2 and controls grid and second to first of described storage unit M20 and control grid and apply second and read voltage, apply the switch controlling signal sel of high level to the grid of a described NMOS pipe N1, control a described NMOS pipe N1 conducting.Described the 2nd NMOS pipe N2 is in incomplete cut-off state, and the electric current that flows through described the 2nd NMOS pipe N2 is clamped to the electric current of described storage unit M20 and equates.The reference current that described reference current source Ir provides and the electric current of described storage unit M20 compare, according to comparative result, back end VD is carried out to charge or discharge, raise or reduce the voltage of described back end VD, described voltage comparator Comp is " 1 " or " 0 " according to the comparative result output data Dout of the voltage of described back end VD and described reference voltage Vr.
Conventionally, described first reads voltage and described second reads voltage and is provided by the line decoder in storer, and described switch controlling signal sel is provided by the column decoder in storer.Described first to read voltage be 2.5V to 3V, and described second to read voltage be 0V.But the power consumption while adopting existing method of operating to read described storage unit M20 is larger, affect the overall performance of storer.
Summary of the invention
What the present invention solved is the large problem of power consumption when storage unit is carried out to read operation.
For addressing the above problem, the invention provides a kind of reading circuit of storage unit, described storage unit comprises target, the first control grid, the second control grid, drain electrode and source electrode, and the reading circuit of described storage unit comprises: a PMOS pipe, precharge unit and comparing unit;
The grid of a described PMOS pipe is suitable for input switch control signal, and the drain electrode of a described PMOS pipe couples the drain electrode of described storage unit;
Described precharge unit is suitable for, in the time receiving precharging signal, the source electrode of a described PMOS pipe is charged to pre-charge voltage;
Described comparing unit is suitable in the time receiving enable signal, the source voltage of the first reference voltage and a described PMOS pipe being compared, export the data of described cell stores according to comparative result, described pre-charge voltage is greater than described the first reference voltage, and described the first reference voltage is greater than the threshold voltage of a described PMOS pipe.
Optionally, described precharge unit comprises the 2nd PMOS pipe;
The grid of described the 2nd PMOS pipe is suitable for inputting described precharging signal, and the source electrode of described the 2nd PMOS pipe is suitable for connecting precharge power supply, and the drain electrode of described the 2nd PMOS pipe connects the source electrode of a described PMOS pipe.
The power supply of the reading circuit that optionally, described precharge power supply is described storage unit.
Optionally, described comparing unit comprises voltage comparator;
The first input end of described voltage comparator connects the source electrode of a described PMOS pipe, the second input end of described voltage comparator is suitable for inputting described the first reference voltage, the control end that enables of described voltage comparator is suitable for inputting described enable signal, and the output terminal of described voltage comparator is suitable for exporting the data of described cell stores.
Optionally, the reading circuit of described storage unit also comprises the reference voltage generation unit that is suitable for producing described the first reference voltage, and described reference voltage generation unit comprises reference current source and the 3rd PMOS pipe;
One end of described reference current source is suitable for the power supply of the reading circuit that connects described storage unit, and the other end of described reference current source connects the source electrode of described the 3rd PMOS pipe and is suitable for exporting described the first reference voltage;
The grid of described the 3rd PMOS pipe is suitable for inputting the second reference voltage, and the drain electrode of described the 3rd PMOS pipe is suitable for inputting reference potential, and described the 3rd PMOS pipe works in saturation region.
Optionally, described reference potential is earth potential.
Based on the reading circuit of said memory cells, the present invention also provides a kind of read method of storage unit, and the read method of described storage unit comprises:
Apply the grid of switch controlling signal to a described PMOS pipe, control a described PMOS pipe conducting;
Apply precharging signal to described precharge unit, the source electrode of a described PMOS pipe is charged to described pre-charge voltage;
Stop applying described precharging signal, apply first of positive voltage value and read the target of voltage to described storage unit, apply second of negative value and read voltage to the first control grid of described storage unit and the second control grid of described storage unit, apply the source electrode of 0V voltage to described storage unit;
Apply enable signal to described comparing unit, the source voltage of more described the first reference voltage and a described PMOS pipe.
Optionally, described first to read voltage be 2.5V to 3.5V, and described second reads voltage for-0.4V is to-1V.
The present invention also provides a kind of storer, comprising:
Storage array, comprise the storage unit that word line, first is controlled grid line, the second control grid line, bit line, source line and is arranged in array, described storage unit comprises target, the first control grid, the second control grid, drain electrode and source electrode, described target connects described word line, described first controls grid connects described the first control grid line, described second controls grid connects described the second control grid line, and described drain electrode connects described bit line, and described source electrode connects described source line;
Line decoder, is suitable for providing first of positive voltage value to read voltage, provide second of negative value to read voltage to described the first control grid line and described the second control grid line to described word line in the time reading described storage unit;
The reading circuit of said memory cells, is suitable for reading the data of described cell stores;
Column decoder, is suitable for providing described switch controlling signal to a described PMOS pipe.
Optionally, described first to read voltage be 2.5V to 3.5V, and described second reads voltage for-0.4V is to-1V.
Compared with prior art, technical scheme of the present invention has the following advantages:
The reading circuit of storage unit provided by the invention and read method, before reading cells, carry out precharge to the source electrode of the PMOS pipe being connected with described storage unit; While reading described storage unit, by reading current, the source electrode of a described PMOS pipe is discharged.Control grid and apply second of negative value and read voltage owing to controlling grid and second to first of described storage unit, read current when described storage unit stores data " 0 " is close to 0.Therefore,, if described storage unit stores data " 0 ", after electric discharge, the source voltage of a described PMOS pipe remains pre-charge voltage, is greater than the first reference voltage; If described storage unit stores data " 1 ", after electric discharge, the source voltage of a described PMOS pipe drops to the threshold voltage of a described PMOS pipe and equates, is less than described the first reference voltage.Because reading circuit and the read method of storage unit provided by the invention do not need to provide reference current, the power consumption while having reduced to read described storage unit.
In possibility of the present invention, precharge power supply can be the power supply of the reading circuit of described storage unit.Guaranteeing that described pre-charge voltage is greater than under the prerequisite of described the first reference voltage, can reduce the magnitude of voltage of described pre-charge voltage as far as possible, with the speed of accelerating while reading described storage unit, the source electrode of a described PMOS pipe to be discharged, the power consumption while further reducing to read described storage unit.That is to say, in the case of the power supply of the reading circuit of described storage unit is lower, also can read described storage unit, and the speed that reads described storage unit is faster, power consumption is less.Therefore, the reading circuit of storage unit provided by the invention and read method can be applied in the system that low-voltage and low-power dissipation requires.
In possibility of the present invention, the reference voltage generation unit that produces described the first reference voltage comprises reference current source and the 3rd PMOS pipe, and described the first reference voltage equals threshold voltage and the second reference voltage sum of described the 3rd PMOS pipe.Because described the 3rd PMOS pipe and a described PMOS pipe belong to the transistor of same type, its manufacturing process is identical, for example, in the time being subject to external environment (temperature) and affecting, the threshold voltage variation of described the 3rd PMOS pipe can be followed the threshold voltage variation of a described PMOS pipe, be the threshold voltage variation that the variation of described the first reference voltage can be followed a described PMOS pipe, improved the precision that reads of described storage unit.
Accompanying drawing explanation
Fig. 1 is the cross-sectional view of existing a kind of EEPROM storage unit;
Fig. 2 is the structural representation that adopts existing a kind of reading circuit to read the storage unit shown in Fig. 1;
Fig. 3 is the read current of the storage unit shown in Fig. 2 and the time dependent schematic diagram of reference current that reference current source provides;
Fig. 4 is the structural representation of the reading circuit of the storage unit of the embodiment of the present invention;
Fig. 5 is the electrical block diagram of the reference voltage generation unit of the embodiment of the present invention;
Fig. 6 is the schematic flow sheet of the read method of the storage unit of embodiment of the present invention;
Fig. 7 is signal sequence and the voltage schematic diagram of the read method of the storage unit of the embodiment of the present invention.
Embodiment
For the read structure of the storage unit shown in Fig. 2, the reference current providing by more described reference current source Ir and the read current of described storage unit M20, determine that according to comparative result the data of described storage unit M20 storage are still " 0 " for " 1 ".Benchmark as a comparison, described reference current source Ir provides the reference current of direct current.The read current when read current of the current value of described reference current during according to described storage unit M20 storage data " 1 " and storage data " 0 " is determined, power consumption when its size has directly determined described storer to carry out read operation.
Fig. 3 is read current and the time dependent schematic diagram of described reference current of described storage unit M20.With reference to figure 3, horizontal ordinate represents the time, ordinate represents electric current, read current when straight line L30 represents described storage unit M20 storage data " 0 " (described storage unit M20 being carried out to write operation), read current when straight line L31 represents described storage unit M20 storage data " 1 " (described storage unit M20 being carried out to erase operation), straight line L32 represents described reference current.Conventionally, in order to increase the surplus that reads of described storage unit M20, the half of read current sum when read current when described reference current is set to described storage unit M20 storage data " 0 " and storage data " 1 ", i.e. ir=(i0+i1)/2.Wherein, the current value that ir is described reference current, read current value when i0 is described storage unit M20 storage data " 0 ", read current value when i1 is described storage unit M20 storage data " 1 ".
In the time of described storage unit M20 storage data " 0 ", the conducting channel of described storage unit M20 can not turn-off completely, therefore, read current value i0 when described storage unit M20 storage data " 0 " is not 0, cause the current value ir of described reference current larger, the power consumption while reading described storage unit M20 is large.Based on this, technical solution of the present invention provides reading circuit and the read method of a kind of storer, storage unit, by changing the voltage that reads that described storage unit is applied, read current while reducing described storage unit stores data " 0 ", thereby adopting does not need to provide the reading circuit of reference current to read described storage unit, the power consumption while reducing to read described storage unit.
For above-mentioned purpose of the present invention, feature and advantage can more be become apparent, below in conjunction with accompanying drawing, specific embodiments of the invention are described in detail.
Fig. 4 is the structural representation of the reading circuit of the storage unit of the embodiment of the present invention.With reference to figure 4, so that storage unit M40 is read as to example, described storage unit M40 is EEPROM storage unit, comprises the first floating boom, the second floating boom, target, the first control grid, the second control grid, drain electrode and source electrode.The target connective word line WL of described storage unit M40, first of described storage unit M40 controls grid and connects the first control grid line CG1, second of described storage unit M40 controls grid and connects the second control grid line CG2, the drain electrode of described storage unit M40 connects bit line BL, and the source electrode of described storage unit M40 connects source line SL.The concrete structure of described storage unit M40 can, with reference to the description to Fig. 1, not done too much explanation at this.
The reading circuit of described storage unit M40 comprises PMOS pipe P1, precharge unit 41 and a comparing unit 42.
Particularly, the grid of a described PMOS pipe P1 is suitable for input switch control signal SEL, described switch controlling signal SEL is suitable for controlling conducting and the cut-off of a described PMOS pipe P1: in the time that described switch controlling signal SEL is low level, control a described PMOS pipe P1 conducting; In the time that described switch controlling signal SEL is high level, control a described PMOS pipe P1 cut-off.The drain electrode of a described PMOS pipe P1 couples the drain electrode of described storage unit M40, i.e. the drain electrode of a described PMOS pipe P1 is connected with the drain electrode of described storage unit M40 by described bit line BL.
Described precharge unit 41 is suitable for, in the time receiving precharging signal CKA, the source electrode of a described PMOS pipe P1 is charged to pre-charge voltage.In the present embodiment, described precharge unit 41 comprises the 2nd PMOS pipe P2.The grid of described the 2nd PMOS pipe P2 is suitable for inputting described precharging signal CKA, and the source electrode of described the 2nd PMOS pipe P2 is suitable for connecting precharge power supply, and the drain electrode of described the 2nd PMOS pipe P2 connects the source electrode of a described PMOS pipe P1.
Because described the 2nd PMOS pipe P2 is P transistor npn npn, therefore, described precharging signal CKA is low level signal.In the time that the grid of described the 2nd PMOS pipe P2 receives described precharging signal CKA, described the 2nd PMOS pipe P2 conducting, described precharge power supply, by described the 2nd source electrode charging of PMOS pipe P2 to a described PMOS pipe P1, charges to pre-charge voltage by the source electrode of a described PMOS pipe P1.The magnitude of voltage of described pre-charge voltage can arrange according to the actual requirements, and the magnitude of voltage of described pre-charge voltage can be provided by the voltage of adjusting described precharge power supply and providing.Described precharge power supply can be direct voltage source arbitrarily, in the present embodiment, and the power supply Vdd of the reading circuit that described precharge power supply is described storage unit.
Described comparing unit 42 is suitable in the time receiving enable signal CKB, the source voltage of the first reference voltage Vref 1 and a described PMOS pipe P1 being compared, and exports the data Dout of described storage unit M40 storage according to comparative result.The duty of described comparing unit 42 is subject to the control of described enable signal CKB: described comparing unit 42 is worked in the time receiving described enable signal CKB, in the time not receiving described enable signal CKB, quits work.Node E is the tie point of the source electrode of described comparing unit 42, described precharge unit 41 and a described PMOS pipe P1, and the source voltage of a described PMOS pipe P1 is the voltage of described node E.
In the present embodiment, described comparing unit 42 comprises voltage comparator Comp.The first input end of described voltage comparator Comp connects the source electrode of a described PMOS pipe P1, the second input end of described voltage comparator Comp is suitable for inputting described the first reference voltage Vref 1, the control end that enables of described voltage comparator Comp is suitable for inputting described enable signal CKB, and the output terminal of described voltage comparator Comp is suitable for exporting the data Dout of described cell stores.
The first input end of described voltage comparator Comp can be in-phase input end, can be also inverting input; Correspondingly, the second input end of described voltage comparator Comp can be inverting input, can be also in-phase input end.Described enable signal CKB can be high level signal, can be also low level signal, specifically can arrange according to the physical circuit of described voltage comparator Comp, and the present invention is not construed as limiting this.
It should be noted that, the physical circuit of described precharge unit 41 and comparing unit 42 is not limited to the description of the present embodiment.In other embodiments, described precharge unit 41 and comparing unit 42 can be also the circuit of other elements formations, and the present invention is not construed as limiting this.
Benchmark as a comparison, described the first reference voltage Vref 1 is less than described pre-charge voltage, and described the first reference voltage Vref 1 is greater than the threshold voltage of a described PMOS pipe P1.Described the first reference voltage Vref 1 can be provided by direct voltage source arbitrarily, such as band gap reference etc.The present embodiment provides the generation unit of the reference voltage shown in a kind of Fig. 5, and described reference voltage generation unit is suitable for producing described the first reference voltage Vref 1.With reference to figure 5, described reference voltage generation unit comprises reference current source Iref and the 3rd PMOS pipe P3.
Particularly, one end of described reference current source Iref is suitable for the power supply Vdd of the reading circuit that connects described storage unit, and the other end of described reference current source Iref connects the source electrode of described the 3rd PMOS pipe P3 and is suitable for exporting described the first reference voltage Vref 1; The grid of described the 3rd PMOS pipe P3 is suitable for inputting the second reference voltage Vref 2, and the drain electrode of described the 3rd PMOS pipe P3 is suitable for inputting reference potential.Conventionally, described reference potential is earth potential, i.e. the grounded drain of described the 3rd PMOS pipe P3.The magnitude of voltage of described the second reference voltage Vref 2 can be determined according to the characteristic of described the 3rd PMOS pipe P3, as long as guarantee that described the 3rd PMOS pipe P3 works in saturation region, described the first reference voltage Vref 1 equals the threshold voltage sum of described the second reference voltage Vref 2 and described the 3rd PMOS pipe P3.
In the present embodiment, because described the first reference voltage Vref 1 equals the threshold voltage sum of described the second reference voltage Vref 2 and described the 3rd PMOS pipe P3, and the transistor that described the 3rd PMOS pipe P3 and a described PMOS pipe P1 are same type, for example, in the time being subject to external environment (temperature) and affecting, the threshold voltage variation of described the 3rd PMOS pipe P3 can be followed the threshold voltage variation of a described PMOS pipe P1.That is to say, the variation of described the first reference voltage Vref 1 can be followed the threshold voltage variation of a described PMOS pipe P1, guarantee that described the first reference voltage Vref 1 is constant with the voltage difference of the threshold voltage of a described PMOS pipe P1, improve the precision that reads of described storage unit M40.
The reading circuit of the storage unit based on above-described embodiment, the embodiment of the present invention also provides a kind of read method of storage unit.Fig. 6 is the schematic flow sheet of the read method of the storage unit of embodiment of the present invention, and the read method of described storage unit comprises:
Step S11: apply the grid of switch controlling signal to a described PMOS pipe, control a described PMOS pipe conducting;
Step S12: apply precharging signal to described precharge unit, the source electrode of a described PMOS pipe is charged to described pre-charge voltage;
Step S13: stop applying described precharging signal, apply first of positive voltage value and read the target of voltage to described storage unit, apply second of negative value and read voltage to the first control grid of described storage unit and the second control grid of described storage unit, apply the source electrode of 0V voltage to described storage unit;
Step S14: apply enable signal to described comparing unit, the source voltage of more described the first reference voltage and a described PMOS pipe.
To read the storage unit M40 shown in Fig. 4 as example, Fig. 7 is the schematic diagram of precharging signal CKA, enable signal CKB and the sequential of switch controlling signal SEL and the voltage VE of the first reference voltage Vref 1 and node E described in the embodiment of the present invention.With reference to figure 7, the method that the reading circuit that adopts the present embodiment to provide reads described storage unit M40 is divided into four-stage: preparatory stage T1, pre-charging stage T2, fetch phase T3 and phase data output T4.
At described preparatory stage T1, as described in step S11, apply the grid of switch controlling signal SEL to a described PMOS pipe P1, control a described PMOS pipe P1 conducting.Because a described PMOS pipe P1 is P transistor npn npn, therefore, described switch controlling signal SEL is low level.After a described PMOS pipe P1 conducting, described node E is communicated with described bit line BL.
At described pre-charging stage T2, as described in step S12, apply precharging signal CKA to described precharge unit 41, the source electrode of a described PMOS pipe P1 is charged to described pre-charge voltage.Or comprise that take described precharge unit 41 described the 2nd PMOS pipe P2 is as example, described precharging signal CKA is low level signal, control described the 2nd PMOS pipe P2 conducting, precharge power supply is by described the 2nd source electrode charging of PMOS pipe P2 to a described PMOS pipe P1, the voltage VE of described node E constantly raises, until reach stable.
At described fetch phase T3, as described in step S13, stop applying described precharging signal CKA, apply first of positive voltage value by described word line WL and read voltage to the target of described storage unit M40, described first to read voltage be 2.5V to 3.5V; Control grid line CG1 and described second by described first and control grid line CG2 and apply second of negative value and read voltage and control grid and second to first of described storage unit M40 and control grid, described second reads voltage for-0.4V is to-1V; By by described source line SL ground connection, apply the source electrode of 0V voltage to described storage unit M40.
Described storage unit M40 is applied and read after voltage, and the electric current of described storage unit M40 is read on described bit line BL.To read voltage be 2.5V to 3.5V due to described first, described second reads voltage for-0.4V is to-1V, the negative voltage being applied on the control grid line of described storage unit M40 is coupled on the floating boom of described storage unit M40, in the time of described storage unit M40 storage data " 0 ", the conducting channel of described storage unit M40 cuts out completely, reads electric current on described bit line BL close to 0.Therefore, in the time of described storage unit M40 storage data " 0 ", the voltage VE of described node E remains unchanged, and is still described pre-charge voltage; In the time of described storage unit M40 storage data " 1 ", by the electric current on described bit line BL, described node E is discharged, the voltage VE of described node E constantly declines, and equates until drop to the threshold voltage of a described PMOS pipe P1, a described PMOS pipe P1 cut-off.
At described phase data output T4, as described in step S14, apply enable signal CKB to described comparing unit 42.In the present embodiment, described enable signal CKB is high level signal.Described comparing unit 42 is started working after receiving described enable signal CKB, and the source voltage (being the voltage VE of described node E) of described the first reference voltage Vref 1 and a described PMOS pipe P1 is compared.If described storage unit M40 storage data " 0 ", the voltage VE of described node E equals described pre-charge voltage, described pre-charge voltage is greater than described the first reference voltage Vref 1, and the data Dout that described comparing unit 42 is exported described storage unit M40 storage is " 0 "; If described storage unit M40 storage data " 1 ", the voltage VE of described node E equals the threshold voltage of a described PMOS pipe P1, the threshold voltage of a described PMOS pipe P1 is less than described the first reference voltage Vref 1, and the data Dout that described comparing unit 42 is exported described storage unit M40 storage is " 1 ".
The reading circuit of the storage unit that the embodiment of the present invention provides and read method, by the source electrode of a described PMOS pipe P1 is discharged and recharged, be directly voltage by the current conversion of described storage unit M40 storage, and do not need to provide reference current, thereby power consumption while having reduced to read described storage unit M40.Further, described precharge power supply can be the power supply Vdd of the reading circuit of described storage unit, guaranteeing that described pre-charge voltage is greater than under the prerequisite of described the first reference voltage Vref 1, can reduce the magnitude of voltage of described pre-charge voltage as far as possible, the speed of while reading described storage unit M40 with quickening, the source electrode of a described PMOS pipe P1 being discharged, the power consumption while further reducing to read described storage unit M40.That is to say, in the case of the power supply Vdd of the reading circuit of described storage unit is lower, also can read described storage unit M40, and the speed that reads described storage unit M40 is faster, power consumption is less.Therefore, the reading circuit of storage unit provided by the invention and read method can be applied in the system that low-voltage and low-power dissipation requires.
The embodiment of the present invention also provides a kind of storer, and described storer comprises storage array, line decoder, reading circuit and array decoding circuit.Particularly, described storage array comprises the storage unit that word line, first is controlled grid line, the second control grid line, bit line, source line and is arranged in array.Described storage unit comprises target, the first control grid, the second control grid, drain electrode, source electrode, the first floating boom and the second floating boom.Described source electrode, first controls grid and the first floating boom forms the first bank bit, and grid is controlled in described drain electrode, second and the second floating boom forms the second bank bit.Conventionally, bank bit storage data in described the first bank bit and described the second bank bit, another bank bit is as for subsequent use.The structure of described storage unit can, with reference to the description to Fig. 1, not repeat them here.
The target of described storage unit connects described word line, first of described storage unit is controlled grid and is connected described the first control grid line, second of described storage unit is controlled grid and is connected described the second control grid line, the drain electrode of described storage unit connects described bit line, and the source electrode of described storage unit connects described source line.Apply voltage by described word line, first being controlled to grid line, the second control grid line, bit line and source line, realize the operation to described storage unit.
As a specific embodiment, in described storage array, connect same word line with the target of line storage unit, control grid connection same first with first of line storage unit and control grid line, control grid connection same second with second of line storage unit and control grid line, drain electrode with array storage unit connects same bit line, connects same source line with the source electrode of array storage unit.Certainly, the concrete structure of described storage array is not limited to the description of the present embodiment, as long as control grid line, bit line and source line and apply voltage and can realize described storage unit is operated by described word line, first being controlled to grid line, second.
Described line decoder is suitable for providing operating voltage to described word line in the time that described storer is operated, in technical solution of the present invention, in the time that described storer is carried out to read operation, described line decoder is suitable for providing first of positive voltage value to read voltage, provide second of negative value to read voltage to described the first control grid line and described the second control grid line to described word line.Described first reads voltage and the described second magnitude of voltage that reads voltage can be set according to circuit structure and device property etc., and in the present embodiment, described first to read voltage be 2.5V to 3.5V, and described second reads voltage for-0.4V is to-1V.
Described reading circuit is suitable for reading the data of described cell stores, and its particular circuit configurations can be the reading circuit shown in Fig. 4.Described column decoder is suitable for providing switch controlling signal to the PMOS pipe in described reading circuit, controls conducting and the cut-off of a described PMOS pipe.
In sum, the reading circuit of storer provided by the invention, storage unit and read method, do not need to provide reference current, the power consumption while having reduced to read described storage unit while reading described storage unit.
Although the present invention discloses as above, the present invention is not defined in this.Any those skilled in the art, without departing from the spirit and scope of the present invention, all can make various changes or modifications, and therefore protection scope of the present invention should be as the criterion with claim limited range.
Claims (10)
1. the reading circuit of a storage unit, described storage unit comprises target, the first control grid, the second control grid, drain electrode and source electrode, it is characterized in that, the reading circuit of described storage unit comprises: a PMOS pipe, precharge unit and comparing unit;
The grid of a described PMOS pipe is suitable for input switch control signal, and the drain electrode of a described PMOS pipe couples the drain electrode of described storage unit;
Described precharge unit is suitable for, in the time receiving precharging signal, the source electrode of a described PMOS pipe is charged to pre-charge voltage;
Described comparing unit is suitable in the time receiving enable signal, the source voltage of the first reference voltage and a described PMOS pipe being compared, export the data of described cell stores according to comparative result, described pre-charge voltage is greater than described the first reference voltage, and described the first reference voltage is greater than the threshold voltage of a described PMOS pipe.
2. the reading circuit of storage unit as claimed in claim 1, is characterized in that, described precharge unit comprises the 2nd PMOS pipe;
The grid of described the 2nd PMOS pipe is suitable for inputting described precharging signal, and the source electrode of described the 2nd PMOS pipe is suitable for connecting precharge power supply, and the drain electrode of described the 2nd PMOS pipe connects the source electrode of a described PMOS pipe.
3. the reading circuit of storage unit as claimed in claim 2, is characterized in that, the power supply of the reading circuit that described precharge power supply is described storage unit.
4. the reading circuit of storage unit as claimed in claim 1, is characterized in that, described comparing unit comprises voltage comparator;
The first input end of described voltage comparator connects the source electrode of a described PMOS pipe, the second input end of described voltage comparator is suitable for inputting described the first reference voltage, the control end that enables of described voltage comparator is suitable for inputting described enable signal, and the output terminal of described voltage comparator is suitable for exporting the data of described cell stores.
5. the reading circuit of the storage unit as described in claim 1 to 4 any one, is characterized in that, also comprises the reference voltage generation unit that is suitable for producing described the first reference voltage, and described reference voltage generation unit comprises reference current source and the 3rd PMOS pipe;
One end of described reference current source is suitable for the power supply of the reading circuit that connects described storage unit, and the other end of described reference current source connects the source electrode of described the 3rd PMOS pipe and is suitable for exporting described the first reference voltage;
The grid of described the 3rd PMOS pipe is suitable for inputting the second reference voltage, and the drain electrode of described the 3rd PMOS pipe is suitable for inputting reference potential, and described the 3rd PMOS pipe works in saturation region.
6. the reading circuit of storage unit as claimed in claim 5, is characterized in that, described reference potential is earth potential.
7. a read method for storage unit, the reading circuit of the storer based on described in claim 1 to 6 any one, is characterized in that, the read method of described storage unit comprises:
Apply the grid of switch controlling signal to a described PMOS pipe, control a described PMOS pipe conducting;
Apply precharging signal to described precharge unit, the source electrode of a described PMOS pipe is charged to described pre-charge voltage;
Stop applying described precharging signal, apply first of positive voltage value and read the target of voltage to described storage unit, apply second of negative value and read voltage to the first control grid of described storage unit and the second control grid of described storage unit, apply the source electrode of 0V voltage to described storage unit;
Apply enable signal to described comparing unit, the source voltage of more described the first reference voltage and a described PMOS pipe.
8. the read method of storage unit as claimed in claim 7, is characterized in that, described first to read voltage be 2.5V to 3.5V, and described second reads voltage for-0.4V is to-1V.
9. a storer, is characterized in that, comprising:
Storage array, comprise the storage unit that word line, first is controlled grid line, the second control grid line, bit line, source line and is arranged in array, described storage unit comprises target, the first control grid, the second control grid, drain electrode and source electrode, described target connects described word line, described first controls grid connects described the first control grid line, described second controls grid connects described the second control grid line, and described drain electrode connects described bit line, and described source electrode connects described source line;
Line decoder, is suitable for providing first of positive voltage value to read voltage, provide second of negative value to read voltage to described the first control grid line and described the second control grid line to described word line in the time reading described storage unit;
The reading circuit of the storage unit described in claim 1 to 6 any one, is suitable for reading the data of described cell stores;
Column decoder, is suitable for providing described switch controlling signal to a described PMOS pipe.
10. storer as claimed in claim 9, is characterized in that, described first to read voltage be 2.5V to 3.5V, and described second reads voltage for-0.4V is to-1V.
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| CN103824597B (en) | 2017-06-30 |
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