KR20100123331A - Semiconductor memory device and method for measuring sensing margin of the same - Google Patents

Abstract

PURPOSE: A semiconductor memory device and a method for measuring sensing margin of the same are provided to test a high sensing margin and a low sensing margin through one read operation by changing the voltage level of a sensing node. CONSTITUTION: A pre-charge unit(310) supplies a precharge current to a sensing node while a precharge operation section. A data input unit(320) inputs data to the sensing node. A sense amplifier(330) senses the data of the sensing node. The precharging unit flows a micro-current to the sensing node. The amount of the micro-current is controlled by a control signal.

Description

Semiconductor memory device and sensing margin measurement method {SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR MEASURING SENSING MARGIN OF THE SAME}

The present invention relates to a semiconductor memory device, and more particularly, to facilitate sensing margin measurement of a semiconductor memory device.

1 is a diagram illustrating a configuration for sensing data in a conventional semiconductor memory device.

As illustrated in FIG. 1, the semiconductor memory device includes a precharge unit 110, a data input unit 120, and a sense amplifier unit 130 for sensing data.

The precharge unit 110 precharges the sensing node SAI to a 'high' level before sensing data. In the precharge operation, the precharge signal SAILD is enabled at the 'low' level, so that the transistor 110 is turned on to precharge the sensing node SAI to the level of the power supply voltage VPPSA. The transistor 110 is turned off because the charge signal SAILD is 'high' disabled. When the transistor 110 is turned off, a fine current (leakage current) flows from the power supply voltage terminal VPPSA to the sensing node SAI.

The data input unit 120 is provided to input data stored in the memory cell to the sensing node SAI. The data input signal CLMBL is enabled as 'high' in the data sensing period to input data stored in the memory cell to the sensing node SAI. In this case, the amount of current sinked from the sensing node SAI varies depending on whether the data stored in the memory cell is 'high' or 'low'. As a result, the voltage level of the sensing node SAI is determined by the logic of the data. It depends on the state.

The sense amplifier 130 senses the voltage level of the sensing node SAI and senses data. The voltage level of the sensing node SAI is determined to be higher or lower than the reference voltage VREF to distinguish between 'high' and 'low' of the data. The sense amplifier enable signal SAEN is a signal for controlling the enable / disable of the sense amplifier unit 130.

FIG. 2 is a timing diagram illustrating a process of testing a sensing margin in the semiconductor memory device of FIG. 1.

In the normal read operation of the memory device, a 'high' and a 'low' of the data is sensed by comparing the voltage of the sensing node with a reference voltage level. However, in order to test the sensing margin of the memory device, a low margin and a high margin should be checked. Therefore, when testing the sensing margin, two read operations for comparing the voltages of the reference voltages VREF_L_M and VREF_H_M having a different level from the normal reference voltage VREF_NOM and the sensing node SAI, not the normal reference voltage VREF_NOM. (1st READ, 2nd READ) is done.

(1) First read operation (1st READ)

First, the sensing node SAI is precharged to a 'high' level by the precharge unit 110 (201). Thereafter, the precharge unit 110 is disabled, and only the fine current (leakage current flowing from the transistor turned off) flows into the sensing node SAI from the precharge unit 110.

With the activation of the data input signal CLMBL, a current is sinked from the sensing node SAI (202). How much current is sinked depends on the logic value of the data stored in the memory cell. Therefore, the voltage level of the sensing node SAI is determined according to the logic value of the data. The voltage level of the sensing node SAI is compared with the reference voltage VREF_L_M by the sense amplifier unit 130, and the result SAO is output from the sense amplifier unit 110.

(2) 2nd read operation (2nd READ)

The sensing node SAI is again precharged to the 'high' level by the precharge unit 110 (203). Thereafter, the precharge unit 110 is disabled, and only the fine current flows into the sensing node SAI from the precharge unit 110.

With the activation of the data input signal CLMBL, a current is sinked from the sensing node SAI (204). How much current is sinked depends on the logic value of the data stored in the memory cell. Therefore, the voltage level of the sensing node SAI is determined according to the logic value of the data. The voltage level of the sensing node SAI is compared with the reference voltage VREF_H_M by the sense amplifier unit 110, and the result SAO is output from the sense amplifier unit 110.

As a result of two read operations (1st READ, 2nd READ), if the voltage of the sensing node SAI is higher than the reference voltage VREF_L_M and lower than the reference voltage VREF_H_M, the sensing margin of the memory device is secured. It seems to be.

As described above, in the process of testing the sensing margin of the memory device, two read operations are performed to check the 'high' margin and the 'low' margin. Therefore, there is a problem that a lot of time is required to test the sensing margin.

In addition, in order to test the sensing margin, there is a burden of generating the reference voltages VREF_L_M and VREF_H_M in addition to the normal reference voltage VREF_NOM.

The present invention is proposed to solve the above problems of the prior art, and an object thereof is to reduce the time required for testing the sensing margin of a semiconductor memory device.

It also aims to enable testing of the sensing margin even with a small number of reference voltages.

A semiconductor memory device according to the present invention for achieving the above object, the sensing node; A precharge unit supplying a precharge current to the sensing node during a precharge operation period; A data input unit for inputting data into the sensing node; And a sense amplifier unit for sensing data of the sensing node, wherein the precharge unit flows a microcurrent to the sensing node during a section other than a precharge operation, wherein the amount of the microcurrent is controlled by a control signal. You can do

In addition, the sensing margin measuring method according to the present invention for achieving the above object, the step of precharging the sensing node to a predetermined voltage level; Flowing a data current through the sensing node; A first micro current flows through the sensing node; Comparing a level of a reference voltage and a voltage level formed on the sensing node by the data current and the first microcurrent; Flowing a second microcurrent through the sensing node; And comparing the level of the reference voltage with a voltage level formed on the sensing node by the data current and the second fine current.

In addition, the sensing margin measuring method according to the present invention for achieving the above object, the step of precharging the sensing node to a predetermined voltage level; Flowing a data current through the sensing node; A first micro current flows through the sensing node; Comparing a level of a plurality of reference voltages with a voltage level formed in the sensing node by the data current and the first microcurrent; Flowing a second microcurrent through the sensing node; And comparing the level of the plurality of reference voltages with a voltage level formed in the sensing node by the data current and the second microcurrent.

The present invention makes it possible to change the voltage level of the sensing node even when the same data is input to the sensing node. Therefore, it is possible to test the high sensing margin and the low sensing margin with a single read operation.

In addition, there is an advantage in that it is possible to test the high sensing margin and the low sensing margin even with one reference voltage.

DETAILED DESCRIPTION Hereinafter, exemplary embodiments of the present invention will be described with reference to the accompanying drawings so that those skilled in the art may easily implement the technical idea of the present invention. .

3 is a block diagram illustrating a semiconductor memory device in accordance with an embodiment of the present invention.

As shown in FIG. 3, the semiconductor memory device according to the present invention includes a sensing node SAI, a precharge unit 310, a data input unit 320, and a sense amplifier unit 330.

The precharge unit 310 supplies a precharge current to the sensing node SAI during the precharge operation period, and flows a microcurrent to the sensing node SAI during the period other than the precharge operation. The amount of microcurrent is controlled by the control signals V_RD, H_M and L_M. The precharge unit 310 supplies a precharge current when the precharge signal SAILD is activated, and a plurality of first transistors 311, 312, for supplying a leakage current when the precharge signal SAILD is inactivated. 313 and a plurality of second transistors 314 for transferring currents supplied from the plurality of first transistors 311, 312, and 313 to the sensing node SAI in response to the control signals V_RD, H_M, and L_M. 315, 316). The plurality of second transistors 314, 315, and 316 are all formed in different sizes.

The precharge signal SAILD is enabled as 'low' during the precharge period, and disabled as 'high' except for the precharge period. The control signal V_RD is always enabled as low during the normal read operation, and has the same logic level as the precharge signal SAILD in the test mode for testing the sensing margin. The control signals H_M and L_M are always disabled at the 'high' level during normal operation, and are alternately enabled at the 'low' level during the read operation for testing the sensing margin.

When the precharge signal SAILD is enabled at the 'low' level during the precharge period, the first transistors 311, 312, and 313 and the second transistor 314 are turned on. Therefore, the sensing node is precharged to the power supply voltage VPPSA level. During the normal read period, the second transistor 314 is turned on while the first transistors 311, 312, and 313 are turned off. Therefore, the minute current is supplied to the sensing node SAI through the second transistor 314. In addition, during the read period for the sensing margin test, the second transistor 314 is turned off, and the second transistors 315 and 416 are alternately turned on. Therefore, the micro current is supplied to the sensing node SAI by the second transistors 315 and 316. Since the second transistors 314, 315, and 316 have different sizes, the voltage level of the sensing node SAI is changed depending on which second transistor 314, 315, or 316 is supplied with the microcurrent.

The data input unit 320 is provided to input data stored in the memory cell to the sensing node. The data input signal is enabled as 'high' in the data sensing period to input data stored in the memory cell to the sensing node.

The sense amplifier 330 senses the voltage level of the sensing node SAI. The voltage level of the sensing node SAI is compared with the level of the reference voltage VREF, and the result SAO is output. The sense amplifier enable signal SAEN is a signal for controlling the enable / disable of the sense amplifier unit 330.

4A is a diagram illustrating a circuit for generating the signals of FIG. 3, and FIG. 4B is a timing diagram illustrating the operation of FIG. 4A.

4A and 4B, the SAE signal is delayed through the delay line 401 to become the SAE1 signal. The enable ('high') section of the SAE signal and the SAE1 signal are combined by the NOA gate 402 and the inverter 403 to form a sense amplifier enable signal SAEN.

While the control signal V_RD is disabled 'high', when the SAE signal is enabled 'high', the control signal L_M is enabled low by the NAND gate 404. Also, while the control signal V_RD is disabled, the control signal H_M is enabled by the NAND gate 405 when the SAE1 signal is enabled.

FIG. 5 is a timing diagram illustrating an operation during a sensing margin test of the semiconductor memory device of FIG. 3.

First, the sensing node SAI is precharged by the precharge unit 310. In this case, the first transistors 311, 312, and 313 and the second transistor 314 are turned on so that the sensing node is precharged to the level of the power supply voltage (section '501').

Thereafter, the data input signal CBLM is enabled 'high', and a data current flows through the sensing node SAI. The data current flows during the period in which the data input signal CBLM is active. The data current refers to a current sinked from the sensing node SAI by data. The amount of current in the data current depends on the logic value of the data.

During the initial period of the read operation (section '502'), the control signal L_M is enabled as 'low'. Therefore, the second transistor 316 is turned on and the first microcurrent is supplied by the second transistor 316. At this time, the data current and the first microcurrent flow through the sensing node SAI. The voltage level of the sensing node SAI formed by the data current and the first microcurrent is compared with the reference voltage VREF by the sense amplifier 330 (503), whereby a low sensing margin is confirmed.

During the later period of the read operation (section '504'), the control signal H_M is enabled as 'low'. Accordingly, the second transistor 315 is turned on, and the second transistor 315 is supplied with a second microcurrent (a different amount of current from the first microcurrent). At this time, the data current and the second micro current flow through the sensing node SAI. The voltage level of the sensing node SAI formed by the data current and the second micro current is compared with the reference voltage VREF by the sense amplifier 330 (505), whereby a high sensing margin is confirmed.

The present invention uses a method of changing the microcurrent flowing through the sensing node SAI in order to test the high sensing margin and the low sensing margin of the memory device. This eliminates the need for two read operations to test the sensing margin and eliminates the need for multiple reference voltages (VREF).

6 is a configuration diagram of a semiconductor memory device according to another embodiment of the present invention.

6 is basically the same as FIG. 3. However, there is only a difference that the sense amplifier unit 630 is composed of a plurality of sense amplifiers 631, 632, and 634.

The memory device may store only one data in one memory cell (SLC), but sometimes two or more data may be stored in one memory cell (MLC). In this case, since the voltage level of the sensing node SAI should be distinguished by various stages instead of just 'high' and 'low', the sense amplifier unit 630 includes a plurality of sense amplifiers 631, 632, and 633.

For example, if two data are stored in one memory cell, the four logic values are (high, high), (high, low), (low, high), and (low, low). There is a case. In this case, the voltage level of the sensing node SAI must also be distinguished in four stages. To do this, the voltage level of the sensing node SAI must be compared with three reference voltages VREF1, VREF2, VREF3 and having different levels. do.

FIG. 6 illustrates a case in which the sense amplifier unit 630 includes three sense amplifiers 631 to 633 to distinguish the voltage level of the sensing node SAI in four stages. 6 operates in the same manner as in FIG. 3 except that the sense amplifier unit 630 includes three sense amplifiers 631, 632, and 633, and thus, detailed description thereof will be omitted.

Although the technical spirit of the present invention has been described in detail according to the above-described preferred embodiment, it should be noted that the above-described embodiment is for the purpose of description and not of limitation. In addition, those skilled in the art will recognize that various embodiments are possible within the scope of the technical idea of the present invention.

1 is a diagram illustrating a configuration for sensing data in a conventional semiconductor memory device.

FIG. 2 is a timing diagram illustrating a process of testing a sensing margin in the semiconductor memory device of FIG. 1. FIG.

3 is a block diagram of a semiconductor memory device in accordance with an embodiment of the present invention.

4A shows a circuit for generating the signals of FIG.

4B is a timing diagram illustrating the operation of FIG. 4A.

FIG. 5 is a timing diagram illustrating an operation during a sensing margin test of the semiconductor memory device of FIG. 3. FIG.

6 is a configuration diagram of a semiconductor memory device according to another embodiment of the present invention.

Claims (8)

Sensing node; A precharge unit supplying a precharge current to the sensing node during a precharge operation period; A data input unit for inputting data into the sensing node; And Sense amplifier unit for sensing the data of the sensing node Including, The precharge unit may flow a microcurrent to the sensing node during a period other than a precharge operation, and the amount of the microcurrent is controlled by a control signal. The method of claim 1, The sense amplifier unit, And a sense amplifier configured to sense data by comparing a reference voltage with a voltage level of the sensing node. The method of claim 1, The sense amplifier unit, Including a plurality of sense amplifiers, And the plurality of sense amplifiers sense the data by comparing reference voltages having different levels with those of the sensing node. The method of claim 1, The precharge unit, A plurality of first transistors for supplying a precharge current upon activation of the precharge signal and for supplying a leakage current upon inactivation of the precharge signal; And a plurality of second transistors for transferring currents supplied from the plurality of first transistors to the sensing node in response to the control signal. The method of claim 4, wherein Each of the plurality of second transistors, A semiconductor memory device, characterized in that different in size. Precharging the sensing node to a predetermined voltage level; Flowing a data current through the sensing node; A first micro current flows through the sensing node; Comparing a level of a reference voltage and a voltage level formed on the sensing node by the data current and the first microcurrent; Flowing a second microcurrent through the sensing node; And Comparing the level of the reference voltage with a voltage level formed on the sensing node by the data current and the second microcurrent; Sensing margin measurement method of a semiconductor memory device comprising a. Precharging the sensing node to a predetermined voltage level; Flowing a data current through the sensing node; A first micro current flows through the sensing node; Comparing a level of a plurality of reference voltages with a voltage level formed in the sensing node by the data current and the first microcurrent; Flowing a second microcurrent through the sensing node; And Comparing the level of the plurality of reference voltages with a voltage level formed on the sensing node by the data current and the second microcurrent; Sensing margin measurement method of a semiconductor memory device comprising a. The method according to claim 6 or 7, And a current amount of the first micro current and the second micro current are different from each other.

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