CN111489779A - Double-separation-gate flash memory circuit, storage device and reading method - Google Patents
Double-separation-gate flash memory circuit, storage device and reading method Download PDFInfo
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- CN111489779A CN111489779A CN202010300323.8A CN202010300323A CN111489779A CN 111489779 A CN111489779 A CN 111489779A CN 202010300323 A CN202010300323 A CN 202010300323A CN 111489779 A CN111489779 A CN 111489779A
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/04—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
- G11C16/0483—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells having several storage transistors connected in series
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/24—Bit-line control circuits
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/26—Sensing or reading circuits; Data output circuits
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Abstract
The invention provides a double-separation gate flash memory circuit, a storage device and a reading method. The dual split gate flash memory circuit includes a memory cell including a first bit line connected to a source electrode and a second bit line connected to a drain electrode, and a read signal control module for acquiring a read signal by electrically connecting the control module to an output terminal of the first bit line while precharging the second bit line to a power supply voltage when a read operation is performed. The double-separation-gate flash memory circuit can conveniently form a potential difference meeting the reading operation requirement between the source electrode and the drain electrode of the memory cell on the occasion of low power supply voltage, and further performs reading operation on the selected memory cell. The control module does not need to be specially provided with an NZ tube to reduce voltage loss, a layer of photomask can be omitted, and the manufacturing cost of the flash memory is saved. The invention also provides a storage device comprising the double-separation gate flash memory circuit and a reading method using the double-separation gate flash memory circuit.
Description
Technical Field
The present invention relates to the field of memory technologies, and in particular, to a dual split gate flash memory circuit, a memory device including the same, and a reading method using the same.
Background
Flash memories (Flash memories) can still retain stored data information when power is off, and are Non-Volatile memories. Flash memory has the characteristics of no need of special high voltage, low manufacturing cost, high storage density and the like during electric erasing and repeated programming, and is currently the mainstream of nonvolatile semiconductor storage technology. The double-split-gate memory Cell (NORD Cell) has high transmission efficiency and high cost efficiency at a small capacity of 1 MB-4 MB, so that the double-split-gate flash memory is one of the major nonvolatile memories in the market at present.
Fig. 1 is a schematic diagram of a conventional dual split gate flash memory circuit, as shown in fig. 1, the dual split gate flash memory circuit includes a memory cell 10 and a first address decoding unit 21 and a second address decoding unit 22 connected to two ends of the memory cell 10, wherein the first address decoding unit 21 and the second address decoding unit 22 are configured to transmit a read signal of a selected memory cell 10 to an input/output end iod of a control module (not shown in fig. 1) under the control of a control signal when a read operation is performed, for the selected memory cell 10, a source electrode S thereof is connected to a bit line B L1, a drain electrode D thereof is connected to a bit line B L, and when the read operation is performed, the bit line B L is placed at a positive potential, the bit line B L is placed at a positive potential to form a certain potential difference between a source-drain-ground potential electrode and a corresponding read signal.
However, for some dual split gate flash memories, the power voltage VDD is small, for example, for a dual split gate flash memory with a 55nm process node, the power voltage VDD is only about 1.05V to 1.35V, and in order to obtain a positive voltage on the bit line B L2, which meets the requirement, on one hand, the control module part needs to use a low-voltage zero-threshold-voltage transistor (NZ tube) to reduce the voltage loss, which results in at least one additional mask added during the manufacturing process, increasing the manufacturing cost of the flash memory device, and on the other hand, this may result in a too small operation window for reading the selected memory cell.
Therefore, the read operation method of the conventional dual split gate flash memory needs to be improved.
Disclosure of Invention
The invention provides a double-separation gate flash memory circuit, which improves the read operation mode of the existing double-separation gate flash memory, can perform read operation under the condition that a control circuit does not need to be provided with an NZ tube, and can save a layer of photomask compared with the existing mode. The invention also provides a storage device comprising the double-separation gate flash memory circuit and a reading method using the double-separation gate flash memory circuit.
In order to achieve the above object, an aspect of the present invention provides a dual split gate flash memory circuit, which includes a memory cell and a control module for obtaining a read signal of the memory cell, wherein the memory cell has a source electrode and a drain electrode, the source electrode is connected to a first bit line, the drain electrode is connected to a second bit line, the control module is electrically connected to the first bit line to obtain the read signal, and a level of the second bit line is precharged to a power supply voltage when a read operation is performed on the memory cell, so that the drain electrode is at a positive potential with respect to the source electrode.
Optionally, the control module includes:
a pre-charging unit for pre-charging an initial potential of the first bit line to a first reference voltage;
a first comparing unit for comparing a voltage of the first bit line with the first reference voltage and outputting a switching control signal when a read operation is performed on the memory cell;
the switch unit is used for being turned on or turned off according to the switch control signal output by the first comparison unit, one end of the switch unit is connected with the first bit line, and the other end of the switch unit is connected with a first node;
the signal output end of the bias unit is connected with the first node and used for pulling down the potential of the first node when the switch unit is not opened;
the reset unit is used for receiving a reset signal and resetting the potential of the first node to enable the initial potential of the first node to be close to zero potential;
and a second comparing unit for comparing the voltage of the first node with a second reference voltage and outputting a sensing signal when a read operation is performed on the memory cell.
Optionally, the precharge unit includes an NMOS transistor, one end of the NMOS transistor is connected to the power supply voltage, and the other end of the NMOS transistor is connected to the first bit line.
Optionally, the switch unit is selected from one of a PMOS transistor, an NMOS transistor, a triode, a JFET, and an IGBT.
Optionally, the power supply voltage is 1V to 1.4V.
Optionally, the dual split gate flash memory further includes:
the first address decoding unit is connected with the output end of the power supply voltage and the second bit line and used for forming a switch control signal between the output end of the power supply voltage and the second bit line according to an externally input address signal; and
and the second address decoding unit is connected with the output end of the first bit line and the control module and is used for forming a switch control signal between the output end of the first bit line and the control module according to an externally input address signal.
Optionally, the first address decoding unit and the second address decoding unit each include a plurality of MOS transistors connected in series.
Optionally, the first address decoding unit includes a plurality of PMOS transistors connected in series, and the second address decoding unit includes a plurality of NMOS transistors connected in series.
In another aspect, the present invention provides a method for reading a dual split gate flash memory, which utilizes the above dual split gate flash memory circuit, and the method includes:
precharging a level of the second bit line to a power supply voltage;
the level of a first bit line is precharged to the output voltage of the precharging unit by using a precharging unit of the control module, the first node is subjected to potential resetting by using the resetting unit, the initial potential of the first node is close to zero potential, and the levels of the first bit line and the first node are precharged to a first reference voltage after the precharging unit and the resetting unit act together and reach balance; and
a read operation is performed in which, among other things,
when a storage signal of a storage unit is at a high level, a voltage of a first bit line is higher than a first reference voltage, the first comparison unit compares the voltage of the first bit line with the first reference voltage and outputs a switch control signal to enable the switch unit to be turned on and the voltage of the first node is higher than the first reference voltage, the first reference voltage is set to be higher than a second reference voltage, and the second comparison unit compares the voltage of the first node with the second reference voltage and outputs the read signal at the high level;
when the storage signal of the storage unit is at a low level, the voltage of the first bit line is lower than a first reference voltage, the first comparison unit compares the voltage of the first bit line with the first reference voltage and outputs the switch control signal to turn off the switch unit, the bias unit pulls down the potential of the first node to make the voltage of the first node lower than the second reference voltage, and the second comparison unit compares the voltage of the first node with the second reference voltage and outputs the read signal at a low level.
The invention further provides a memory device comprising the dual split gate flash memory circuit.
The double-separation-gate flash memory circuit provided by the invention has the advantages that when the memory cell is read, the second bit line connected with the drain electrode of the memory cell is precharged to the power supply voltage, so that the drain electrode is at a positive potential relative to the source electrode, and on the occasion of low power supply voltage, the control module only needs to apply low voltage on the first bit line, and can also conveniently form a potential difference meeting the reading operation requirement between the source electrode and the drain electrode of the memory cell, so that the memory cell can form a corresponding reading signal and output the reading signal to the control module through the first bit line, and further, the reading operation is carried out on the selected memory cell. Because the read operation mode of the dual-split-gate flash memory is improved, the voltage applied by the control module is smaller when the memory unit is read, so that the control module does not need to be specially provided with an NZ tube to reduce the voltage loss, and the NZ tube is arranged in the control module and at least needs to be added with an additional layer of photomask, therefore, the control module in the dual-split-gate flash memory circuit can omit a layer of photomask when being manufactured, and the manufacturing cost of the dual-split-gate flash memory device can be reduced.
In another aspect of the present invention, a method for reading a dual split gate flash memory is provided, which mainly uses the dual split gate flash memory circuit to read a memory cell, and since the dual split gate flash memory circuit can perform a read operation without setting an NZ pipe in a control module, the method for reading a dual split gate flash memory circuit can also perform a read operation on a memory cell without setting an NZ pipe in a control module, thereby reducing the manufacturing cost of the dual split gate flash memory device.
The memory device further comprises the double-split-gate flash memory circuit, so that the memory device has the advantages similar to the double-split-gate flash memory circuit.
Drawings
Fig. 1 is a schematic diagram of a conventional dual split gate flash memory circuit.
Fig. 2 is a schematic diagram of a dual split gate flash memory circuit according to an embodiment of the invention.
FIG. 3 is a diagram of a sense amplifier circuit according to an embodiment of the invention.
FIG. 4 is a waveform diagram of a control signal when the sense amplifier operates according to an embodiment of the present invention.
Description of reference numerals:
10-a memory cell; 21-a first address decoding unit; 22-second address decoding unit.
Detailed Description
The dual split gate flash memory circuit, the memory device including the dual split gate flash memory circuit, and the reading method using the dual split gate flash memory circuit according to the present invention will be described in further detail with reference to the accompanying drawings and specific embodiments. The advantages and features of the present invention will become more apparent from the following description. It is to be noted that the drawings are in a very simplified form and are not to precise scale, which is provided solely for the purpose of facilitating and distinctly claiming the embodiments of the present invention.
The dual split gate flash memory circuit of the present embodiment includes a memory cell and a control module for obtaining a read signal of the memory cell, the memory cell has a source electrode and a drain electrode, the source electrode is connected to a first bit line, the drain electrode is connected to a second bit line, the control module is electrically connected to the first bit line to obtain the read signal, and the level of the second bit line is precharged to a power supply voltage when a read operation is performed on the memory cell, so that the drain electrode is at a positive potential with respect to the source electrode.
Specifically, the power voltage in this embodiment may be 1V to 1.4V. The level of the second bit line is precharged to the power supply voltage when the memory cell is read, the drain electrode connected with the second bit line is a positive potential relative to the source electrode due to the high potential of the power supply voltage, the control module only needs to apply a small voltage on the first bit line, and a potential difference meeting the reading operation requirement can be formed between the source electrode and the drain electrode of the memory cell, so that a corresponding reading signal is formed and output to the control module through the output end of the first bit line, and the reading function of the dual-split-gate flash memory circuit is realized. The double-split-gate flash memory circuit of the embodiment has the advantages that the control module does not need to apply larger voltage at the output end of the first bit line, and the NZ tube arranged in the control module is used for reducing the voltage loss of the control module, so that the control module of the double-split-gate flash memory can perform reading operation under the condition that the NZ tube is not arranged, a layer of photomask can be saved, and the manufacturing cost of a double-split-gate flash memory device is reduced. In addition, the control module does not need to apply larger voltage to the first bit line, the operation space for applying the voltage to the first bit line by the control module is larger, and the operation window when the control module performs read operation on the storage unit can be enlarged, namely the read operation window of the storage unit is enlarged.
Fig. 2 is a schematic diagram of a dual split gate flash memory circuit according to an embodiment of the present invention, which will be described below with reference to fig. 2, the dual split gate flash memory circuit of the present embodiment includes a memory cell 10 and a control module (not shown in fig. 1) for obtaining a read signal of the memory cell, the memory cell 10 includes a first bit line B L1 connected to a source electrode S and a second bit line B L2 connected to a drain electrode D, wherein, when a read operation is performed on the memory cell 10, the second bit line B L2 is precharged to a power supply voltage to make the drain electrode D a positive potential with respect to the source electrode S, and the control module is electrically connected to the first bit line B L1 to obtain the read signal, the dual split gate flash memory circuit of the present embodiment may further include a first address decoding unit 21 and a second address decoding unit 22, the first address decoding unit 21 connects an output terminal of the power supply voltage and the second bit line B L2, the first address decoding unit 21 is used for forming an external address control signal for connecting the second bit line B L1 between the power supply voltage and the second bit line B L1, and the control module forms an external address decoding unit 3626 for controlling the second bit line B.
Fig. 2 shows only selected memory cells 10 and first address decoding units 21 and second address decoding units 22 selectively connected to the selected memory cells 10 when reading the dual split gate flash memory. The dual split gate flash memory circuit may further include a plurality of unselected memory cells, and the plurality of memory cells may be arranged in an array to form a memory array for storing information. The two ends of the source electrode and the drain electrode of each storage unit are respectively selectively connected with a corresponding first address decoding unit and a corresponding second address decoding unit, the first address decoding units and the second address decoding units form an address decoding circuit, the address decoding circuit is used for selectively connecting the storage units in the storage array according to an externally input address signal so as to read the selected storage units, and more specifically, the address decoding circuit is used for applying voltage to a first bit line and a second bit line which are connected with the two ends of the source electrode and the drain electrode of each storage unit and transmitting a read signal generated in each storage unit to the control module.
In this embodiment, each of the first address decoding unit 21 and the second address decoding unit 22 may include a plurality of MOS transistors (metal oxide semiconductors) connected in series. Specifically, the first address decoding unit 21 may include a plurality of PMOS transistors (Positive channel Metal Oxide Semiconductor) connected in series, and the second address decoding unit 22 may include a plurality of NMOS transistors (Negative channel Metal Oxide Semiconductor) connected in series. Because the voltage loss generated by the NMOS tube when the voltage is applied to the storage unit is larger than that of the PMOS tube, the loss of power supply voltage can be reduced when the first address decoding unit adopts the PMOS tube to read the storage unit, the difficulty of generating potential difference required by reading between the source electrode and the drain electrode of the storage unit can be further reduced, and the operation window when the flash memory is read can be increased under the condition of reducing the power supply voltage.
With continued reference to fig. 2, the first address decoding unit 21 in this embodiment may include three PMOS transistors PM01, PM02, and PM03, a source terminal of PM01 is connected to the power supply voltage vdd, a source terminal of PM02 is connected to a drain terminal of PM01, a drain terminal of PM02 is connected to a source terminal of PM03, and a drain terminal of PM03 is connected to the drain electrode D of the memory cell 10 through a second bit line B L, wherein a gate of the PMOS transistor may be grounded, and a substrate terminal of the PMOS transistor may be connected to the power supply voltage vdd. in a read operation on the memory cell, the PMOS transistor in the first address decoding unit is turned on and the power supply voltage is applied to a second bit line B L connected to the drain electrode D of the memory cell, the second address decoding unit 22 in this embodiment may include three NMOS transistors NM11, NM 8, and NM13, a drain terminal of NM11 is connected to the source electrode S of the memory cell, a drain terminal of NM11 is connected to the NM 84, a source terminal of the NM 3642 is connected to the NMOS transistor, and a drain terminal of the NMOS transistor is connected to the NMOS transistor 4610, wherein the drain terminal of the decoding module may be connected to the NMOS transistor, and the drain terminal of the NMOS transistor is connected to the NMOS transistor, and the drain transistor is connected to the NMOS transistor, and the transistor is connected to the NMOS transistor, wherein the transistor is connected to the transistor, and the transistor is connected to the drain terminal of the.
In this embodiment, the control module of the dual split gate flash memory circuit may include a pre-charge unit, a first comparison unit, a switch unit, a bias unit, a reset unit and a second comparison unit, wherein the pre-charge unit is configured to pre-charge an initial potential of the first bit line to the first reference voltage, the first comparison unit is configured to compare a voltage of the first bit line with the first reference voltage and output a switch control signal when performing a read operation on the memory cell, the switch unit is configured to be turned on or off according to the switch control signal output by the first comparison unit, one end of the switch unit is connected to the first bit line, the other end of the switch unit is connected to the first node, a signal output end of the bias unit is connected to the first node and is configured to pull down a potential of the first node when the switch unit is not turned on, the reset unit is configured to receive a reset signal and reset the potential of the first node, the initial potential of the first node is made to approach zero potential, and the second comparing unit is used for comparing the voltage of the first node with a second reference voltage and outputting and reading out signals when the memory cell is read. It should be noted that, the pre-charge unit pre-charges the level of the first bit line to the output voltage of the pre-charge unit, and the reset unit resets the level of the first node to make the initial level of the first node approach to zero, and after the pre-charge unit and the reset unit act together and reach equilibrium, the levels of the first bit line and the first node are pre-charged to the first reference voltage, where the output voltage of the pre-charge unit may be the difference between the power supply voltage and the internal loss voltage of the pre-charge unit.
In this embodiment, the control module may include a sense amplifier, wherein the switching unit may be selected from one of a PMOS transistor, an NMOS transistor, a triode, a JFET, and an IGBT. FIG. 3 is a diagram of a sense amplifier circuit according to an embodiment of the invention. As shown in fig. 3, the sense amplifier of the present embodiment may include a precharge unit, a switch unit, a reset unit and a bias unit which are different NMOS transistors, and the first comparison unit and the second comparison unit may include a voltage comparator and an inverter.
The sense amplifier and the first bit line B1 may be electrically connected at the input/output terminal IOS through a second address decoding unit, the precharge unit may include an NMOS transistor NM having one end connected to a power supply voltage vdd and the other end electrically connected to the IOS, i.e., the other end connected to the first bit line B1, a precharge signal ATD input from the gate of the NM, a precharge unit NM for precharging an initial potential of the first bit line B1 to a first reference voltage, the first comparison unit may include a voltage comparator I having a plurality of signal input ports, a first read signal SEN input from the signal input terminal of the inverter I, a signal output terminal of the inverter I connected to a signal input terminal of the voltage comparator I, a first reference voltage VREF applied to a signal input terminal of the voltage comparator I, the other signal input terminal of the voltage comparator I connected to the IOS, a BIAS current SA _ BIAS and a voltage applied to the voltage comparator NM, a signal output terminal of the voltage comparator NM connected to a signal input terminal of the switch I, a voltage comparator I connected to a gate voltage input terminal of the first bit line NM, a drain voltage comparator I connected to a gate of the first bit line NM, a drain voltage comparator I, a drain voltage I connected to a gate I, a drain voltage I, a drain I.
In a read operation of a memory cell, the operation of the sense amplifier may include a precharge step and a normal read step. FIG. 4 is a waveform diagram of a control signal when the sense amplifier operates according to an embodiment of the present invention. The operation of each unit of the sense amplifier will be described in detail with reference to fig. 4.
When a new memory address signal is transmitted to the sense amplifier, the sense amplifier first performs a precharge step, a precharge signal ADT is input from the gate of NM14 of the precharge unit, and the potential of the input/output terminal IOS at the initial stage is precharged to the output voltage of the precharge unit under the action of the precharge unit, wherein the output voltage of the precharge unit is the power supply voltage minus the threshold voltage of the NMOS transistor NM14, and at the same time, a reset signal RSTB L is input to the reset unit from the gate of NM16 of the reset unit, the reset unit performs a potential reset on the first node E so that the initial potential of the first node E is close to zero potential, after the precharge unit and the reset unit are combined and balanced, the levels of the input/output terminal IOS and the first node E are precharged to a first reference voltage, that is the level of the first bit line precharged to the first reference voltage, the first reference voltage VREF1 is smaller than the power supply voltage applied to the second bit line, and the first reference voltage is a smaller voltage applied to the first bit line, so that the potential difference between the control module (sense amplifier) can generate a common read-source-drain signal, thereby generating a memory cell.
The memory cell can be divided into a high level memory cell (storing information is 1) and a low level memory cell (storing information is 0) according to the stored information, when a read operation is performed on the high level memory cell, SEN2 is a high-order stage, the memory cell outputs a read signal to the IOS through a first bit line B L1, i.e., the output current is large, the voltage of the IOS, i.e., the voltage of the first bit line, is higher than VREF1, a voltage comparator I10 of the first comparison unit compares the voltage of the first bit line with a first reference voltage and outputs a switch control signal, a switch unit NM15 is turned on according to the switch control signal, the potential of the first node E is also higher than VREF1, VREF 4 is set to be higher than a second reference voltage 2, a voltage comparator I11 of the second comparison unit compares the voltage of the first node E with a second node e., VREF2, and outputs a high level signal which is consistent with the read signal, I4831, and outputs a high level signal which is not consistent with the read signal (no output) of the read signal, wherein the read signal SEN 8291 is output after the stored information, the read signal does not output level of the high level B351, and the output level of the switch control signal (no output signal).
When reading a low level memory cell, SEN2 is a high-order segment, the memory cell outputs less read information to the IOS through the first bit line, i.e. the output current, the IOS voltage, i.e. the voltage of the first bit line, is lower than the first reference voltage VREF1, the voltage comparator I10 of the first comparing unit compares the voltage of the first bit line with the first reference voltage and outputs a switch control signal, the switch unit NM15 is turned off according to the switch control signal, the potential of the first node E is pulled to 0 by the bias unit NM17, at this time, the potential of the first node E is lower than the second reference voltage VREF2, the voltage comparator I11 of the second comparing unit compares the voltage of the first node E with the second reference voltage 2 and outputs a low level signal (0), the inverter I03 outputs a high level signal SOUTB (1), and after the inversion outputs a low level read signal DOUT (0), i.e. the second comparing unit outputs a read signal consistent with the level of the first VREF, the read information is identical to the storage information of the low-level memory cell. It should be noted that the first read signal SEN in the sense amplifier is applied all the time during the whole reading process.
In addition, when the memory cell is read, the memory address signal is also transmitted to the address decoding circuit, and the address decoding circuit selects the memory cell according to the memory address signal, namely, the first address decoding unit and the second decoding unit corresponding to the selected memory cell are opened, so that the source electrode and the drain electrode of the memory cell can be respectively connected to the control module and the power supply voltage.
The embodiment further provides a method for reading a dual split gate flash memory, where the method for reading a memory cell by using the dual split gate flash memory circuit includes:
firstly, the level of a second bit line is precharged to a power supply voltage, wherein the second bit line is connected with a drain electrode of a storage unit, namely the level of the drain electrode of the storage unit is precharged to the power supply voltage;
then, a pre-charge unit of a control module is used for pre-charging the level of a first bit line to the output voltage of the pre-charge unit, and a reset unit is used for resetting the level of a first node, so that the initial potential of the first node is close to zero potential, after the pre-charge unit and the reset unit act together and reach balance, the levels of the first bit line and the first node are pre-charged to a first reference voltage, wherein one end of the pre-charge unit can be pre-charged to a power supply voltage, the other end of the pre-charge unit is connected with the first bit line, the output voltage of the pre-charge unit can be the difference between the power supply voltage and the internal loss voltage of the pre-charge unit, in addition, a first reference voltage VREF1 is smaller than the power supply voltage applied to a second bit line, the first reference voltage is a smaller voltage applied to the first bit line by the control module, and the first reference voltage and the power supply voltage act together can enable a potential difference meeting the read operation, thereby causing a read signal to be generated within the memory cell;
then, executing a read operation, wherein when a storage signal of the storage unit is at a high level, a read signal output by the storage unit, namely, an output current, is large, so that a voltage of a first bit line is higher than a first reference voltage, a first comparison unit compares the voltage of the first bit line with the first reference voltage and outputs a switch control signal to turn on a switch unit, the voltage of a first node is higher than the first reference voltage, and the first reference voltage is set to be larger than a second reference voltage, a second comparison unit compares the voltage of the first node with the second reference voltage and outputs a read signal at a high level, and the level of the read signal is consistent with the level of the storage signal of the storage unit;
when the storage signal of the storage unit is in a low level, the output current of the readout signal output by the storage unit is small, so that the voltage of the first bit line is lower than a first reference voltage, the first comparison unit compares the voltage of the first bit line with the first reference voltage and outputs the switch control signal to turn off the switch unit, the bias unit pulls down the potential of the first node (to 0 potential) to make the voltage of the first node lower than the second reference voltage, the second comparison unit compares the voltage of the first node with the second reference voltage and outputs the readout signal in the low level, and the level of the readout signal is consistent with the level of the storage signal of the storage unit.
Specifically, the power voltage in the reading method of the dual split gate flash memory of the embodiment may be 1V to 1.4V. The method for reading a dual split gate flash memory according to this embodiment may further include turning on a first address decoding unit and a second address decoding unit corresponding to the memory cell by using an externally input address signal, and then performing a read operation on the memory cell, where the first address decoding unit is connected to the power supply voltage and the second bit line, and the second address decoding unit is connected to the first bit line and the control module.
The method for reading the dual-split-gate flash memory mainly uses the dual-split-gate flash memory circuit to read the memory cell, and because the dual-split-gate flash memory circuit can perform read operation under the condition that the control module does not need to be provided with the NZ tube, the method for reading the dual-split-gate flash memory circuit can also perform read operation on the memory cell under the condition that the control module is not provided with the NZ tube, and the manufacturing cost of the dual-split-gate flash memory device can be reduced. In addition, because the second bit line of the double-separation-gate flash memory circuit is precharged to the power supply voltage, the control module only needs to apply smaller voltage to the first bit line, and under the combined action of the power supply voltage and the smaller voltage applied by the control module, the potential difference meeting the reading operation requirement can be generated between the source electrode and the drain electrode of the storage unit, so that the operation space of the control module for applying the voltage to the first bit line is larger, and the operation window when the control module performs the reading operation on the storage unit can be enlarged, namely the reading operation window of the storage unit is enlarged.
The present embodiment additionally provides a memory device including the above dual split gate flash memory circuit. A dual split gate flash memory circuit in the memory device includes a memory cell having a source electrode connected to a first bit line and a drain electrode connected to a second bit line, and a control module for obtaining a read signal of the memory cell, the control module being electrically connected to the first bit line to obtain the read signal, the second bit line being precharged to a power supply voltage when a read operation is performed on the memory cell so that the drain electrode is at a positive potential with respect to the source electrode. Therefore, the memory device can also perform read operation without setting an NZ tube in a control module like the dual split gate flash memory circuit, so that a layer of photomask can be omitted when the memory device is manufactured, and the manufacturing cost of the memory device can be reduced. Meanwhile, the memory device can also increase an operation window when the control module performs read operation on the memory cell, namely, increase the read operation window of the memory cell.
The above description is only for the purpose of describing the preferred embodiments of the present invention and is not intended to limit the scope of the claims of the present invention, and any person skilled in the art can make possible the variations and modifications of the technical solutions of the present invention using the methods and technical contents disclosed above without departing from the spirit and scope of the present invention, and therefore, any simple modification, equivalent change and modification made to the above embodiments according to the technical essence of the present invention belong to the protection scope of the technical solutions of the present invention.
Claims (10)
1. A dual split gate flash memory circuit comprising a memory cell and a control module for obtaining a read signal from said memory cell, said memory cell having a source electrode and a drain electrode, and said source electrode being connected to a first bit line and said drain electrode being connected to a second bit line, said control module being electrically connected to said first bit line for obtaining said read signal, the level of said second bit line being precharged to a supply voltage during a read operation performed on said memory cell to make said drain electrode at a positive potential with respect to said source electrode.
2. The dual split gate flash memory circuit of claim 1, wherein the control module comprises:
a pre-charging unit for pre-charging an initial potential of the first bit line to a first reference voltage;
a first comparing unit for comparing a voltage of the first bit line with the first reference voltage and outputting a switching control signal when a read operation is performed on the memory cell;
the switch unit is used for being turned on or turned off according to the switch control signal output by the first comparison unit, one end of the switch unit is connected with the first bit line, and the other end of the switch unit is connected with a first node;
the signal output end of the bias unit is connected with the first node and used for pulling down the potential of the first node when the switch unit is not opened;
the reset unit is used for receiving a reset signal and resetting the potential of the first node to enable the initial potential of the first node to be close to zero potential;
and a second comparing unit for comparing the voltage of the first node with a second reference voltage and outputting a sensing signal when a read operation is performed on the memory cell.
3. The dual split gate flash memory circuit of claim 2, wherein the precharge unit comprises an NMOS transistor having one end connected to a power supply voltage and the other end connected to the first bit line.
4. The dual split gate flash memory circuit of claim 2, wherein the switching unit is selected from one of a PMOS transistor, an NMOS transistor, a triode, a JFET, and an IGBT.
5. The dual split gate flash memory circuit of any of claims 1 or 2, wherein the power supply voltage is 1V to 1.4V.
6. The dual split gate flash memory circuit of any of claims 1 or 2, further comprising:
the first address decoding unit is connected with the output end of the power supply voltage and the second bit line and used for forming a switch control signal between the output end of the power supply voltage and the second bit line according to an externally input address signal; and
and the second address decoding unit is connected with the output end of the first bit line and the control module and is used for forming a switch control signal between the output end of the first bit line and the control module according to an externally input address signal.
7. The dual split gate flash memory circuit of claim 6, wherein the first address decoding unit and the second address decoding unit each comprise a plurality of MOS transistors connected in series.
8. The dual split gate flash memory circuit of claim 7, wherein the first address decoding unit comprises a plurality of series connected PMOS transistors and the second address decoding unit comprises a plurality of series connected NMOS transistors.
9. A method for reading a dual split gate flash memory, using the dual split gate flash memory circuit of claims 2-8, the method comprising:
precharging a level of the second bit line to a power supply voltage;
the level of a first bit line is precharged to the output voltage of the precharging unit by using a precharging unit of the control module, the first node is subjected to potential resetting by using the resetting unit, the initial potential of the first node is close to zero potential, and the levels of the first bit line and the first node are precharged to a first reference voltage after the precharging unit and the resetting unit act together and reach balance; and
a read operation is performed in which, among other things,
when a storage signal of a memory cell is at a high level, a voltage of the first bit line is higher than the first reference voltage, the first comparing unit compares the voltage of the first bit line with the first reference voltage and outputs a switch control signal to turn on the switching unit and the voltage of the first node is higher than the first reference voltage, the first reference voltage is set to be higher than a second reference voltage, and the second comparing unit compares the voltage of the first node with the second reference voltage and outputs the read signal at a high level;
when a storage signal of the memory cell is at a low level, the voltage of the first bit line is lower than the first reference voltage, the first comparison unit compares the voltage of the first bit line with the first reference voltage and outputs the switch control signal to turn off the switch unit, the bias unit pulls down the potential of the first node to make the voltage of the first node lower than the second reference voltage, and the second comparison unit compares the voltage of the first node with the second reference voltage and outputs the read signal at a low level.
10. A memory device comprising the dual split gate flash memory circuit of any of claims 1 to 8.
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