CN102426845B - Current mode sensitive amplifier - Google Patents
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- CN102426845B CN102426845B CN2011103913906A CN201110391390A CN102426845B CN 102426845 B CN102426845 B CN 102426845B CN 2011103913906 A CN2011103913906 A CN 2011103913906A CN 201110391390 A CN201110391390 A CN 201110391390A CN 102426845 B CN102426845 B CN 102426845B
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Abstract
The invention discloses a current mode sensitive amplifier, which can use a feedback clamping circuit to provide stable bias voltage for a storage unit so as to obtain stable transmission current flowing through the storage unit, and input the current into a current comparison amplifier so as to compare the current with the current obtained from a reference storage unit and output a comparison result. The current comparison amplifier of the invention uses the accelerated response circuit to accelerate the charging speed of the parasitic capacitance at the output end of the current comparison amplifier, thereby effectively improving the reading speed of data.
Description
Technical field
The present invention relates to the memory technology field, particularly relate to a kind of ATD-assisted current sense amplifier.
Background technology
Sense amplifier is one of read path Key Circuit of storer, and its effect is read and compared with the output of reference memory unit storage unit, output judged result (logical zero or logical one).According to principle of work, sense amplifier is divided into two kinds of voltage-mode and current-mode, and their input signal is respectively voltage and the magnitude of current.
Wherein, ATD-assisted current sense amplifier (AACSA) is the circuit of a kind of low supply voltage, high response speed and low-power consumption, it carries out pre-punching and the electric discharge of electric current by address mapping converter (ATD, Address Transition Detector) the clock control bit line provided.Because the current ratio of ATD-assisted current sense amplifier is to carry out the current-voltage conversion than process nature, its complete comparison required time and comparative degree output node place stray capacitance to discharge and recharge the time proportional.In some cases, deviation due to technique, can make the characteristic of storage unit influenced, if transform less than normal to the charging and discharging currents of virtual stray capacitance after the sense amplifier sampling, for traditional ATD-assisted current sense amplifier, need the longer time of cost to complete the current-voltage transfer process, be unfavorable for reading fast of data.
Summary of the invention
For solving the problems of the technologies described above, the embodiment of the present invention provides a kind of ATD-assisted current sense amplifier, the speed read to improve data, and technical scheme is as follows:
A kind of ATD-assisted current sense amplifier, be applied to storer, comprising: feedback-clamp circuit, electric current comparison amplifier and booster response circuit,
The input end of described feedback-clamp circuit is connected with the storage unit floating-gate pipe, stablize bias voltage to obtain the stable transmission current of this storage unit of flowing through for storage unit provides, and by output terminal, described transmission current is inputted to the in-phase input end of described electric current comparison amplifier;
The inverting input of described electric current comparison amplifier is connected with reference memory unit, for the size of the electric current relatively obtained from described reference memory unit and the electric current obtained from described feedback-clamp circuit, and exports comparative result by output terminal;
Described booster response circuit is connected with the output terminal of electric current comparison amplifier, for accelerating the electric current comparison procedure of electric current comparison amplifier.
Preferably, this ATD-assisted current sense amplifier also comprises: the output Shaping circuit, for described difference between current signal is carried out to shaping, the input end of described output Shaping circuit is connected with the output terminal of described electric current comparison amplifier, and the output terminal of described output Shaping circuit is for the difference between current signal after output Shaping.
Preferably, described feedback-clamp circuit comprises: the first phase inverter, the 2nd NMOS pipe and NMOS pipe,
The input end of described the first phase inverter is connected with the source electrode of described the 2nd NMOS pipe, and output terminal is connected with the grid of described the 2nd NMOS pipe; The output terminal that the drain electrode of described the 2nd NMOS pipe is described feedback-clamp circuit, the input end that source electrode is described feedback-clamp circuit and being connected with the drain electrode of described storage unit floating-gate pipe; The drain electrode of a described NMOS pipe is connected with power supply, and grid is inputted a precharging signal, with the drain electrode of controlling described storage unit floating-gate pipe, quickly charges to the clamper current potential, and source electrode is connected with the source electrode of described the 2nd NMOS pipe.
Preferably, described electric current comparison amplifier comprises:
The one PMOS pipe, the 2nd PMOS pipe, the 3rd NMOS pipe and the 8th NMOS pipe,
The in-phase input end that the drain electrode of a described PMOS pipe is described electric current comparison amplifier, source electrode is connected with power supply, and grid drains and is connected with self; The grid of the grid of described the 2nd PMOS pipe and a described PMOS pipe links together, and source electrode is connected with power supply, and drain electrode is connected with the drain electrode of the 3rd NMOS pipe; A described PMOS pipe and described the 2nd PMOS pipe form current mirror circuit, and the current signal that a described PMOS pipe drain electrode is obtained is mirrored to the drain electrode of described the 2nd PMOS pipe;
The inverting input that the drain electrode of described the 8th NMOS pipe is described electric current comparison amplifier, be connected with reference memory unit, obtains the electric current flowed out in reference memory unit, the source ground of described the 8th NMOS pipe, and grid is connected with the drain electrode of self; The grid of described the 3rd NMOS pipe is connected with the grid of described the 8th NMOS pipe, form current mirror circuit, the drain electrode of for the current mirror that described the 8th NMOS pipe drain electrode is obtained, arriving described the 3rd NMOS pipe, the source ground of described the 3rd NMOS pipe, drain electrode is connected with the drain electrode of described the 2nd PMOS pipe, tie point is common point A, for the drain current at more described the 2nd PMOS pipe in common point A place and the drain current of described the 3rd NMOS pipe, and by common point A output comparative result;
There is an equivalent stray capacitance between described common point A and ground, for following described comparative result, discharged and recharged, when the drain current of described the 2nd PMOS pipe is greater than the drain current of described the 3rd NMOS pipe, described stray capacitance is charged, when the drain current of described the 2nd PMOS pipe is less than the drain current of described the 3rd NMOS pipe, described stray capacitance is discharged.
Preferably, described booster response circuit comprises: the 3rd PMOS pipe, the 4th PMOS pipe, the 4th NMOS pipe, the 5th NMOS pipe, the 6th NMOS pipe, the 7th NMOS pipe and the 4th phase inverter,
The drain electrode of described the 3rd PMOS pipe is connected with described common point A, and source electrode is connected with described power supply, and grid is connected with the drain electrode of the 4th PMOS pipe;
The grid of described the 4th PMOS pipe is connected with the drain electrode of described the 2nd PMOS pipe, and source electrode is connected with power supply;
The drain electrode of described the 7th NMOS pipe is connected with the drain electrode of described the 3rd PMOS pipe, source ground, and grid is connected with the input end of described the 4th phase inverter;
The output terminal of described the 4th phase inverter is connected with the grid of described the 6th NMOS pipe;
The drain electrode of described the 6th NMOS pipe is connected with a current source, and source electrode is connected with the grid of described the 5th NMOS pipe and the drain electrode of described the 5th NOMS pipe;
The grid of described the 5th NMOS pipe also is connected with the grid of described the 4th NMOS pipe, the source ground of described the 5th NOMS pipe, and described the 5th NMOS pipe forms current mirror circuit with described the 4th NMOS pipe;
The source ground of described the 4th NMOS pipe, drain electrode is connected with the grid of described the 3rd PMOS pipe.
Preferably, described output Shaping circuit comprises: the second phase inverter and the 3rd phase inverter,
The input end that the input end of described the second phase inverter is described output Shaping circuit, the output terminal of described the second phase inverter is connected with the input end of described the 3rd phase inverter, the output terminal that the output terminal of described the 3rd phase inverter is described output Shaping circuit.
The technical scheme that the embodiment of the present invention provides, can use feedback-clamp circuit to stablize the stable transmission current of bias voltage with this storage unit that obtains flowing through for storage unit provides, and, by described electric current input current comparison amplifier, with the electric current with obtaining from reference memory unit, compare and export comparative result.Accelerate current ratio than the charging rate of amplifier out stray capacitance because electric current comparison amplifier of the present invention has been used the booster response circuit, and then accelerated the electric current comparison procedure, therefore can effectively improve the reading speed of data.
The accompanying drawing explanation
In order to be illustrated more clearly in the embodiment of the present invention or technical scheme of the prior art, below will the accompanying drawing of required use in embodiment or description of the Prior Art be briefly described, apparently, accompanying drawing in the following describes is only some embodiments of the present invention, for those of ordinary skills, under the prerequisite of not paying creative work, can also obtain according to these accompanying drawings other accompanying drawing.
The circuit diagram of a kind of ATD-assisted current sense amplifier that Fig. 1 provides for the embodiment of the present invention;
The circuit diagram of the another kind of ATD-assisted current sense amplifier that Fig. 2 provides for the embodiment of the present invention;
The circuit diagram of the another kind of ATD-assisted current sense amplifier that Fig. 3 provides for the embodiment of the present invention.
Embodiment
Below in conjunction with the accompanying drawing in the embodiment of the present invention, the technical scheme in the embodiment of the present invention is clearly and completely described, obviously, described embodiment is only the present invention's part embodiment, rather than whole embodiment.Embodiment based in the present invention, those of ordinary skills, not making under the creative work prerequisite the every other embodiment obtained, belong to the scope of protection of the invention.
As shown in Figure 1, a kind of ATD-assisted current sense amplifier that the embodiment of the present invention provides, be applied to storer, comprising: feedback-clamp circuit 100, booster response circuit 200 and electric current comparison amplifier 300.
The input end of feedback-clamp circuit 100 is connected with storage unit 400 floating-gate pipes, for storage unit 400 provides, stablizes the stable transmission current I of bias voltage with this storage unit 400 that obtains flowing through
MC, and by output terminal by described transmission current I
MCThe in-phase input end of input current comparison amplifier 300;
Feedback-clamp circuit 100 is a kind of circuit that are usually used in fixed voltage, and the present invention no longer describes at this.The inverting input of electric current comparison amplifier 300 is connected with reference memory unit 500, for the electric current I relatively obtained from reference memory unit 500
MRCWith the electric current I obtained from feedback-clamp circuit 100
MCSize, and export comparative result by output terminal.
Wherein, will be designated as I from the electric current of feedback-clamp circuit 100 inflow current comparison amplifiers 300
MC, from the electric current of reference memory unit 500 inflow current comparison amplifiers 300, be designated as I
MRC.Work as I
MCBe greater than I
MRCThe time, electric current comparison amplifier 300 perceives difference between current, and its output is judged to be logic ' 1 ', starts stray capacitance is charged.Work as I
MCBe less than I
MRCThe time, electric current comparison amplifier 300 perceives difference between current, and its output is judged to be logic ' 0 ', and stray capacitance starts to be discharged.
Described booster response circuit 200, be connected with the output terminal of electric current comparison amplifier 300, for accelerating the electric current comparison procedure of electric current comparison amplifier 300.
Work as I
MCBe greater than I
MRCThe time, booster response circuit 200 is that stray capacitance is charged by electric current comparison amplifier 300 output terminals, shortens its charging process, can effectively reduce the electric current comparison procedure.
A kind of ATD-assisted current sense amplifier that the embodiment of the present invention provides, can use feedback-clamp circuit to stablize the stable transmission current of bias voltage with this storage unit that obtains flowing through for storage unit provides, and, by described electric current input current comparison amplifier, with the electric current with obtaining from reference memory unit, compare and export comparative result.Accelerate current ratio than the charging rate of amplifier out stray capacitance because electric current comparison amplifier of the present invention has been used the booster response circuit, therefore can effectively improve the reading speed of data.
As shown in Figure 2, the another kind of ATD-assisted current sense amplifier that the embodiment of the present invention provides, also comprise: output Shaping circuit 600, for described difference between current signal is carried out to shaping, the input end of output Shaping circuit 600 is connected with the output terminal of electric current comparison amplifier 300, and the output terminal of output Shaping circuit 600 is for the difference between current signal after output Shaping.
It will be appreciated by persons skilled in the art that output Shaping circuit 600 can carry out the waveform arrangement to exported signal, make its level value more meet standard digital logic ' 0 ', ' 1 ' value.Wherein, output Shaping circuit 600 can be comprised of two phase inverters that are cascaded, and carries out respectively the processing of analog to digital conversion and increase driving force.
As shown in Figure 3, in the another kind of ATD-assisted current sense amplifier that the embodiment of the present invention provides, feedback-clamp circuit 100 comprises: the first phase inverter I1, the 2nd NMOS pipe NM2 and NMOS pipe NM1, the input end of the first phase inverter I1 is connected with the source electrode of the 2nd NMOS pipe NM2, the output terminal of the first phase inverter I1 is connected with the grid of the 2nd NMOS pipe NM2, the output terminal that the drain electrode of the 2nd NMOS pipe NM2 is feedback-clamp circuit 100, the input end that the source electrode of the 2nd NMOS pipe NM2 is feedback-clamp circuit 100, with the drain electrode of metal-oxide-semiconductor MC in storage unit, be connected, the drain electrode of the one NMOS pipe NM1 is connected with power supply VDD, the grid of the one NMOS pipe NM1 is inputted a precharging signal SA_PC, drain electrode with control store unit floating-gate pipe quickly charges to the clamper current potential, the source electrode of the one NMOS pipe NM1 is connected with the source electrode of the 2nd NMOS pipe NM2.
Electric current comparison amplifier 300 comprises:
The one PMOS pipe PM1, the 2nd PMOS pipe PM2, the 3rd NMOS pipe NM3 and the 8th NMOS pipe NM8.
The in-phase input end that the drain electrode of a described PMOS pipe PM1 is described electric current comparison amplifier, source electrode is connected with power supply, and grid drains and is connected with self; The grid of the grid of described the 2nd PMOS pipe PM2 and a described PMOS pipe PM1 links together, and source electrode is connected with power supply, and drain electrode is connected with the drain electrode of the 3rd NMOS pipe NM3; A described PMOS pipe PM1 and described the 2nd PMOS pipe PM2 form current mirror circuit, and the current signal that a described PMOS pipe PM1 drain electrode is obtained is mirrored to the drain electrode of described the 2nd PMOS pipe PM2.
The inverting input that the drain electrode of described the 8th NMOS pipe NM8 is described electric current comparison amplifier, be connected with reference memory unit, obtains the electric current flowed out in reference memory unit, the source ground of described the 8th NMOS pipe NM8, and grid is connected with the drain electrode of self; The grid of described the 3rd NMOS pipe NM3 is connected with the grid of described the 8th NMOS pipe NM8, form current mirror circuit, the drain electrode of for the current mirror that described the 8th NMOS pipe NM8 drain electrode is obtained, arriving described the 3rd NMOS pipe NM3, the source ground of described the 3rd NMOS pipe NM3, drain electrode is connected with the drain electrode of described the 2nd PMOS pipe PM2, tie point is common point A, for the drain current of more described the 2nd PMOS pipe PM2 at common point A place and the drain current of described the 3rd NMOS pipe NM3, and by common point A output comparative result.
There is an equivalent stray capacitance C between described common point A and ground
pFor following described comparative result, discharged and recharged, when the drain current of described the 2nd PMOS pipe PM2 is greater than the drain current of described the 3rd NMOS pipe NM3, described stray capacitance is charged, when the drain current of described the 2nd PMOS pipe PM2 is less than the drain current of described the 3rd NMOS pipe NM3, described stray capacitance is discharged.
It will be appreciated by persons skilled in the art that equivalent stray capacitance C
pBe that virtual link is between described common point A and ground in actual applications.
Electric current comparison amplifier 300 is obtained respectively the electric current I of storage unit MC by in-phase end and end of oppisite phase sampling
MCElectric current I with reference memory unit
MRC, and as two input signals of electric current comparison amplifier 300.By the current mirror action of a PMOS pipe PM1 and the 2nd PMOS pipe PM2, the 3rd NMOS pipe NM3 and the 8th NMOS pipe NM8, the 2nd NMOS pipe PM2 and the 3rd NMOS pipe NM3 carry out I
MCAnd I
MRCComparison, comparative result is converted into voltage signal at common point A.Work as I
MCI
MRCThe time, known according to the current balance type principle, 300 pairs of stray capacitance Cp chargings of electric current comparison amplifier, the 2nd PMOS pipe PM2 finally enters linear zone, and now its drain-source voltage is very little, and the A point voltage is cashed as approaching the noble potential of VDD, i.e. output logic " 1 ".Work as I
MC<I
MRCThe time, known according to the current balance type principle, 300 pairs of stray capacitance Cp electric discharges of electric current comparison amplifier, the 3rd NMOS pipe NM3 finally enters linear zone, and now its drain-source voltage is very little, and the A point voltage is cashed as approaching 0 electronegative potential, i.e. output logic " 0 ".
Described the 3rd PMOS pipe PM3, the 4th PMOS pipe PM4, the 4th NMOS pipe NM4, the 5th NMOS pipe NM5, the 6th NMOS pipe NM6, the 7th NMOS pipe NM7 and the 4th phase inverter I4.
The drain electrode of described the 3rd PMOS pipe PM3 is connected with described common point A, and source electrode is connected with described power supply, and grid is connected with the drain electrode of the 4th PMOS pipe PM4, and tie point is common point B.
The grid of described the 4th PMOS pipe PM4 is connected with the drain electrode of described the 2nd PMOS pipe PM2, and source electrode is connected with power supply.
The drain electrode of described the 7th NMOS pipe NM7 is connected with the drain electrode of described the 3rd PMOS pipe PM3, source ground, and grid is connected with the input end of described the 4th phase inverter I4.
The output terminal of described the 4th phase inverter I4 is connected with the grid of described the 6th NMOS pipe NM6.
The drain electrode of described the 6th NMOS pipe NM6 is connected with a current source I5, and source electrode is connected with the grid of described the 5th NMOS pipe NM5 and the drain electrode of described the 5th NOMS pipe NM5.
The grid of described the 5th NMOS pipe NM5 also is connected with the grid of described the 4th NMOS pipe NM4, the source ground of described the 5th NOMS pipe NM5.
The source ground of described the 4th NMOS pipe NM4, drain electrode is connected with the grid of described the 3rd PMOS pipe PM3.
Wherein, the grid of the 7th NMOS pipe NM7 and the input end of the 4th phase inverter I4 are inputted a control signal SA_PC, and whether the work of SA_PC control booster response circuit 200.
Easily be understood that, before data being read and judge, need at first carry out the precharge to storage unit 400 bit lines, make bit-line voltage reach predetermined clamp voltage.Between precharge phase, a NMOS pipe NM1 carries out the preliminary filling processing to the output terminal of feedback-clamp circuit 100, makes this terminal voltage reach rapidly predetermined clamp voltage.After precharge finishes, enter reading and decision stage of data, namely between non-precharge phase.
At electric current comparison amplifier 300, carry out between precharge phase, SA_PC is high level, by the 4th phase inverter I4, makes the 6th NMOS pipe NM6 cut-off, the electric current I of blocking-up current source I5
PULL, booster response circuit 200 is in off position.Simultaneously, the 7th NMOS pipe NM7 conducting, make zero the current potential of common point A, therefore the 4th PMOS pipe PM4 conducting, and the electric current of the source electrode of the 4th PMOS pipe PM4 that flows through is I
PM4, make B point current potential be placed in high level, the output signal SA_OUT perseverance of ultimate current comparison amplifier 300 is low level.
In the non-preliminary filling stage, SA_PC is low level, the electric current I that current source I5 produces
PULLBy the 6th NMOS pipe NM6, the 5th NMOS pipe NM5, to ground, the 4th NMOS pipe NM4 mirror image flows through the electric current of the 5th NMOS pipe NM5, and booster response circuit 200 is in effective duty.
Considering Dynamic Processes, after the preliminary filling stage finishes, electric current comparison amplifier 300 enters reading of data and decision stage.If what the storage element MC be read deposited is logical data " 0 ", just I is arranged
MC<I
MRC, according to the principle of work of electric current comparison amplifier 300, the output of A point should remain low level.Due to before relatively and the A point current potential relatively there is no the conversion of occurrence logic state, do not have the transformation process of establishing of signal, also just do not need to accelerate intervention.
If what the storage element MC be read deposited is logical data " 1 ", just I is arranged
MCI
MRC, according to the principle of work of electric current comparison amplifier 300, the output of A point should be high level.So, in comparison procedure, stray capacitance Cp being charged, A point current potential rises gradually, and the gate source voltage of the 4th PMOS pipe PM4 reduces gradually, and the current potential of common point B descends gradually.When B point current potential, during lower than a threshold voltage of VDD, the 3rd PMOS pipe PM3 starts conducting, and with electric current I
PM3Stray capacitance Cp is carried out to auxiliary charging, accelerated the charging process of stray capacitance Cp, make the A point reach quickly the trigging signal of phase inverter I2, complete and judge and export.
A kind of ATD-assisted current sense amplifier that the embodiment of the present invention provides, can use feedback-clamp circuit to stablize the stable transmission current of bias voltage with this storage unit that obtains flowing through for storage unit provides, and, by described electric current input current comparison amplifier, with the electric current with obtaining from reference memory unit, compare and export comparative result.Accelerate current ratio than the charging rate of amplifier out stray capacitance because electric current comparison amplifier of the present invention has been used the booster response circuit, therefore can effectively improve the reading speed of data.
It should be noted that, in this article, relational terms such as the first and second grades only is used for an entity or operation are separated with another entity or operational zone, and not necessarily requires or imply between these entities or operation the relation of any this reality or sequentially of existing.
The above is only the application's embodiment; it should be pointed out that for those skilled in the art, under the prerequisite that does not break away from the application's principle; can also make some improvements and modifications, these improvements and modifications also should be considered as the application's protection domain.
Claims (6)
1. an ATD-assisted current sense amplifier, be applied to storer, it is characterized in that, comprising: feedback-clamp circuit, electric current comparison amplifier and booster response circuit,
The input end of described feedback-clamp circuit is connected with the storage unit floating-gate pipe, stablize bias voltage to obtain the stable transmission current of this storage unit of flowing through for storage unit provides, and by output terminal, described transmission current is inputted to the in-phase input end of described electric current comparison amplifier;
The inverting input of described electric current comparison amplifier is connected with reference memory unit, for the size of the electric current relatively obtained from described reference memory unit and the electric current obtained from described feedback-clamp circuit, and exports comparative result by output terminal;
Described booster response circuit is connected with the output terminal of electric current comparison amplifier, for accelerating current ratio than the charging rate of amplifier out stray capacitance, accelerates the electric current comparison procedure of electric current comparison amplifier.
2. ATD-assisted current sense amplifier according to claim 1, it is characterized in that, also comprise: the output Shaping circuit, for the difference between current signal is carried out to shaping, the input end of described output Shaping circuit is connected with the output terminal of described electric current comparison amplifier, and the output terminal of described output Shaping circuit is for the difference between current signal after output Shaping.
3. ATD-assisted current sense amplifier according to claim 1 and 2, is characterized in that, described feedback-clamp circuit comprises: the first phase inverter, the 2nd NMOS pipe and NMOS pipe,
The input end of described the first phase inverter is connected with the source electrode of described the 2nd NMOS pipe, and output terminal is connected with the grid of described the 2nd NMOS pipe; The output terminal that the drain electrode of described the 2nd NMOS pipe is described feedback-clamp circuit, the input end that source electrode is described feedback-clamp circuit and being connected with the drain electrode of described storage unit floating-gate pipe; The drain electrode of a described NMOS pipe is connected with power supply, and grid is inputted a precharging signal, with the drain electrode of controlling described storage unit floating-gate pipe, quickly charges to the clamper current potential, and source electrode is connected with the source electrode of described the 2nd NMOS pipe.
4. ATD-assisted current sense amplifier according to claim 1 and 2, is characterized in that, described electric current comparison amplifier comprises:
The one PMOS pipe, the 2nd PMOS pipe, the 3rd NMOS pipe and the 8th NMOS pipe,
The in-phase input end that the drain electrode of a described PMOS pipe is described electric current comparison amplifier, source electrode is connected with power supply, and grid drains and is connected with self; The grid of the grid of described the 2nd PMOS pipe and a described PMOS pipe links together, and source electrode is connected with power supply, and drain electrode is connected with the drain electrode of the 3rd NMOS pipe; A described PMOS pipe and described the 2nd PMOS pipe form current mirror circuit, and the current signal that a described PMOS pipe drain electrode is obtained is mirrored to the drain electrode of described the 2nd PMOS pipe;
The inverting input that the drain electrode of described the 8th NMOS pipe is described electric current comparison amplifier, be connected with reference memory unit, obtains the electric current flowed out in reference memory unit, the source ground of described the 8th NMOS pipe, and grid is connected with the drain electrode of self; The grid of described the 3rd NMOS pipe is connected with the grid of described the 8th NMOS pipe, form current mirror circuit, the drain electrode of for the current mirror that described the 8th NMOS pipe drain electrode is obtained, arriving described the 3rd NMOS pipe, the source ground of described the 3rd NMOS pipe, drain electrode is connected with the drain electrode of described the 2nd PMOS pipe, tie point is common point A, for the drain current at more described the 2nd PMOS pipe in common point A place and the drain current of described the 3rd NMOS pipe, and by common point A output comparative result;
There is an equivalent stray capacitance between described common point A and ground, for following described comparative result, discharged and recharged, when the drain current of described the 2nd PMOS pipe is greater than the drain current of described the 3rd NMOS pipe, described stray capacitance is charged, when the drain current of described the 2nd PMOS pipe is less than the drain current of described the 3rd NMOS pipe, described stray capacitance is discharged.
5. ATD-assisted current sense amplifier according to claim 4, is characterized in that, described booster response circuit comprises: the 3rd PMOS pipe, the 4th PMOS pipe, the 4th NMOS pipe, the 5th NMOS pipe, the 6th NMOS pipe, the 7th NMOS pipe and the 4th phase inverter,
The drain electrode of described the 3rd PMOS pipe is connected with described common point A, and source electrode is connected with described power supply, and grid is connected with the drain electrode of the 4th PMOS pipe;
The grid of described the 4th PMOS pipe is connected with the drain electrode of described the 2nd PMOS pipe, and source electrode is connected with power supply;
The drain electrode of described the 7th NMOS pipe is connected with the drain electrode of described the 3rd PMOS pipe, source ground, and grid is connected with the input end of described the 4th phase inverter;
The output terminal of described the 4th phase inverter is connected with the grid of described the 6th NMOS pipe;
The drain electrode of described the 6th NMOS pipe is connected with a current source, and source electrode is connected with the grid of described the 5th NMOS pipe and the drain electrode of described the 5th NMOS pipe;
The grid of described the 5th NMOS pipe also is connected with the grid of described the 4th NMOS pipe, the source ground of described the 5th NOMS pipe, and described the 5th NMOS pipe forms current mirror circuit with described the 4th NMOS pipe;
The source ground of described the 4th NMOS pipe, drain electrode is connected with the grid of described the 3rd PMOS pipe.
6. ATD-assisted current sense amplifier according to claim 2, is characterized in that, described output Shaping circuit comprises: the second phase inverter and the 3rd phase inverter,
The input end that the input end of described the second phase inverter is described output Shaping circuit, the output terminal of described the second phase inverter is connected with the input end of described the 3rd phase inverter, the output terminal that the output terminal of described the 3rd phase inverter is described output Shaping circuit.
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| CN2011103913906A CN102426845B (en) | 2011-11-30 | 2011-11-30 | Current mode sensitive amplifier |
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| CN104681053B (en) * | 2013-11-27 | 2017-09-05 | 苏州东微半导体有限公司 | A kind of Current-type sensitive amplifier circuit for being applied to half floating gate memory cell |
| CN105719679B (en) * | 2014-12-01 | 2018-02-02 | 中国科学院微电子研究所 | Sensitive amplifier and signal processing method |
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| CN1845253A (en) * | 2006-04-28 | 2006-10-11 | 清华大学 | Sensitive amplifier circuit for quickflashing memory |
| CN102081959A (en) * | 2009-11-26 | 2011-06-01 | 中国科学院微电子研究所 | Memory reading circuit and memory |
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| JPH0782758B2 (en) * | 1987-03-16 | 1995-09-06 | 株式会社日立製作所 | Semiconductor memory device |
| JP2003173700A (en) * | 2001-12-03 | 2003-06-20 | Mitsubishi Electric Corp | Semiconductor memory |
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Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1845253A (en) * | 2006-04-28 | 2006-10-11 | 清华大学 | Sensitive amplifier circuit for quickflashing memory |
| CN102081959A (en) * | 2009-11-26 | 2011-06-01 | 中国科学院微电子研究所 | Memory reading circuit and memory |
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| Title |
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| JP昭63-225998A 1988.09.20 |
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