CN102426845B - Current mode sensitive amplifier - Google Patents

Abstract

The invention discloses a current mode sensitive amplifier, which can use a feedback clamping circuit to provide stable bias voltage for a storage unit so as to obtain stable transmission current flowing through the storage unit, and input the current into a current comparison amplifier so as to compare the current with the current obtained from a reference storage unit and output a comparison result. The current comparison amplifier of the invention uses the accelerated response circuit to accelerate the charging speed of the parasitic capacitance at the output end of the current comparison amplifier, thereby effectively improving the reading speed of data.

Description

A Current Mode Sensitive Amplifier

technical field

The invention relates to the technical field of memory, in particular to a current mode sensitive amplifier.

Background technique

The sense amplifier is one of the key circuits in the read path of the memory. Its function is to read the storage unit and compare it with the output of the reference storage unit, and output the judgment result (logic "0" or logic "1"). According to the working principle, the sensitive amplifier is divided into voltage mode and current mode, and their input signals are voltage and current respectively.

Among them, the current-mode sense amplifier (AACSA) is a circuit with low power supply voltage, high response speed and low power consumption. It performs current pre-charging through the clock control bit line provided by the address transition converter (ATD, Address Transition Detector). and discharge. Since the current comparison process of the current mode sense amplifier is essentially a current-voltage conversion, the time required to complete the comparison is proportional to the charge and discharge time of the parasitic capacitance at the output node of the comparison stage. In some cases, due to the deviation of the process, the characteristics of the memory cell will be affected. If the charge and discharge current converted to the virtual parasitic capacitance by the sense amplifier after sampling is too small, it will take a long time for the traditional current mode sense amplifier. It takes time to complete the current-voltage conversion process, which is not conducive to the rapid reading of data.

Contents of the invention

In order to solve the above technical problems, an embodiment of the present invention provides a current mode sense amplifier to improve the speed of data reading, the technical solution is as follows:

A current-mode sensitive amplifier applied to memory, including: a feedback clamp circuit, a current comparison amplifier and an accelerated response circuit,

The input terminal of the feedback clamping circuit is connected to the floating gate transistor of the storage unit, and provides a stable bias voltage for the storage unit to obtain a stable transmission current flowing through the storage unit, and the transmission current is input to the storage unit through the output terminal. The non-inverting input terminal of the current comparison amplifier;

The inverting input terminal of the current comparison amplifier is connected to the reference storage unit for comparing the magnitude of the current obtained from the reference storage unit with the current obtained from the feedback clamping circuit, and the comparison is output through the output terminal result;

The acceleration response circuit is connected with the output end of the current comparison amplifier, and is used for accelerating the current comparison process of the current comparison amplifier.

Preferably, the current mode sense amplifier further includes: an output shaping circuit for shaping the current difference signal, the input end of the output shaping circuit is connected to the output end of the current comparison amplifier, and the output shaping circuit The output terminal of the circuit is used to output the current difference signal after shaping.

Preferably, the feedback clamp circuit includes: a first inverter, a second NMOS transistor and a first NMOS transistor,

The input end of the first inverter is connected to the source of the second NMOS transistor, and the output end is connected to the gate of the second NMOS transistor; the drain of the second NMOS transistor is the feedback The output end of the clamping circuit, the source is the input end of the feedback clamping circuit and is connected to the drain of the floating gate transistor of the storage unit; the drain of the first NMOS transistor is connected to the power supply, and the gate A precharge signal is input to control the drain of the floating gate transistor of the storage unit to be quickly charged to a clamping potential, and the source is connected to the source of the second NMOS transistor.

Preferably, the current comparison amplifier includes:

the first PMOS transistor, the second PMOS transistor, the third NMOS transistor and the eighth NMOS transistor,

The drain of the first PMOS transistor is the non-inverting input terminal of the current comparison amplifier, the source is connected to the power supply, and the gate is connected to its own drain; the gate of the second PMOS transistor is connected to the first The gates of the PMOS transistors are connected together, the source is connected to the power supply, and the drain is connected to the drain of the third NMOS transistor; the first PMOS transistor and the second PMOS transistor form a current mirror circuit, and the The current signal obtained by the drain of the first PMOS transistor is mirrored to the drain of the second PMOS transistor;

The drain of the eighth NMOS transistor is the inverting input terminal of the current comparison amplifier, which is connected to the reference storage unit to obtain the current flowing out of the reference storage unit, the source of the eighth NMOS transistor is grounded, and the gate is connected to the reference storage unit. The drain of itself is connected; the gate of the third NMOS transistor is connected with the gate of the eighth NMOS transistor to form a current mirror circuit, which is used to mirror the current obtained by the drain of the eighth NMOS transistor to the The drain of the third NMOS transistor, the source of the third NMOS transistor is grounded, the drain is connected to the drain of the second PMOS transistor, and the connection point is a common point A, for comparing the drain current of the second PMOS transistor with the drain current of the third NMOS transistor, and outputting the comparison result through the common point A;

There is an equivalent parasitic capacitance between the common point A and the ground, which is used for charging and discharging following the comparison result, when the drain current of the second PMOS transistor is greater than the drain current of the third NMOS transistor , the parasitic capacitor is charged, and when the drain current of the second PMOS transistor is smaller than the drain current of the third NMOS transistor, the parasitic capacitor is discharged.

Preferably, the accelerated response circuit includes: a third PMOS transistor, a fourth PMOS transistor, a fourth NMOS transistor, a fifth NMOS transistor, a sixth NMOS transistor, a seventh NMOS transistor and a fourth inverter,

The drain of the third PMOS transistor is connected to the common point A, the source is connected to the power supply, and the gate is connected to the drain of the fourth PMOS transistor;

The gate of the fourth PMOS transistor is connected to the drain of the second PMOS transistor, and the source is connected to a power supply;

The drain of the seventh NMOS transistor is connected to the drain of the third PMOS transistor, the source is grounded, and the gate is connected to the input terminal of the fourth inverter;

The output end of the fourth inverter is connected to the gate of the sixth NMOS transistor;

The drain of the sixth NMOS transistor is connected to a current source, and the source is connected to the gate of the fifth NMOS transistor and the drain of the fifth NOMS transistor;

The gate of the fifth NMOS transistor is also connected to the gate of the fourth NMOS transistor, the source of the fifth NOMS transistor is grounded, and the fifth NMOS transistor and the fourth NMOS transistor form a current mirror circuit;

The source of the fourth NMOS transistor is grounded, and the drain is connected to the gate of the third PMOS transistor.

Preferably, the output shaping circuit includes: a second inverter and a third inverter,

The input end of the second inverter is the input end of the output shaping circuit, the output end of the second inverter is connected to the input end of the third inverter, and the third inverter The output end of the device is the output end of the output shaping circuit.

In the technical solution provided by the embodiment of the present invention, the feedback clamping circuit can be used to provide a stable bias voltage for the storage unit to obtain a stable transmission current flowing through the storage unit, and the current is input into the current comparison amplifier to compare with the current from The current acquired by the reference storage unit is compared and a comparison result is output. Because the current comparison amplifier of the present invention uses an accelerated response circuit to accelerate the charging speed of the parasitic capacitance at the output end of the current comparison amplifier, thereby speeding up the current comparison process, the reading speed of data can be effectively improved.

Description of drawings

In order to more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the following will briefly introduce the drawings that need to be used in the description of the embodiments or the prior art. Obviously, the accompanying drawings in the following description are only These are some embodiments of the present invention. For those skilled in the art, other drawings can also be obtained according to these drawings without any creative effort.

Fig. 1 is the circuit diagram of a kind of current mode sense amplifier that the embodiment of the present invention provides;

Fig. 2 is the circuit diagram of another kind of current mode sense amplifier that the embodiment of the present invention provides;

FIG. 3 is a circuit diagram of another current mode sense amplifier provided by an embodiment of the present invention.

Detailed ways

The following will clearly and completely describe the technical solutions in the embodiments of the present invention with reference to the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only some of the embodiments of the present invention, not all of them. Based on the embodiments of the present invention, all other embodiments obtained by persons of ordinary skill in the art without making creative efforts belong to the protection scope of the present invention.

As shown in FIG. 1 , a current mode sense amplifier provided by an embodiment of the present invention is applied to a memory, and includes: a feedback clamp circuit 100 , an accelerated response circuit 200 and a current comparison amplifier 300 .

The input terminal of the feedback clamping circuit 100 is connected to the floating gate transistor of the storage unit 400, and provides a stable bias voltage for the storage unit 400 to obtain a stable transmission current I _MC flowing through the storage unit 400, and the output terminal transfers the The non-inverting input terminal of the transmission current I _MC input current comparison amplifier 300;

The feedback clamping circuit 100 is a circuit commonly used for fixed voltage, and the present invention will not be described here again. The inverting input terminal of the current comparison amplifier 300 is connected with the reference storage unit 500, and is used to compare the magnitude of the current I _MRC obtained from the reference storage unit 500 and the current I _MC obtained from the feedback clamp circuit 100, and through the output terminal Output the comparison result.

Wherein, the current flowing from the feedback clamp circuit 100 into the current comparison amplifier 300 is denoted as I _MC , and the current flowing into the current comparison amplifier 300 from the reference storage unit 500 is denoted as I _MRC . When I _MC is greater than I _MRC , the current comparison amplifier 300 senses the current difference, and its output is judged as logic '1', and starts to charge the parasitic capacitor. When I _MC is smaller than I _MRC , the current comparison amplifier 300 senses the current difference, and its output is judged as logic '0', and the parasitic capacitance starts to discharge.

The acceleration response circuit 200 is connected to the output terminal of the current comparison amplifier 300 and is used for accelerating the current comparison process of the current comparison amplifier 300 .

When I _MC is greater than I _MRC , the accelerated response circuit 200 charges the parasitic capacitance through the output terminal of the current comparison amplifier 300 , shortening its charging process, which can effectively reduce the current comparison process.

A current-mode sense amplifier provided by an embodiment of the present invention can use a feedback clamp circuit to provide a stable bias voltage for the storage unit to obtain a stable transmission current flowing through the storage unit, and input the current into the current comparison amplifier, to compare with the current obtained from the reference memory cell and output the comparison result. Since the current comparison amplifier of the present invention uses an accelerated response circuit to accelerate the charging speed of the parasitic capacitance at the output end of the current comparison amplifier, the reading speed of data can be effectively improved.

As shown in Figure 2, another current mode sense amplifier provided by the embodiment of the present invention also includes: an output shaping circuit 600, which is used to shape the current difference signal, and the input terminal of the output shaping circuit 600 is connected to the current comparison amplifier The output ends of 300 are connected to each other, and the output end of output shaping circuit 600 is used to output the shaped current difference signal.

Those skilled in the art can understand that the output shaping circuit 600 can perform waveform shaping on the output signal so that its level value can better meet the standard digital logic values of '0' and '1'. Wherein, the output shaping circuit 600 may be composed of two inverters connected in series to perform analog-to-digital conversion and increase driving capability respectively.

As shown in FIG. 3 , in another current mode sense amplifier provided by an embodiment of the present invention, the feedback clamping circuit 100 includes: a first inverter I1, a second NMOS transistor NM2 and a first NMOS transistor NM1, the first inverter The input end of the phaser I1 is connected to the source of the second NMOS transistor NM2, the output end of the first inverter I1 is connected to the gate of the second NMOS transistor NM2, and the drain of the second NMOS transistor NM2 is a feedback clamp The output end of the circuit 100, the source of the second NMOS transistor NM2 is the input end of the feedback clamping circuit 100, and is connected to the drain of the MOS transistor MC in the storage unit, and the drain of the first NMOS transistor NM1 is connected to the power supply VDD , the gate of the first NMOS transistor NM1 inputs a precharge signal SA_PC to control the drain of the floating gate transistor of the storage unit to quickly charge to the clamping potential, the source of the first NMOS transistor NM1 and the source of the second NMOS transistor NM2 connected.

The current comparator amplifier 300 includes:

The first PMOS transistor PM1, the second PMOS transistor PM2, the third NMOS transistor NM3 and the eighth NMOS transistor NM8.

The drain of the first PMOS transistor PM1 is the non-inverting input terminal of the current comparison amplifier, the source is connected to the power supply, and the gate is connected to its own drain; the gate of the second PMOS transistor PM2 is connected to the The gates of the first PMOS transistor PM1 are connected together, the source is connected to the power supply, and the drain is connected to the drain of the third NMOS transistor NM3; the first PMOS transistor PM1 and the second PMOS transistor PM2 constitute The current mirror circuit mirrors the current signal obtained by the drain of the first PMOS transistor PM1 to the drain of the second PMOS transistor PM2.

The drain of the eighth NMOS transistor NM8 is the inverting input terminal of the current comparison amplifier, which is connected to the reference storage unit to obtain the current flowing out of the reference storage unit, the source of the eighth NMOS transistor NM8 is grounded, and the gate The gate of the third NMOS transistor NM3 is connected to the gate of the eighth NMOS transistor NM8 to form a current mirror circuit, which is used to connect the drain of the eighth NMOS transistor NM8 The obtained current is mirrored to the drain of the third NMOS transistor NM3, the source of the third NMOS transistor NM3 is grounded, the drain is connected to the drain of the second PMOS transistor PM2, and the connection point is a common point A , for comparing the drain current of the second PMOS transistor PM2 with the drain current of the third NMOS transistor NM3 at the common point A, and output the comparison result through the common point A.

There is an equivalent parasitic capacitance C _p between the common point A and the ground, which is used for charging and discharging following the comparison result. When the drain current of the second PMOS transistor PM2 is greater than that of the third NMOS transistor NM3 When the drain current is low, the parasitic capacitor is charged, and when the drain current of the second PMOS transistor PM2 is smaller than the drain current of the third NMOS transistor NM3, the parasitic capacitor is discharged.

Those skilled in the art can understand that the equivalent parasitic capacitance C _p is virtually connected between the common point A and the ground in practical applications.

The current comparison amplifier 300 obtains the current I _MC of the memory cell MC and the current I _MRC of the reference memory cell by sampling the non-inverting terminal and the inverting terminal respectively, and serves as two input signals of the current comparison amplifier 300 . Through the current mirror effect of the first PMOS transistor PM1 and the second PMOS transistor PM2, the third NMOS transistor NM3 and the eighth NMOS transistor NM8, the second NMOS transistor PM2 and the third NMOS transistor NM3 perform the comparison of _IMC and _IMRC , The comparison result is converted into a voltage signal at the common point A. When I _MC >I _MRC , according to the principle of current balance, the current comparison amplifier 300 charges the parasitic capacitor Cp, and the second PMOS transistor PM2 finally enters the linear region, and its drain-source voltage is very small at this time, that is, the voltage at point A is realized to be close to The high potential of VDD, that is, output logic "1". When I _MC < I _MRC , according to the principle of current balance, the current comparison amplifier 300 discharges the parasitic capacitance Cp, and the third NMOS transistor NM3 finally enters the linear region. At this time, its drain-source voltage is very small, that is, the voltage at point A becomes close to The low potential of 0, that is, output logic "0".

The output shaping circuit 600 includes: a second inverter I2 and a third inverter I3, the input end of the second inverter I2 is the input end of the output shaping circuit 600, and the output end of the second inverter I2 is connected to the third inverter I2. The input terminals of the inverter I3 are connected together, and the output terminal of the third inverter I3 is the output terminal of the output shaping circuit 600 .

The accelerated response circuit 200 includes:

The third PMOS transistor PM3, the fourth PMOS transistor PM4, the fourth NMOS transistor NM4, the fifth NMOS transistor NM5, the sixth NMOS transistor NM6, the seventh NMOS transistor NM7 and the fourth inverter I4.

The drain of the third PMOS transistor PM3 is connected to the common point A, the source is connected to the power supply, the gate is connected to the drain of the fourth PMOS transistor PM4, and the connection point is the common point B.

The gate of the fourth PMOS transistor PM4 is connected to the drain of the second PMOS transistor PM2, and the source is connected to a power supply.

The drain of the seventh NMOS transistor NM7 is connected to the drain of the third PMOS transistor PM3, the source is grounded, and the gate is connected to the input terminal of the fourth inverter I4.

The output end of the fourth inverter I4 is connected to the gate of the sixth NMOS transistor NM6.

The drain of the sixth NMOS transistor NM6 is connected to a current source I5, and the source is connected to the gate of the fifth NMOS transistor NM5 and the drain of the fifth NOMS transistor NM5.

The gate of the fifth NMOS transistor NM5 is also connected to the gate of the fourth NMOS transistor NM4, and the source of the fifth NOMS transistor NM5 is grounded.

The source of the fourth NMOS transistor NM4 is grounded, and the drain is connected to the gate of the third PMOS transistor PM3.

Wherein, the gate of the seventh NMOS transistor NM7 and the input terminal of the fourth inverter I4 input a control signal SA_PC, and SA_PC controls whether the acceleration response circuit 200 works or not.

It is easy to understand that before reading and determining data, it is necessary to precharge the bit line of the memory cell 400 so that the voltage of the bit line reaches a predetermined clamping voltage. During the precharging period, the first NMOS transistor NM1 precharges the output terminal of the feedback clamp circuit 100 so that the voltage at the terminal quickly reaches a predetermined clamping voltage. After the pre-charging is finished, it enters the phase of reading and judging data, that is, the non-pre-charging period.

During the precharging period of the current comparison amplifier 300 , SA_PC is at a high level, and the sixth NMOS transistor NM6 is turned off through the fourth inverter I4 , blocking the current I _PULL of the current source I5 , and the acceleration response circuit 200 is in an inactive state. At the same time, the seventh NMOS transistor NM7 is turned on, and the potential of the common point A is returned to zero, so the fourth PMOS transistor PM4 is turned on, and the current flowing through the source of the fourth PMOS transistor PM4 is I _PM4 , so that the potential of point B is placed at High level, and finally the output signal SA_OUT of the current comparison amplifier 300 is always low level.

In the non-precharge phase, SA_PC is at low level, the current I _PULL generated by the current source I5 passes through the sixth NMOS transistor NM6 and the fifth NMOS transistor NM5 to ground, and the fourth NMOS transistor NM4 mirrors the current flowing through the fifth NMOS transistor NM5 , the accelerated response circuit 200 is in an effective working state.

Considering the dynamic process, after the pre-charge phase is over, the current comparison amplifier 300 enters the data reading and determination phase. If the read memory cell MC stores logic data “0”, then I _MC < I _MRC , and according to the working principle of the current comparator amplifier 300 , the output of point A should be kept at a low level. Since there is no logic state transition between the potentials at point A before and after the comparison, there is no signal transition establishment process, and no acceleration intervention is required.

If the read memory cell MC stores logic data “1”, then I _MC >I _MRC , and according to the working principle of the current comparator amplifier 300 , the output of point A should be at a high level. Therefore, during the comparison process, the parasitic capacitor Cp is charged, the potential of point A increases gradually, the gate-source voltage of the fourth PMOS transistor PM4 decreases gradually, and the potential of the common point B decreases gradually. When the potential of point B is lower than a threshold voltage of VDD, the third PMOS transistor PM3 starts to conduct, and the parasitic capacitor Cp is auxiliary charged with the current I _PM3 , which speeds up the charging process of the parasitic capacitor Cp, so that point A can be reached faster. The inversion level of the inverter I2 completes the judgment and outputs.

A current-mode sense amplifier provided by an embodiment of the present invention can use a feedback clamp circuit to provide a stable bias voltage for the storage unit to obtain a stable transmission current flowing through the storage unit, and input the current into the current comparison amplifier, to compare with the current obtained from the reference memory cell and output the comparison result. Since the current comparison amplifier of the present invention uses an accelerated response circuit to accelerate the charging speed of the parasitic capacitance at the output end of the current comparison amplifier, the reading speed of data can be effectively improved.

It should be noted that in this article, relational terms such as first and second are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply that there is a relationship between these entities or operations. There is no such actual relationship or order between them.

The above description is only the specific implementation of the present application. It should be pointed out that for those of ordinary skill in the art, without departing from the principle of the present application, some improvements and modifications can also be made. It should be regarded as the protection scope of this application.

Claims (6)

1. an ATD-assisted current sense amplifier, be applied to storer, it is characterized in that, comprising: feedback-clamp circuit, electric current comparison amplifier and booster response circuit,

The input end of described feedback-clamp circuit is connected with the storage unit floating-gate pipe, stablize bias voltage to obtain the stable transmission current of this storage unit of flowing through for storage unit provides, and by output terminal, described transmission current is inputted to the in-phase input end of described electric current comparison amplifier;

The inverting input of described electric current comparison amplifier is connected with reference memory unit, for the size of the electric current relatively obtained from described reference memory unit and the electric current obtained from described feedback-clamp circuit, and exports comparative result by output terminal;

Described booster response circuit is connected with the output terminal of electric current comparison amplifier, for accelerating current ratio than the charging rate of amplifier out stray capacitance, accelerates the electric current comparison procedure of electric current comparison amplifier.

2. ATD-assisted current sense amplifier according to claim 1, it is characterized in that, also comprise: the output Shaping circuit, for the difference between current signal is carried out to shaping, the input end of described output Shaping circuit is connected with the output terminal of described electric current comparison amplifier, and the output terminal of described output Shaping circuit is for the difference between current signal after output Shaping.

3. ATD-assisted current sense amplifier according to claim 1 and 2, is characterized in that, described feedback-clamp circuit comprises: the first phase inverter, the 2nd NMOS pipe and NMOS pipe,

The input end of described the first phase inverter is connected with the source electrode of described the 2nd NMOS pipe, and output terminal is connected with the grid of described the 2nd NMOS pipe; The output terminal that the drain electrode of described the 2nd NMOS pipe is described feedback-clamp circuit, the input end that source electrode is described feedback-clamp circuit and being connected with the drain electrode of described storage unit floating-gate pipe; The drain electrode of a described NMOS pipe is connected with power supply, and grid is inputted a precharging signal, with the drain electrode of controlling described storage unit floating-gate pipe, quickly charges to the clamper current potential, and source electrode is connected with the source electrode of described the 2nd NMOS pipe.

4. ATD-assisted current sense amplifier according to claim 1 and 2, is characterized in that, described electric current comparison amplifier comprises:

The one PMOS pipe, the 2nd PMOS pipe, the 3rd NMOS pipe and the 8th NMOS pipe,

The in-phase input end that the drain electrode of a described PMOS pipe is described electric current comparison amplifier, source electrode is connected with power supply, and grid drains and is connected with self; The grid of the grid of described the 2nd PMOS pipe and a described PMOS pipe links together, and source electrode is connected with power supply, and drain electrode is connected with the drain electrode of the 3rd NMOS pipe; A described PMOS pipe and described the 2nd PMOS pipe form current mirror circuit, and the current signal that a described PMOS pipe drain electrode is obtained is mirrored to the drain electrode of described the 2nd PMOS pipe;

The inverting input that the drain electrode of described the 8th NMOS pipe is described electric current comparison amplifier, be connected with reference memory unit, obtains the electric current flowed out in reference memory unit, the source ground of described the 8th NMOS pipe, and grid is connected with the drain electrode of self; The grid of described the 3rd NMOS pipe is connected with the grid of described the 8th NMOS pipe, form current mirror circuit, the drain electrode of for the current mirror that described the 8th NMOS pipe drain electrode is obtained, arriving described the 3rd NMOS pipe, the source ground of described the 3rd NMOS pipe, drain electrode is connected with the drain electrode of described the 2nd PMOS pipe, tie point is common point A, for the drain current at more described the 2nd PMOS pipe in common point A place and the drain current of described the 3rd NMOS pipe, and by common point A output comparative result;

There is an equivalent stray capacitance between described common point A and ground, for following described comparative result, discharged and recharged, when the drain current of described the 2nd PMOS pipe is greater than the drain current of described the 3rd NMOS pipe, described stray capacitance is charged, when the drain current of described the 2nd PMOS pipe is less than the drain current of described the 3rd NMOS pipe, described stray capacitance is discharged.

5. ATD-assisted current sense amplifier according to claim 4, is characterized in that, described booster response circuit comprises: the 3rd PMOS pipe, the 4th PMOS pipe, the 4th NMOS pipe, the 5th NMOS pipe, the 6th NMOS pipe, the 7th NMOS pipe and the 4th phase inverter,

The drain electrode of described the 3rd PMOS pipe is connected with described common point A, and source electrode is connected with described power supply, and grid is connected with the drain electrode of the 4th PMOS pipe;

The grid of described the 4th PMOS pipe is connected with the drain electrode of described the 2nd PMOS pipe, and source electrode is connected with power supply;

The drain electrode of described the 7th NMOS pipe is connected with the drain electrode of described the 3rd PMOS pipe, source ground, and grid is connected with the input end of described the 4th phase inverter;

The output terminal of described the 4th phase inverter is connected with the grid of described the 6th NMOS pipe;

The drain electrode of described the 6th NMOS pipe is connected with a current source, and source electrode is connected with the grid of described the 5th NMOS pipe and the drain electrode of described the 5th NMOS pipe;

The grid of described the 5th NMOS pipe also is connected with the grid of described the 4th NMOS pipe, the source ground of described the 5th NOMS pipe, and described the 5th NMOS pipe forms current mirror circuit with described the 4th NMOS pipe;

The source ground of described the 4th NMOS pipe, drain electrode is connected with the grid of described the 3rd PMOS pipe.

6. ATD-assisted current sense amplifier according to claim 2, is characterized in that, described output Shaping circuit comprises: the second phase inverter and the 3rd phase inverter,

The input end that the input end of described the second phase inverter is described output Shaping circuit, the output terminal of described the second phase inverter is connected with the input end of described the 3rd phase inverter, the output terminal that the output terminal of described the 3rd phase inverter is described output Shaping circuit.

Images