CN102426845A - Current-mode sense amplifier - Google Patents
Current-mode sense amplifier Download PDFInfo
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- CN102426845A CN102426845A CN2011103913906A CN201110391390A CN102426845A CN 102426845 A CN102426845 A CN 102426845A CN 2011103913906 A CN2011103913906 A CN 2011103913906A CN 201110391390 A CN201110391390 A CN 201110391390A CN 102426845 A CN102426845 A CN 102426845A
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Abstract
The invention discloses a current-mode sense amplifier; a feedback clamp circuit is used to provide a stable bias voltage for a memory cell so as to obtain a stable transport current passing through the memory cell; the current is inputted into a current comparing amplifier, and is compared with a current obtained from a reference memory cell, and the comparison result is outputted. The current comparing amplifier of the invention adopts an accelerating response circuit to accelerate the charging speed of a parasitic capacitance at the output end of the current comparing amplifier, so the data reading speed is effectively improved.
Description
Technical field
The present invention relates to the memory technology field, particularly relate to a kind of current-mode sense amplifier.
Background technology
Sense amplifier is one of read path Key Circuit of storer, and its effect is that storage unit is read and compares with the output of reference memory unit, output judged result (logical zero or logical one).According to principle of work, sense amplifier is divided into two kinds of voltage-mode and current-mode, and their input signal is respectively the voltage and the magnitude of current.
Wherein, Current-mode sense amplifier (AACSA) is the circuit of a kind of low supply voltage, high response speed and low-power consumption; The clock control bit line that it provides through address mapping converter (ATD, Address Transition Detector) carries out dashing in advance and discharge of electric current.Because the current ratio of current-mode sense amplifier is to carry out the current-voltage conversion than process nature, it is proportional that it accomplishes the time that discharges and recharges of comparing required time and comparative degree output node place stray capacitance.In some cases; Because the deviation of technology; Can make that the characteristic of storage unit is influenced; Give the charging and discharging currents of virtual stray capacitance less than normal if transform after the sense amplifier sampling, then need spend long time completion current-voltage transfer process, be unfavorable for reading fast of data for traditional current-mode sense amplifier.
Summary of the invention
For solving the problems of the technologies described above, the embodiment of the invention provides a kind of current-mode sense amplifier, and to improve the speed that data read, technical scheme is following:
A kind of current-mode sense amplifier is applied to storer, comprising: feedback-clamp circuit, electric current comparison amplifier and booster response circuit,
The input end of said feedback-clamp circuit is connected with the storage unit floating-gate pipe; Stablize the stable transmission current of bias voltage for storage unit provides, and said transmission current is imported the in-phase input end of said electric current comparison amplifier through output terminal with this storage unit that obtains flowing through;
Said current ratio is connected with reference memory unit than amplifier's inverting input, the size of electric current that is used for relatively obtaining from said reference memory unit and the electric current that obtains from said feedback-clamp circuit, and through output terminal output comparative result;
Said booster response circuit is connected with the output terminal of electric current comparison amplifier, is used to quicken the electric current comparison procedure of electric current comparison amplifier.
Preferably; This current-mode sense amplifier also comprises: the output Shaping circuit; Be used for said difference between current signal is carried out shaping; The input end of said output Shaping circuit is connected with the output terminal of said electric current comparison amplifier, and the output terminal of said output Shaping circuit is used for the difference between current signal behind the output Shaping.
Preferably, said feedback-clamp circuit comprises: first phase inverter, the 2nd NMOS pipe and NMOS pipe,
The input end of said first phase inverter is connected with the source electrode of said the 2nd NMOS pipe, and output terminal is connected with the grid of said the 2nd NMOS pipe; The drain electrode of said the 2nd NMOS pipe is the output terminal of said feedback-clamp circuit, and source electrode is the input end of said feedback-clamp circuit and is connected with the drain electrode of said storage unit floating-gate pipe; The drain electrode of said NMOS pipe is connected with the energy supply power supply, and grid is imported a precharging signal, quickly charges to the clamper current potential with the drain electrode of controlling said storage unit floating-gate pipe, and source electrode is connected with the source electrode of said the 2nd NMOS pipe.
Preferably, said electric current comparison amplifier comprises:
The one PMOS pipe, the 2nd PMOS pipe, the 3rd NMOS pipe and the 8th NMOS pipe,
The drain electrode of said PMOS pipe is the in-phase input end of said electric current comparison amplifier, and source electrode is connected with power supply, and grid drains with self and is connected; The grid of the grid of said the 2nd PMOS pipe and said PMOS pipe links together, and source electrode is connected with power supply, and drain electrode is connected with the drain electrode of the 3rd NMOS pipe; A said PMOS manages and said the 2nd PMOS pipe constitutes current mirror circuit, and the current signal that the drain electrode of said PMOS pipe is obtained is mirrored to the drain electrode that said the 2nd PMOS manages;
The drain electrode of said the 8th NMOS pipe be said current ratio than amplifier's inverting input, be connected with reference memory unit, obtain the electric current that flows out in the reference memory unit, the source ground of said the 8th NMOS pipe, grid is connected with the drain electrode of self; The grid of said the 3rd NMOS pipe is connected with the grid of said the 8th NMOS pipe; Constitute current mirror circuit, be used for said the 8th NMOS is managed the drain electrode of the current mirror of drain electrode acquisition to said the 3rd NMOS pipe, the source ground that said the 3rd NMOS manages; Drain electrode is connected with the drain electrode of said the 2nd PMOS pipe; Tie point is common point A, is used for the drain current of more said the 2nd PMOS pipe at common point A place and the drain current of said the 3rd NMOS pipe, and through common point A output comparative result;
There is an equivalent stray capacitance between said common point A and the ground; Being used to follow said comparative result discharges and recharges; When the drain current of said the 2nd PMOS pipe during greater than the drain current of said the 3rd NMOS pipe; Said stray capacitance is charged, and when the drain current of said the 2nd PMOS pipe during less than the drain current of said the 3rd NMOS pipe, said stray capacitance is discharged.
Preferably, said booster response circuit comprises: the 3rd PMOS pipe, the 4th PMOS pipe, the 4th NMOS pipe, the 5th NMOS pipe, the 6th NMOS pipe, the 7th NMOS pipe and the 4th phase inverter,
The drain electrode of said the 3rd PMOS pipe is connected with said common point A, and source electrode is connected with said energy supply power supply, and grid is connected with the drain electrode of the 4th PMOS pipe;
The grid of said the 4th PMOS pipe is connected with the drain electrode of said the 2nd PMOS pipe, and source electrode is connected with power supply;
The drain electrode of said the 7th NMOS pipe is connected with the drain electrode of said the 3rd PMOS pipe, source ground, and grid is connected with the input end of said the 4th phase inverter;
The output terminal of said the 4th phase inverter is connected with the grid of said the 6th NMOS pipe;
The drain electrode of said the 6th NMOS pipe is connected with a current source, and source electrode is connected with the grid of said the 5th NMOS pipe and the drain electrode of said the 5th NOMS pipe;
The grid of said the 5th NMOS pipe also is connected with the grid of said the 4th NMOS pipe, the source ground of said the 5th NOMS pipe, and said the 5th NMOS pipe constitutes current mirror circuit with said the 4th NMOS pipe;
The source ground of said the 4th NMOS pipe, drain electrode is connected with the grid of said the 3rd PMOS pipe.
Preferably, said output Shaping circuit comprises: second phase inverter and the 3rd phase inverter,
The input end of said second phase inverter is the input end of said output Shaping circuit, and the output terminal of said second phase inverter is connected with the input end of said the 3rd phase inverter, and the output terminal of said the 3rd phase inverter is the output terminal of said output Shaping circuit.
The technical scheme that the embodiment of the invention provided; Can use feedback-clamp circuit to provide and stablize the stable transmission current of bias voltage with this storage unit that obtains flowing through as storage unit; And with said electric current input current comparison amplifier, to compare and to export comparative result with the electric current that obtains from reference memory unit.Because electric current comparison amplifier of the present invention has used the booster response circuit to accelerate the charging rate of current ratio than the amplifier out stray capacitance, and then has accelerated the electric current comparison procedure, therefore can effectively improve the reading speed of data.
Description of drawings
In order to be illustrated more clearly in the embodiment of the invention or technical scheme of the prior art; To do simple the introduction to the accompanying drawing of required use in embodiment or the description of the Prior Art below; Obviously, the accompanying drawing in describing below only is some embodiments of the present invention, for those of ordinary skills; Under the prerequisite of not paying creative work property, can also obtain other accompanying drawing according to these accompanying drawings.
The circuit diagram of a kind of current-mode sense amplifier that Fig. 1 provides for the embodiment of the invention;
The circuit diagram of the another kind of current-mode sense amplifier that Fig. 2 provides for the embodiment of the invention;
The circuit diagram of the another kind of current-mode sense amplifier that Fig. 3 provides for the embodiment of the invention.
Embodiment
To combine the accompanying drawing in the embodiment of the invention below, the technical scheme in the embodiment of the invention is carried out clear, intactly description, obviously, described embodiment only is the present invention's part embodiment, rather than whole embodiment.Based on the embodiment among the present invention, those of ordinary skills are not making the every other embodiment that is obtained under the creative work prerequisite, all belong to the scope of the present invention's protection.
A kind of current-mode sense amplifier as shown in Figure 1, that the embodiment of the invention provides is applied to storer, comprising: feedback-clamp circuit 100, booster response circuit 200 and electric current comparison amplifier 300,
The input end of feedback-clamp circuit 100 is connected with storage unit 400 floating-gate pipes, stablizes the stable transmission current I of bias voltage with this storage unit 400 that obtains flowing through for storage unit 400 provides
MC, and pass through output terminal with said transmission current I
MCThe in-phase input end of input current comparison amplifier 300;
Feedback-clamp circuit 100 is a kind of circuit that are usually used in fixed voltage, and the present invention no longer describes at this.The inverting input of electric current comparison amplifier 300 is connected with reference memory unit 500, is used for the electric current I that relatively obtains from reference memory unit 500
MRCWith the electric current I that from feedback-clamp circuit 100, obtains
MCSize, and through output terminal output comparative result.
Wherein, will be designated as I from the electric current of feedback-clamp circuit 100 inflow current comparison amplifiers 300
MC, be designated as I from the electric current of reference memory unit 500 inflow current comparison amplifiers 300
MRCWork as I
MCGreater than I
MRCThe time, electric current comparison amplifier 300 perceives difference between current, and its output is judged to be logic ' 1 ', begins stray capacitance is charged.Work as I
MCLess than I
MRCThe time, electric current comparison amplifier 300 perceives difference between current, and its output is judged to be logic ' 0 ', and stray capacitance begins to discharge.
Said booster response circuit 200 is connected with the output terminal of electric current comparison amplifier 300, is used to quicken the electric current comparison procedure of electric current comparison amplifier 300.
Work as I
MCGreater than I
MRCThe time, booster response circuit 200 is that stray capacitance is charged through electric current comparison amplifier 300 output terminals, shortens its charging process, can effectively reduce the electric current comparison procedure.
A kind of current-mode sense amplifier that the embodiment of the invention provides; Can use feedback-clamp circuit to provide and stablize the stable transmission current of bias voltage with this storage unit that obtains flowing through as storage unit; And with said electric current input current comparison amplifier, to compare and to export comparative result with the electric current that obtains from reference memory unit.Because electric current comparison amplifier of the present invention has used the booster response circuit to accelerate the charging rate of current ratio than the amplifier out stray capacitance, therefore can effectively improve the reading speed of data.
As shown in Figure 2; The another kind of current-mode sense amplifier that the embodiment of the invention provides; Also comprise: output Shaping circuit 600; Be used for said difference between current signal is carried out shaping, the input end of output Shaping circuit 600 is connected with the output terminal of electric current comparison amplifier 300, and the output terminal of output Shaping circuit 600 is used for the difference between current signal behind the output Shaping.
It will be appreciated by persons skilled in the art that output Shaping circuit 600 can carry out the waveform arrangement to the signal of being exported, and makes its level value more satisfy standard digital logic ' 0 ', ' 1 ' value.Wherein, output Shaping circuit 600 can be made up of two phase inverters that are cascaded, and carries out analog to digital conversion and the processing that increases driving force respectively.
As shown in Figure 3, in the another kind of current-mode sense amplifier that the embodiment of the invention provides,
Feedback-clamp circuit 100 comprises: the first phase inverter I1, the 2nd NMOS pipe NM2 and NMOS pipe NM1; The input end of the first phase inverter I1 is connected with the source electrode of the 2nd NMOS pipe NM2; The output terminal of the first phase inverter I1 is connected with the grid of the 2nd NMOS pipe NM2; The drain electrode of the 2nd NMOS pipe NM2 is the output terminal of feedback-clamp circuit 100, and the source electrode of the 2nd NMOS pipe NM2 is the input end of feedback-clamp circuit 100, is connected with the drain electrode of metal-oxide-semiconductor MC in the storage unit; The drain electrode of the one NMOS pipe NM1 is connected with energy supply power vd D; The grid of the one NMOS pipe NM1 is imported a precharging signal SA_PC, quickly charges to the clamper current potential with the drain electrode of control store unit floating-gate pipe, and the source electrode of NMOS pipe NM1 is connected with the source electrode that the 2nd NMOS manages NM2.
Electric current comparison amplifier 300 comprises:
The one PMOS pipe PM1, the 2nd PMOS pipe PM2, the 3rd NMOS pipe NM3 and the 8th NMOS pipe NM8,
The drain electrode of said PMOS pipe PM1 is the in-phase input end of said electric current comparison amplifier, and source electrode is connected with power supply, and grid drains with self and is connected; The grid of the grid of said the 2nd PMOS pipe PM2 and said PMOS pipe PM1 links together, and source electrode is connected with power supply, and drain electrode is connected with the drain electrode of the 3rd NMOS pipe NM3; A said PMOS manages PM1 and said the 2nd PMOS pipe PM2 constitutes current mirror circuit, and the current signal that said PMOS pipe PM1 drain electrode is obtained is mirrored to the drain electrode that said the 2nd PMOS manages PM2;
The drain electrode of said the 8th NMOS pipe NM8 be said current ratio than amplifier's inverting input, be connected with reference memory unit, obtain the electric current that flows out in the reference memory unit, the source ground of said the 8th NMOS pipe NM8, grid is connected with the drain electrode of self; The grid of said the 3rd NMOS pipe NM3 is connected with the grid of said the 8th NMOS pipe NM8; Constitute current mirror circuit; Be used for the current mirror that said the 8th NMOS pipe NM8 drain electrode obtains is managed to said the 3rd NMOS the drain electrode of NM3; The source ground of said the 3rd NMOS pipe NM3, drain electrode is connected with the drain electrode of said the 2nd PMOS pipe PM2, and tie point is common point A; Be used for the drain current of more said the 2nd PMOS pipe PM2 at common point A place and the drain current of said the 3rd NMOS pipe NM3, and through common point A output comparative result;
There is an equivalent stray capacitance C between said common point A and the ground
pBeing used to follow said comparative result discharges and recharges; When the drain current of said the 2nd PMOS pipe PM2 is managed the drain current of NM3 greater than said the 3rd NMOS; Said stray capacitance is charged, and when the drain current of said the 2nd PMOS pipe PM2 was managed the drain current of NM3 less than said the 3rd NMOS, said stray capacitance was discharged.
It will be appreciated by persons skilled in the art that the stray capacitance C of equivalence
pIn practical application, be virtual being connected between said common point A and the ground.
Electric current comparison amplifier 300 is obtained the electric current I of storage unit MC respectively through in-phase end and end of oppisite phase sampling
MCElectric current I with reference memory unit
MRC, and as two input signals of electric current comparison amplifier 300.Through the current mirror action of PMOS pipe PM1 and the 2nd PMOS pipe PM2, the 3rd NMOS pipe NM3 and the 8th NMOS pipe NM8, the 2nd NMOS pipe PM2 and the 3rd NMOS pipe NM3 carry out I
MCAnd I
MRCComparison, comparative result is converted into voltage signal at common point A.Work as I
MC＞I
MRCThe time, can know according to the current balance type principle, 300 pairs of stray capacitance Cp chargings of electric current comparison amplifier, the 2nd PMOS pipe PM2 finally gets into linear zone, and this moment, its drain-source voltage was very little, and promptly the A point voltage is cashed and is the noble potential near VDD, i.e. output logic " 1 ".Work as I
MC＜I
MRCThe time, can know according to the current balance type principle, 300 pairs of stray capacitance Cp discharges of electric current comparison amplifier, the 3rd NMOS pipe NM3 finally gets into linear zone, and this moment, its drain-source voltage was very little, i.e. and A point voltage realization is the electronegative potential near 0, i.e. output logic " 0 ".
Said the 3rd PMOS pipe PM3, the 4th PMOS pipe PM4, the 4th NMOS pipe NM4, the 5th NMOS pipe NM5, the 6th NMOS pipe NM6, the 7th NMOS pipe NM7 and the 4th phase inverter I4,
The drain electrode of said the 3rd PMOS pipe PM3 is connected with said common point A, and source electrode is connected with said energy supply power supply, and grid is connected with the drain electrode of the 4th PMOS pipe PM4, and tie point is common point B;
The grid of said the 4th PMOS pipe PM4 is connected with the drain electrode of said the 2nd PMOS pipe PM2, and source electrode is connected with power supply;
The drain electrode of said the 7th NMOS pipe NM7 is connected with the drain electrode of said the 3rd PMOS pipe PM3, source ground, and grid is connected with the input end of said the 4th phase inverter I4;
The output terminal of said the 4th phase inverter I4 is connected with the grid of said the 6th NMOS pipe NM6;
The drain electrode of said the 6th NMOS pipe NM6 is connected with a current source I5, and source electrode is connected with the grid of said the 5th NMOS pipe NM5 and the drain electrode of said the 5th NOMS pipe NM5;
The grid of said the 5th NMOS pipe NM5 also is connected with the grid of said the 4th NMOS pipe NM4, the source ground of said the 5th NOMS pipe NM5;
The source ground of said the 4th NMOS pipe NM4, drain electrode is connected with the grid of said the 3rd PMOS pipe PM3.
Wherein, the grid of the 7th NMOS pipe NM7 and the input end of the 4th phase inverter I4 are imported a control signal SA_PC, and whether the work of SA_PC control booster response circuit 200.
Be understood that easily, before data being read and judge, need at first carry out precharge, make bit-line voltage reach predetermined clamp voltage storage unit 400 bit lines.Between precharge phase, NMOS pipe NM1 carries out the preliminary filling processing to the output terminal of feedback-clamp circuit 100, makes this terminal voltage reach predetermined clamp voltage rapidly.After precharge finishes, promptly get into reading and decision stage of data, between just non-precharge phase.
Carry out between precharge phase at electric current comparison amplifier 300, SA_PC is a high level, makes the 6th NMOS pipe NM6 end through the 4th phase inverter I4, the electric current I of blocking-up current source I5
PULL, booster response circuit 200 is in off position.Simultaneously, the current potential of common point A is made zero in the 7th NMOS pipe NM7 conducting, therefore the 4th PMOS pipe PM4 conducting, and the electric current of the source electrode of the 4th PMOS that flows through pipe PM4 is I
PM4, make B point current potential place high level, the output signal SA_OUT perseverance of ultimate current comparison amplifier 300 is a low level.
In the non-preliminary filling stage, SA_PC is a low level, the electric current I that current source I5 produces
PULLTo ground, the 4th NMOS pipe NM4 mirror image flows through the electric current of the 5th NMOS pipe NM5 through the 6th NMOS pipe NM6, the 5th NMOS pipe NM5, and booster response circuit 200 is in effective duty.
Consider dynamic process, after the preliminary filling stage finished, electric current comparison amplifier 300 promptly got into reading of data and decision stage.If what the storage element MC that is read deposited is logical data " 0 ", I is arranged just
MC＜I
MRC, according to the principle of work of electric current comparison amplifier 300, the output of A point should remain low level.Since relatively with relatively after A point current potential do not have the conversion of occurrence logic state, do not exist the transformation of signal to set up process, also just need not quicken intervention.
If what the storage element MC that is read deposited is logical data " 1 ", I is arranged just
MC＞I
MRC, according to the principle of work of electric current comparison amplifier 300, the output of A point should be high level.So, in comparison procedure, stray capacitance Cp being charged, A point current potential rises gradually, and the gate source voltage of the 4th PMOS pipe PM4 reduces gradually, and the current potential of common point B descends gradually.When B point current potential was lower than threshold voltage of VDD, the 3rd PMOS pipe PM3 began conducting, and with electric current I
PM3Stray capacitance Cp is carried out auxiliary charging, accelerated the charging process of stray capacitance Cp, make the A point reach the upset level of phase inverter I2 quickly, accomplish and judge and output.
A kind of current-mode sense amplifier that the embodiment of the invention provides; Can use feedback-clamp circuit to provide and stablize the stable transmission current of bias voltage with this storage unit that obtains flowing through as storage unit; And with said electric current input current comparison amplifier, to compare and to export comparative result with the electric current that obtains from reference memory unit.Because electric current comparison amplifier of the present invention has used the booster response circuit to accelerate the charging rate of current ratio than the amplifier out stray capacitance, therefore can effectively improve the reading speed of data.
Need to prove; In this article; Relational terms such as first and second grades only is used for an entity or operation are made a distinction with another entity or operation, and not necessarily requires or hint relation or the order that has any this reality between these entities or the operation.
The above only is the application's a embodiment; Should be pointed out that for those skilled in the art, under the prerequisite that does not break away from the application's principle; Can also make some improvement and retouching, these improvement and retouching also should be regarded as the application's protection domain.
Claims (6)
1. a current-mode sense amplifier is applied to storer, it is characterized in that, comprising: feedback-clamp circuit, electric current comparison amplifier and booster response circuit,
The input end of said feedback-clamp circuit is connected with the storage unit floating-gate pipe; Stablize the stable transmission current of bias voltage for storage unit provides, and said transmission current is imported the in-phase input end of said electric current comparison amplifier through output terminal with this storage unit that obtains flowing through;
Said current ratio is connected with reference memory unit than amplifier's inverting input, the size of electric current that is used for relatively obtaining from said reference memory unit and the electric current that obtains from said feedback-clamp circuit, and through output terminal output comparative result;
Said booster response circuit is connected with the output terminal of electric current comparison amplifier, is used to quicken the electric current comparison procedure of electric current comparison amplifier.
2. current-mode sense amplifier according to claim 1; It is characterized in that; Also comprise: the output Shaping circuit; Be used for said difference between current signal is carried out shaping, the input end of said output Shaping circuit is connected with the output terminal of said electric current comparison amplifier, and the output terminal of said output Shaping circuit is used for the difference between current signal behind the output Shaping.
3. current-mode sense amplifier according to claim 1 and 2 is characterized in that, said feedback-clamp circuit comprises: first phase inverter, the 2nd NMOS pipe and NMOS pipe,
The input end of said first phase inverter is connected with the source electrode of said the 2nd NMOS pipe, and output terminal is connected with the grid of said the 2nd NMOS pipe; The drain electrode of said the 2nd NMOS pipe is the output terminal of said feedback-clamp circuit, and source electrode is the input end of said feedback-clamp circuit and is connected with the drain electrode of said storage unit floating-gate pipe; The drain electrode of said NMOS pipe is connected with the energy supply power supply, and grid is imported a precharging signal, quickly charges to the clamper current potential with the drain electrode of controlling said storage unit floating-gate pipe, and source electrode is connected with the source electrode of said the 2nd NMOS pipe.
4. current-mode sense amplifier according to claim 1 and 2 is characterized in that, said electric current comparison amplifier comprises:
The one PMOS pipe, the 2nd PMOS pipe, the 3rd NMOS pipe and the 8th NMOS pipe,
The drain electrode of said PMOS pipe is the in-phase input end of said electric current comparison amplifier, and source electrode is connected with power supply, and grid drains with self and is connected; The grid of the grid of said the 2nd PMOS pipe and said PMOS pipe links together, and source electrode is connected with power supply, and drain electrode is connected with the drain electrode of the 3rd NMOS pipe; A said PMOS manages and said the 2nd PMOS pipe constitutes current mirror circuit, and the current signal that the drain electrode of said PMOS pipe is obtained is mirrored to the drain electrode that said the 2nd PMOS manages;
The drain electrode of said the 8th NMOS pipe be said current ratio than amplifier's inverting input, be connected with reference memory unit, obtain the electric current that flows out in the reference memory unit, the source ground of said the 8th NMOS pipe, grid is connected with the drain electrode of self; The grid of said the 3rd NMOS pipe is connected with the grid of said the 8th NMOS pipe; Constitute current mirror circuit, be used for said the 8th NMOS is managed the drain electrode of the current mirror of drain electrode acquisition to said the 3rd NMOS pipe, the source ground that said the 3rd NMOS manages; Drain electrode is connected with the drain electrode of said the 2nd PMOS pipe; Tie point is common point A, is used for the drain current of more said the 2nd PMOS pipe at common point A place and the drain current of said the 3rd NMOS pipe, and through common point A output comparative result;
There is an equivalent stray capacitance between said common point A and the ground; Being used to follow said comparative result discharges and recharges; When the drain current of said the 2nd PMOS pipe during greater than the drain current of said the 3rd NMOS pipe; Said stray capacitance is charged, and when the drain current of said the 2nd PMOS pipe during less than the drain current of said the 3rd NMOS pipe, said stray capacitance is discharged.
5. current sensitive amplifier according to claim 4 is characterized in that, said booster response circuit comprises: the 3rd PMOS pipe, the 4th PMOS pipe, the 4th NMOS pipe, the 5th NMOS pipe, the 6th NMOS pipe, the 7th NMOS pipe and the 4th phase inverter,
The drain electrode of said the 3rd PMOS pipe is connected with said common point A, and source electrode is connected with said energy supply power supply, and grid is connected with the drain electrode of the 4th PMOS pipe;
The grid of said the 4th PMOS pipe is connected with the drain electrode of said the 2nd PMOS pipe, and source electrode is connected with power supply;
The drain electrode of said the 7th NMOS pipe is connected with the drain electrode of said the 3rd PMOS pipe, source ground, and grid is connected with the input end of said the 4th phase inverter;
The output terminal of said the 4th phase inverter is connected with the grid of said the 6th NMOS pipe;
The drain electrode of said the 6th NMOS pipe is connected with a current source, and source electrode is connected with the grid of said the 5th NMOS pipe and the drain electrode of said the 5th NOMS pipe;
The grid of said the 5th NMOS pipe also is connected with the grid of said the 4th NMOS pipe, the source ground of said the 5th NOMS pipe, and said the 5th NMOS pipe constitutes current mirror circuit with said the 4th NMOS pipe;
The source ground of said the 4th NMOS pipe, drain electrode is connected with the grid of said the 3rd PMOS pipe.
6. current sensitive amplifier according to claim 2 is characterized in that, said output Shaping circuit comprises: second phase inverter and the 3rd phase inverter,
The input end of said second phase inverter is the input end of said output Shaping circuit, and the output terminal of said second phase inverter is connected with the input end of said the 3rd phase inverter, and the output terminal of said the 3rd phase inverter is the output terminal of said output Shaping circuit.
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| CN104681053A (en) * | 2013-11-27 | 2015-06-03 | 苏州东微半导体有限公司 | Current mode sense amplifier circuit applied in semi-floating gate memory cell |
| CN105719679A (en) * | 2014-12-01 | 2016-06-29 | 中国科学院微电子研究所 | Sensitive amplifier and signal processing method |
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| CN102081959A (en) * | 2009-11-26 | 2011-06-01 | 中国科学院微电子研究所 | Storage reading circuit and storage |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN104681053A (en) * | 2013-11-27 | 2015-06-03 | 苏州东微半导体有限公司 | Current mode sense amplifier circuit applied in semi-floating gate memory cell |
| CN104681053B (en) * | 2013-11-27 | 2017-09-05 | 苏州东微半导体有限公司 | A kind of Current-type sensitive amplifier circuit for being applied to half floating gate memory cell |
| CN105719679A (en) * | 2014-12-01 | 2016-06-29 | 中国科学院微电子研究所 | Sensitive amplifier and signal processing method |
| CN105719679B (en) * | 2014-12-01 | 2018-02-02 | 中国科学院微电子研究所 | Sense amplifier and a kind of method of signal transacting |
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| CN102426845B (en) | 2013-12-04 |
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