CN109257024A - Sensitive amplifier circuit - Google Patents
Sensitive amplifier circuit Download PDFInfo
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- CN109257024A CN109257024A CN201811144062.4A CN201811144062A CN109257024A CN 109257024 A CN109257024 A CN 109257024A CN 201811144062 A CN201811144062 A CN 201811144062A CN 109257024 A CN109257024 A CN 109257024A
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
- H03F3/04—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements with semiconductor devices only
- H03F3/16—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements with semiconductor devices only with field-effect devices
- H03F3/165—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements with semiconductor devices only with field-effect devices with junction-FET's
Abstract
The invention discloses a kind of sensitive amplifier circuits, comprising: nine PMOS transistors, seven NMOS transistors, two capacitors, two phase inverters, an operational amplifier, a voltage-controlled current source and a storage unit；The compensation electric current of first capacitor and the second the first PMOS transistor of Capacity control and the second PMOS transistor；Memory cell current and the first voltage controlled current ource electric current influence to compensate electric current by first capacitor and the second capacitor, realize that dynamic changes the effect of compensation electric current.The speed for comparing electric current can be substantially turned up in the present invention, realize the sensitive amplifier circuit of high speed.
Description
Technical field
The present invention relates to semiconductor integrated circuit fields, more particularly to a kind of sense amplifier (SA) circuit.
Background technique
Traditional sense amplifier is mainly compared by electric current, and the method that cooperation latch accelerates realizes the effect for improving speed
Fruit.
Fig. 1 is a kind of existing traditional sensitive amplifier circuit, by four PMOS transistor PM0~PM3, six NMOS crystalline substances
Body pipe NM0~NM5, two capacitor C1, C2, two voltage-controlled current sources DY1, DY2, a rest-set flip-flop RS composition.
Electric current lref is to flow out from the drain electrode of PMOS transistor PM1, into the electric current of node VD0；Electric current lcell be from
The drain electrode of PMOS transistor PM2 is flowed out, into the electric current of node VD1.
LATCH is latch cicuit, and reference memory unit CKDY is made of in Fig. 1 capacitor C1 and voltage-controlled current source DY1, ginseng
Storage unit CCDY is examined to be made of capacitor C2 and voltage-controlled current source DY2.
The waveform diagram of circuit shown in Fig. 1, it is shown in Figure 2.
In circuit shown in Fig. 1, the voltage of node VE is VDD-Vt when charging, and VDD is supply voltage, and Vt is PMOS brilliant
The threshold voltage of body pipe PM1, can have an impact to charging rate, in addition, latch cicuit accelerates when Iref and Icell are closer to
Time can be elongated.
Summary of the invention
The technical problem to be solved in the present invention is to provide a kind of sensitive amplifier circuits, can substantially be turned up and compare electric current
Speed realizes the sensitive amplifier circuit of high speed.
In order to solve the above technical problems, sensitive amplifier circuit of the invention, comprising: nine PMOS transistors, seven
NMOS transistor, two capacitors, two phase inverters, an operational amplifier, a voltage-controlled current source and a storage unit；
The source electrode of first PMOS transistor, the drain electrode of the source electrode of the 4th PMOS transistor and third PMOS transistor, second
The drain electrode of PMOS transistor is connected with supply voltage vdd terminal；
The source electrode of third PMOS transistor is connected with the drain electrode of the first PMOS transistor, and the node of connection is denoted as LD,
The source electrode of second PMOS transistor is connected with the drain electrode of the 4th PMOS transistor, and the node of connection is denoted as RD；First capacitor
One end be connected with node LD, the other end is connected with the grid of the second PMOS transistor, connection node be denoted as RG；The
One end of two capacitors is connected with node R D, and the other end is connected with the grid of the first PMOS transistor, the node note of connection
For LG；The grid of third PMOS transistor and the grid of the 4th PMOS transistor input ready signal PRE；
The inverting input terminal of first operational amplifier is connected with node LD, and positive inverting input terminal is connected with node R D
It connects, output end OUT of the output end as circuit；
The drain electrode of first NMOS transistor is connected with node LD, and the input terminal and storage of source electrode and the first phase inverter are single
One end of member is connected, and the node of connection is denoted as A, the other end ground connection of storage unit, the output end of the first phase inverter and the
The grid of one NMOS transistor is connected；
The source electrode of second NMOS transistor is connected with node R D, drain electrode and the input terminal of the second phase inverter and the first pressure
The anode of control current source is connected, and the node of connection is denoted as B, the negative one end ground connection of the first voltage-controlled current source；Second phase inverter
Output end be connected with the grid of the second NMOS transistor；
The drain electrode of 7th PMOS transistor is connected with power voltage terminal VDD, the enabled letter of grid input signal reverse phase
Number SAENB, source electrode are connected with the drain electrode of the source electrode and the 6th PMOS transistor of the 5th PMOS transistor；5th PMOS crystal
The drain electrode of pipe, the grid of the 6th PMOS transistor, the grid of the 4th NMOS transistor and the source electrode and section of third NMOS transistor
Point LD is connected；The source electrode of 6th PMOS transistor, the drain electrode of the 4th NMOS transistor, the grid of the 5th PMOS transistor and
The grid of three NMOS transistor NM3 is connected with node R D；
The drain electrode of third NMOS transistor is connected with the drain electrode of the source electrode and the 5th NMOS transistor of the 4th NMOS transistor
It connects, the 5th NMOS transistor grid inputs enable signal SAEN, source electrode ground connection；
The source electrode of 8th PMOS transistor is connected with the drain electrode of the 6th NMOS transistor and node LG, the 8th PMOS crystal
The drain electrode of pipe is connected with the source electrode of the 6th NMOS transistor, inputs the biasing voltage signal of external offer PMOS transistor
PBIAS；The grid of 8th PMOS transistor inputs ready signal PRE, and the grid of the 6th NMOS transistor inputs precharging signal
PREB；
The source electrode of 9th PMOS transistor is connected with the drain electrode of the 7th NMOS transistor and node R G, the 9th PMOS crystal
The drain electrode of pipe is connected with the source electrode of the 7th NMOS transistor, inputs the biasing voltage signal of external offer PMOS transistor
PBIAS；The grid of 9th PMOS transistor inputs ready signal PRE, and the grid of the 7th NMOS transistor inputs precharging signal
PREB。
The speed for comparing electric current is substantially turned up under the premise of not sacrificing charging rate in the present invention.Realize the mesh of high speed SA
's.
Using circuit of the invention, the first PMOS transistor and the 2nd PMOS are controlled by first capacitor and the second capacitor
The electric current (compensation electric current) of transistor, is no longer the compensation electric current for the fixation for using to be come by external mirror image, or will directly deposit
The method (speed that charging can be greatly reduced in this method) that storage unit electric current and voltage-controlled current source current mirror come out.Storage unit
Electric current and the first voltage controlled current ource electric current influence to compensate electric current by first capacitor and the second capacitor, realize that dynamic changes compensation
The effect of electric current.In this way, the speed for comparing electric current can be improved greatly, cooperation is brilliant by the 5th PMOS transistor and the 6th PMOS
The latch units of the composition of body pipe and third NMOS transistor and the 4th NMOS transistor realize the purpose of high speed SA.
Detailed description of the invention
Present invention will now be described in further detail with reference to the accompanying drawings and specific embodiments:
Fig. 1 is existing sensitive amplifier circuit schematic diagram；
Fig. 2 is sensitive amplifier circuit waveform diagram shown in Fig. 1；
Fig. 3 is improved one embodiment schematic diagram of sensitive amplifier circuit；
Fig. 4 is sensitive amplifier circuit waveform diagram shown in Fig. 3 (one)；
Fig. 5 is sensitive amplifier circuit waveform diagram shown in Fig. 3 (two).
Specific embodiment
As shown in connection with fig. 3, the improved sensitive amplifier circuit of the present invention, in the following embodiments, comprising: nine
PMOS transistor PM1~PM9, seven NMOS transistor NM1~NM7, two capacitor C1, C2, two phase inverter FX1, FX2, one
A operational amplifier YF1, a voltage-controlled current source DY3 and a storage unit.
The source electrode of PMOS transistor PM1, PM4 and the drain electrode of PMOS transistor PM3, PM2 are connected with power voltage terminal VDD
It connects.
The source electrode of PMOS transistor PM3 is connected with the drain electrode of PMOS transistor PM1, and the node of connection is denoted as LD,
The source electrode of PMOS transistor PM2 is connected with the drain electrode of PMOS transistor PM4, and the node of connection is denoted as RD.The one of capacitor C1
End is connected with node LD, and the other end is connected with the grid of PMOS transistor PM2, and the node of connection is denoted as RG；Capacitor C2
One end be connected with node R D, the other end is connected with the grid of PMOS transistor PM1, connection node be denoted as LG.
The grid of PMOS transistor PM3 and the grid of PMOS transistor PM4 input ready signal PRE.Capacitor C1, C2 and PMOS transistor
PM1, PM2 constitute compensation current unit.
The inverting input terminal of the operational amplifier YF1 is connected with node LD, positive inverting input terminal and node R D phase
Connection, output end OUT of the output end as circuit.The operational amplifier YF1 is the output unit of circuit.
The drain electrode of NMOS transistor NM1 is connected with node LD, the input terminal and storage of source electrode and the first phase inverter FX1
One end of unit is connected, and the node of connection is denoted as A, the other end ground connection of storage unit.The output end of first phase inverter FX1
It is connected with the grid of NMOS transistor NM1.Voltage clamping of the first phase inverter FX1 to node A.
The source electrode of NMOS transistor NM2 is connected with node R D, drains and the input terminal of the second phase inverter FX2 and voltage-controlled
The anode of current source DY3 is connected, and the node of connection is denoted as B, the negative one end ground connection of voltage-controlled current source DY3.Second phase inverter
The output end of FX2 is connected with the grid of NMOS transistor NM2.Voltage clamping of the second phase inverter FX2 to node B.
The drain electrode of PMOS transistor PM7 is connected with power voltage terminal VDD, the enable signal of grid input inversion
SAENB (signal that enable signal SAEN is obtained after level-one reverse phase), the source electrode and PMOS of source electrode and PMOS transistor PM5
The drain electrode of transistor PM6 is connected,
The drain electrode of PMOS transistor PM5, the grid of PMOS transistor PM6, NMOS transistor NM4 grid and NMOS crystal
The source electrode of pipe NM3 is connected with node LD.The source electrode of PMOS transistor PM6, the drain electrode of NMOS transistor NM4, PMOS transistor
The grid of PM5 and the grid of NMOS transistor NM3 are connected with node R D.The drain electrode of NMOS transistor NM3 and NMOS transistor
The source electrode of NM4 is connected with the drain electrode of NMOS transistor NM5, and NMOS transistor NM5 grid inputs enable signal SAEN, source electrode
Ground connection.PMOS transistor PM5, PM6 and NMOS transistor NM3, NM4 constitute latch units.
The source electrode of PMOS transistor PM8 is connected with the drain electrode of NMOS transistor NM6 and node LG, PMOS transistor PM8
Drain electrode be connected with the source electrode of NMOS transistor NM6, input and external provide the biasing voltage signal PBIAS of PMOS transistor.
The grid of PMOS transistor PM8 inputs ready signal PRE, and the grid of NMOS transistor NM6 inputs precharging signal PREB (PREB
It is the signal that ready signal PRE is obtained after level-one reverse phase).
The source electrode of PMOS transistor PM9 is connected with the drain electrode of NMOS transistor NM7 and node R G, PMOS transistor PM9
Drain electrode be connected with the source electrode of NMOS transistor NM7, input and external provide the biasing voltage signal PBIAS of PMOS transistor.
The grid of PMOS transistor PM9 inputs ready signal PRE, and the grid of NMOS transistor NM7 inputs precharging signal PREB.
PMOS transistor PM8 and NMOS transistor NM6 and PMOS transistor PM9 and NMOS transistor NM7 opened nodes
LG, RG make voltage be charged to bias voltage PBIAS to the access of biasing voltage signal PBIAS, provide an initial voltage, protect
It demonstrate,proves consistent with PMOS transistor PM2 initial state current in the moment PMOS transistor PM1 for entering second stage.
1. pre-charging stage, PMOS transistor PM3, PM4 opening, node LD, RD are charged to supply voltage VDD；Node R G,
LG point is opened to the access of the external bias voltage PBIAS for providing PMOS transistor, and voltage is charged to bias voltage PBIAS.PMOS
Transistor PM3, PM4 form precharge unit.Label 1 indicates pre-charging stage in label 1 and Fig. 5 in Fig. 4.
2. read phase, when memory cell current (being denoted as Icell) is less than the electric current (being denoted as Iref) of voltage-controlled current source DY3
When, the grid of PMOS transistor PM1, PM2 disconnect and the connection at the end bias voltage PBIAS, and due to capacitor C1, the coupling of C2 is made
With node R G will receive the influence of node LD, and node LG will receive the influence of RD；The voltage decrease speed of node R D is greater than node
LD, therefore the voltage decrease speed of node LG is greater than node R G.The electric current (Ip1) of PMOS transistor PM1 is greater than PMOS transistor
The electric current (Ip2) of PM2.The electric current of node LD is equal to Icell-Ip1；The electric current of node R D node be equal to Iref-Ip2, Icell <
Iref, Ip1>Ip2, so the voltage of Icell-Ip1<<Iref-Ip2, node LD and RD separate speed quickening, the electricity of node R D
Drops speed is greater than node LD.Waveform is specifically shown in label 2 in Fig. 4.
Otherwise similarly.In read phase, when memory cell current is greater than the electric current of voltage-controlled current source DY3, PMOS transistor
The grid of PM1, PM2 disconnect and the connection at the end bias voltage PBIAS, and due to capacitor C1, the coupling of C2, node R G be will receive
The influence of node LD, node LG will receive the influence of RD；The voltage decrease speed of node R D is less than node LD, therefore node LG
Voltage decrease speed is less than node R G；The electric current of PMOS transistor PM1 is less than the electric current of PMOS transistor PM2；The electricity of node LD
Stream is equal to Icell-Ip1；The electric current of node R D node is equal to Iref-Ip2, Icell>Iref, Ip1<Ip2, so Icell-Ip1
The voltage of > > Iref-Ip2, node LD and RD separate speed quickening, and the voltage decrease speed of node R D is less than node LD.Waveform tool
Body is shown in label 2 in Fig. 5.
3. latch stage, when node LD and RD are divided to out 0.1*VDD (difference of 0.1*VDD occurs in the voltage of two nodes),
The latch units of enable signal SAEN control are opened, the overturning of node LD and RD are accelerated, change it quickly for VDD and GND.Lock
Deposit output.Label 3 indicates latch stage in label 3 and Fig. 5 in Fig. 4." * " indicates multiplication sign.
The voltage that the present invention guarantees node LD and RD in pre-charging stage improves precharge speed, read phase passes through in VDD
Capacitor C1, C2, which realizes compensation electric current Ip1, Ip2, to generate dynamic change with the relationship of Icell electric current and Iref electric current, greatly
The time is compared in width acceleration.Finally cooperate latch structure, realizes and put for the sensitive of high speed in NVM (nonvolatile memory)
Big device.
Above by specific embodiment, invention is explained in detail, but these are not constituted to of the invention
Limitation.Without departing from the principles of the present invention, those skilled in the art can also make many modification and improvement, these
It should be regarded as protection scope of the present invention.
Claims (11)
1. a kind of sensitive amplifier circuit characterized by comprising nine PMOS transistors, seven NMOS transistors, two electricity
Hold, two phase inverters, an operational amplifier, a voltage-controlled current source and a storage unit；
The source electrode of first PMOS transistor, the drain electrode of the source electrode of the 4th PMOS transistor and third PMOS transistor, the 2nd PMOS
The drain electrode of transistor is connected with supply voltage vdd terminal；
The source electrode of third PMOS transistor is connected with the drain electrode of the first PMOS transistor, and the node of connection is denoted as LD, and second
The source electrode of PMOS transistor is connected with the drain electrode of the 4th PMOS transistor, and the node of connection is denoted as RD；The one of first capacitor
End is connected with node LD, and the other end is connected with the grid of the second PMOS transistor, and the node of connection is denoted as RG；Second electricity
One end of appearance is connected with node R D, and the other end is connected with the grid of the first PMOS transistor, and the node of connection is denoted as LG；
The grid of third PMOS transistor and the grid of the 4th PMOS transistor input ready signal PRE；
The inverting input terminal of first operational amplifier is connected with node LD, and positive inverting input terminal is connected with node R D,
Output end OUT of the output end as circuit；
The drain electrode of first NMOS transistor is connected with node LD, the input terminal and storage unit of source electrode and the first phase inverter
One end is connected, and the node of connection is denoted as A, the other end ground connection of storage unit, the output end of the first phase inverter and first
The grid of NMOS transistor is connected；
The source electrode of second NMOS transistor is connected with node R D, the input terminal and the first voltage-controlled electricity of drain electrode and the second phase inverter
The anode in stream source is connected, the negative one end ground connection of the first voltage-controlled current source；The output end of second phase inverter and the 2nd NMOS crystal
The grid of pipe is connected；
The drain electrode of 7th PMOS transistor is connected with power voltage terminal VDD, the enable signal of grid input signal reverse phase
SAENB, source electrode are connected with the drain electrode of the source electrode and the 6th PMOS transistor of the 5th PMOS transistor；5th PMOS transistor
Drain electrode, the grid of the 6th PMOS transistor, the grid of the 4th NMOS transistor and the source electrode and node of third NMOS transistor
LD is connected；The drain electrode of the source electrode, the 4th NMOS transistor of 6th PMOS transistor, the 5th PMOS transistor grid and third
The grid of NMOS transistor NM3 is connected with node R D；
The drain electrode of third NMOS transistor is connected with the drain electrode of the source electrode and the 5th NMOS transistor of the 4th NMOS transistor, the
Five NMOS transistor grids input enable signal SAEN, source electrode ground connection；
The source electrode of 8th PMOS transistor is connected with the drain electrode of the 6th NMOS transistor and node LG, the 8th PMOS transistor
Drain electrode is connected with the source electrode of the 6th NMOS transistor, inputs the biasing voltage signal PBIAS of external offer PMOS transistor；The
The grid of eight PMOS transistors inputs ready signal PRE, and the grid of the 6th NMOS transistor inputs precharging signal PREB；
The source electrode of 9th PMOS transistor is connected with the drain electrode of the 7th NMOS transistor and node R G, the 9th PMOS transistor
Drain electrode is connected with the source electrode of the 7th NMOS transistor, inputs the biasing voltage signal PBIAS of external offer PMOS transistor；The
The grid of nine PMOS transistors inputs ready signal PRE, and the grid of the 7th NMOS transistor inputs precharging signal PREB.
2. circuit as described in claim 1, it is characterised in that: first capacitor, the second capacitor, the first PMOS transistor and second
PMOS transistor constitutes compensation current unit, passes through the compensation electric current of first capacitor and second the first PMOS transistor of Capacity control
With the compensation electric current of the second PMOS transistor.
3. circuit as claimed in claim 1 or 2, it is characterised in that: the electric current of the storage unit and the first voltage-controlled current source
Electric current influenced by first capacitor and the second capacitor compensate electric current, realize dynamic change compensation electric current effect.
4. circuit as described in claim 1, it is characterised in that: for first phase inverter to the voltage clamping of node A, second is anti-
Voltage clamping of the phase device to node B.
5. circuit as described in claim 1, it is characterised in that: the 8th PMOS transistor and the 6th NMOS transistor, Yi Ji
Nine PMOS transistors and the 7th NMOS transistor opened nodes LG, RG to the access of biasing voltage signal PBIAS, make node LG,
RG voltage is charged to bias voltage PBIAS, provides an initial voltage, guarantees the first PMOS transistor when entering second stage
It is consistent with the second PMOS transistor initial state current.
6. circuit as described in claim 1, it is characterised in that: third PMOS transistor and the 4th PMOS transistor form preliminary filling
Electric unit, pre-charging stage, third PMOS transistor and the 4th PMOS transistor are opened, and node LD, RD are charged to supply voltage
VDD；Node R G, LG point is opened to the access of the external bias voltage PBIAS for providing PMOS transistor, and node R G, LG voltage fills
To bias voltage PBIAS.
7. circuit as claimed in claim 6, it is characterised in that: guarantee the voltage of node LD and RD in power supply in pre-charging stage
Voltage VDD improves precharge speed.
8. circuit as described in claim 1, it is characterised in that: in read phase, when memory cell current is less than the first voltage-controlled electricity
When the electric current in stream source, the grid of the grid of the first PMOS transistor and the second PMOS transistor disconnects and the end bias voltage PBIAS
Connection, due to the coupling of first capacitor and the second capacitor, node R G will receive the influence of node LD, and node LG will receive
The influence of RD；The voltage decrease speed of node R D is greater than node LD, therefore the voltage decrease speed of node LG is greater than node R G；The
The electric current of one PMOS transistor is greater than the electric current of the second PMOS transistor；The electric current of node LD is equal to Icell-Ip1；Node R D section
The electric current of point is equal to Iref-Ip2, Icell<Iref, Ip1>Ip2, so Icell-Ip1<<Iref-Ip2, node LD's and RD
Voltage separates speed quickening, and the voltage decrease speed of node R D is greater than node LD；Wherein Icell is memory cell current, Iref
For the first voltage controlled current ource electric current, Ip1 is the first PMOS transistor current, and Ip2 is the second PMOS transistor current.
9. circuit as described in claim 1, it is characterised in that: in read phase, when memory cell current is greater than the first voltage-controlled electricity
When the electric current in stream source, the grid of the grid of the first PMOS transistor and the second PMOS transistor disconnects and the end bias voltage PBIAS
Connection, due to the coupling of first capacitor and the second capacitor, node R G will receive the influence of node LD, and node LG will receive
The influence of RD；The voltage decrease speed of node R D is less than node LD, therefore the voltage decrease speed of node LG is less than node R G；The
Electric current of the electric current of one PMOS transistor less than the second PMOS transistor；The electric current of node LD is equal to Icell-Ip1；Node R D section
The electric current of point is equal to Iref-Ip2, Icell>Iref, Ip1<Ip2, so Icell-Ip1>>Iref-Ip2, node LD's and RD
Voltage separates speed quickening, and the voltage decrease speed of node R D is less than node LD；Wherein Icell is memory cell current, Iref
For the first voltage controlled current ource electric current, Ip1 is the first PMOS transistor current, and Ip2 is the second PMOS transistor current.
10. circuit as claimed in claim 8 or 9, it is characterised in that: read phase is realized by first capacitor and the second capacitor and mended
Electric current Ip1 is repaid, Ip2 can generate dynamic change with the relationship of electric current Icell and electric current Iref, improve the speed for comparing electric current.
11. circuit as described in claim 1, it is characterised in that: the 5th PMOS transistor, the 6th PMOS transistor, third
NMOS transistor and the 4th NMOS transistor constitute latch units；In latch stage, when opening 0.1*VDD for node LD and RD points,
That is there is the difference of 0.1*VDD in the voltage of two nodes, opens the latch units of enable signal SAEN control, accelerates node LD and RD
Overturning changes it quickly for VDD and GND, latch output；Wherein " * " indicates multiplication sign.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201811144062.4A CN109257024B (en) | 2018-09-29 | 2018-09-29 | Sensitive amplifier circuit |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201811144062.4A CN109257024B (en) | 2018-09-29 | 2018-09-29 | Sensitive amplifier circuit |
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| CN109257024A true CN109257024A (en) | 2019-01-22 |
| CN109257024B CN109257024B (en) | 2022-06-17 |
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Cited By (1)
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| WO2023134138A1 (en) * | 2022-01-11 | 2023-07-20 | 长鑫存储技术有限公司 | Sensitivity amplifier and driving method therefor, and memory |
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| Publication number | Publication date |
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| CN109257024B (en) | 2022-06-17 |
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