CN115240737A

CN115240737A - High-speed data reading circuit and method for phase change memory

Info

Publication number: CN115240737A
Application number: CN202210822331.8A
Authority: CN
Inventors: 李喜; 陈成; 解晨晨; 徐思秋; 陈后鹏
Original assignee: Shanghai Xinchu Integrated Circuit Co Ltd
Current assignee: Shanghai Xinchu Integrated Circuit Co Ltd
Priority date: 2022-07-13
Filing date: 2022-07-13
Publication date: 2022-10-25

Abstract

The invention relates to the technical field of microelectronics, in particular to a high-speed data reading circuit and a method of a phase change memory, and the high-speed data reading circuit comprises a pre-charging control circuit, a clamping circuit, a parasitic matching array, a pre-charging circuit, a comparison circuit and a reference current generating circuit, wherein the pre-charging circuit comprises a target bit line pre-charging part and a parasitic matching array pre-charging part, and the comparison circuit comprises a reading current conversion part, a reference current conversion part and a comparison part.

Description

High-speed data reading circuit and method for phase change memory

Technical Field

The invention relates to the technical field of microelectronics, in particular to a data reading circuit and a data reading method of a phase change memory.

Background

The phase change memory is a novel nonvolatile memory based on chalcogenide compound materials, and with the continuous advance of process nodes, the phase change memory has an increasingly important position in memory development due to the characteristics of huge micro-scale prospect, high speed, high density, low power consumption, compatibility with a CMOS (complementary metal oxide semiconductor) process and the like, and is considered to be one of novel memories with the most development potential in the industry.

The phase change memory is based on an ovonic electronic effect memory proposed by Ovshinsky in the end of the 20 th 60 th century, generally refers to a chalcogenide random access memory, also called an ovonic electronic effect unified memory, and is used as a new generation of high-speed low-power-consumption memory.

In the conventional technical scheme, the reference current is a constant current provided by a Low Dropout Regulator (LDO), and by comparing a read current generated by an external clamp voltage, the core comparison module compares the read current with the reference current and inputs the comparison result to the SR latch, and outputs a high level and a Low level. When the selected phase change memory cell is a crystalline state memory cell, the reading current is larger than the reference current, and a high level is output; when the selected phase change memory cell is an amorphous memory cell, the read current is less than the reference current, and a low level is output.

Along with the increase of the capacity of a phase change memory chip, when the size of a phase change memory array is too large, the parasitic effect can cause the overlong charging time of a bit line so as to influence the reading speed of the chip, and meanwhile, due to the influence of the manufacturing process and the relative position of the array, the resistance value of a phase change memory unit is in normal distribution, and the resistance distribution also has great influence on the speed of reading operation.

Disclosure of Invention

The invention aims to provide a high-speed data reading circuit of a phase change memory, which solves the technical problems;

the present invention also aims to provide a phase change memory high-speed data reading method, which solves the above technical problems;

the technical problem solved by the invention can be realized by adopting the following technical scheme:

a phase change memory high speed data sensing circuit includes,

the precharge control circuit is used for receiving a first read enable signal and generating a second read enable signal and a first precharge signal based on the first read enable signal;

the clamping circuit is connected with the pre-charging control circuit, the clamping circuit is also connected with a phase-change storage array and a parasitic matching array, the clamping circuit clamps the bit line voltages of the phase-change storage array and the parasitic matching array respectively, and the clamping circuit reads and mirrors the reading current and the reference current under the action of the second reading enabling signal;

the pre-charging circuit is connected with the pre-charging control circuit, the clamping circuit and the phase change storage array and the parasitic matching array and is used for generating pre-charging current to carry out pre-charging operation on the phase change storage array and the parasitic matching array simultaneously;

the comparison circuit is connected with the clamping circuit and is used for comparing the reading current with the reference current;

and the reference current generating circuit is connected with the clamping circuit, the pre-charging circuit and the parasitic matching array, and generates the reference current based on a reference voltage.

Preferably, the precharge control circuit includes,

the input end of the phase inverter is connected with the external read enable signal output end;

the source electrode of the first PMOS tube is connected with the power supply voltage input end, and the grid electrode of the first PMOS tube is connected with the output end of the phase inverter;

the grid electrode of the first NMOS tube is connected with the output end of the phase inverter, and the source electrode of the first NMOS tube is grounded;

a source electrode of the second PMOS tube is connected with a drain electrode of the first PMOS tube;

the drain electrode of the second NMOS tube is connected with the drain electrode of the first NMOS tube, the grid electrode of the second NMOS tube is connected with the grid electrode of the second PMOS tube, and the source electrode of the second NMOS tube is grounded;

a source electrode of the third PMOS tube is connected with a drain electrode of the second PMOS tube, and a drain electrode of the third PMOS tube is connected with drain electrodes of the first NMOS tube, the second NMOS tube and the third NMOS tube;

and the drain electrode of the third NMOS tube is connected with the drain electrodes of the first NMOS tube and the second NMOS tube, the grid electrode of the third NMOS tube is connected with the grid electrode of the third PMOS tube, and the source electrode of the second NMOS tube is grounded.

Preferably, the clamp circuit includes a sense bit line clamp and a parasitic match array clamp connected to the sense bit line clamp;

the sense bit line clamp includes a clamp portion for clamping a sense bit line,

a source electrode of the fourth PMOS tube is connected with the power supply voltage input end;

a gate of the fifth PMOS tube is connected with the output end of the phase inverter, and a source of the fifth PMOS tube is connected with a drain of the fourth PMOS tube and a gate of the fourth PMOS tube;

a drain electrode of the fourth NMOS tube is connected with a drain electrode of the fifth PMOS tube, and a grid electrode of the fourth NMOS tube is connected with a clamping voltage input end;

a drain electrode of the fifth NMOS tube is connected with a source electrode of the fourth NMOS tube and a bit line of the phase change memory array, a grid electrode of the fifth NMOS tube is connected with an output end of the phase inverter, and a source electrode of the fifth NMOS tube is grounded;

the parasitic matching array clamp includes a first clamp portion,

a source electrode of the sixth PMOS tube is connected with a source electrode of the fourth PMOS tube;

a source electrode of the seventh PMOS transistor is connected with a gate electrode of the sixth PMOS transistor and a drain electrode of the sixth PMOS transistor, and a gate electrode of the seventh PMOS transistor is connected with an output end of the inverter;

a drain electrode of the sixth NMOS transistor is connected with a drain electrode of the seventh PMOS transistor, and a gate electrode of the sixth NMOS transistor is connected with the clamping voltage input end;

and the drain electrode of the seventh NMOS tube is connected with the source electrode of the sixth NMOS tube, the grid electrode of the seventh NMOS tube is connected with the output end of the phase inverter, and the source electrode of the seventh NMOS tube is grounded.

Preferably, the fourth NMOS transistor and the sixth NMOS transistor are common-gate amplifier transistors, the source end voltages of the fourth NMOS transistor and the sixth NMOS transistor clamp the bit line voltage of the phase-change memory array, and the fourth NMOS transistor and the sixth NMOS transistor amplify the bit line voltage of the phase-change memory array.

Preferably, a first node is arranged at a connection position of the gate of the second NMOS transistor and the gate of the second PMOS transistor, a second node is arranged at a connection position of the drain of the sixth NMOS transistor and the drain of the seventh PMOS transistor, and the first node is connected with the second node.

A third node is arranged at the joint of the grid electrode of the third NMOS tube and the grid electrode of the third PMOS tube, a fourth node is arranged at the joint of the drain electrode of the fourth NMOS tube and the drain electrode of the fifth PMOS tube, and the third node is connected with the fourth node.

Preferably, the number of transistors connected between the second node of the sense bit line clamp and the fourth node of the parasitic match array clamp is the same, and the sense bit line clamp and the parasitic match array clamp have the same parasitic parameters.

Preferably, the precharge circuit includes a target bit line precharge section and a parasitic matching array precharge section connected to the target bit line precharge section;

the target bit line precharge section includes,

the source electrode of the eighth PMOS tube is connected with the power supply voltage input end;

the drain electrode of the eighth NMOS tube is connected with the gate electrode of the eighth PMOS tube and the drain electrode of the eighth PMOS tube, the gate electrode of the eighth NMOS tube is connected with the first precharge signal, and the source electrode of the eighth NMOS tube is connected with the bit line of the phase change memory array;

the parasitic match array pre-charge section includes,

a ninth PMOS tube, wherein the source electrode of the ninth PMOS tube is connected with the power supply voltage input end;

the drain electrode of the ninth NMOS tube is connected with the grid electrode of the ninth PMOS tube and the drain electrode of the ninth PMOS tube, the grid electrode of the ninth NMOS tube is connected with the first pre-charge signal, and the source electrode of the ninth NMOS tube is connected with the reference current generating circuit.

Preferably, the comparison circuit includes, in addition to the first and second comparators,

a read current converting section including,

a source electrode of the eleventh PMOS tube is connected with the power supply voltage input end, and a grid electrode of the eleventh PMOS tube is connected with a grid electrode of the fourth PMOS tube and a drain electrode of the fourth PMOS tube;

the drain electrode of the eleventh NMOS tube is connected with the grid electrode of the eleventh NMOS tube and the drain electrode of the eleventh PMOS tube, and the source electrode of the eleventh NMOS tube is grounded;

a comparison section connected to the read current conversion section, the comparison section including,

a source electrode of the thirteenth PMOS tube is connected with the power supply voltage input end, and a grid electrode of the thirteenth PMOS tube is connected with a grid electrode of the eleventh PMOS tube;

a source electrode of the fourteenth PMOS tube is connected with the power supply voltage input end;

a thirteenth NMOS tube, wherein the drain electrode of the thirteenth NMOS tube is connected with the drain electrode of the thirteenth PMOS tube, and the source electrode of the thirteenth NMOS tube is grounded;

a fourteenth NMOS tube, wherein the drain electrode of the fourteenth NMOS tube is connected with the drain electrode of the fourteenth PMOS tube, and the gate electrode of the fourteenth NMOS tube is connected with the gate electrode of the eleventh NMOS tube and the drain electrode of the eleventh NMOS tube;

a reference current converting part connected to the comparing part, the reference current converting part including,

a source electrode of the twelfth PMOS tube is connected with the power supply voltage input end, a grid electrode of the twelfth PMOS tube is connected with a grid electrode of the fourteenth PMOS tube, and a grid electrode of the sixth PMOS tube and a drain electrode of the sixth PMOS tube are connected;

and the drain electrode of the twelfth NMOS tube is connected with the grid electrode of the thirteenth NMOS tube and the grid electrode of the twelfth NMOS tube, and the source electrode of the twelfth NMOS tube is grounded.

Preferably, the reference current generating circuit includes a tenth NMOS transistor, a drain of the tenth NMOS transistor is connected to a source of the ninth NMOS transistor, a source of the sixth NMOS transistor and a drain of the seventh NMOS transistor, and is further connected to a bit line of the parasitic matching array, a gate of the tenth NMOS transistor is connected to the reference voltage input terminal, and a source of the tenth NMOS transistor is grounded.

Preferably, the parasitic matching array comprises,

a parasitic transmission gate, a drain of which is connected to the sense bit line clamping part and the target bit line precharge part, a gate of which is connected to the external read enable signal output terminal, and a source of which is connected to a parasitic phase change resistor of a parasitic matching unit;

the n parasitic matching units comprise the parasitic phase change resistors and parasitic gate tubes, drain electrodes of the parasitic gate tubes are connected with the parasitic phase change resistors, grid electrodes of the parasitic gate tubes are connected with word lines, and source electrodes of the parasitic gate tubes are suspended;

wherein n is a positive integer.

Preferably, the parasitic matching array and the phase change memory array have the same parasitic parameters.

A phase change memory high-speed data reading method is applied to the phase change memory high-speed data reading circuit and comprises,

step S1, the pre-charge control circuit outputs the second read enable signal and the first pre-charge signal based on the received first read enable signal, and when the first pre-charge signal rises to a power supply voltage, the pre-charge circuit generates the pre-charge current to simultaneously pre-charge the phase change memory array and the parasitic matching array;

step S2, the clamping circuit clamps the bit line of the phase change memory array and the bit line of the parasitic matching array to the same voltage;

s3, when the second pre-charge signal output by the clamping circuit rises to a preset value, the first pre-charge signal is changed from an effective state to an ineffective state, and the pre-charge operation is terminated;

and S4, reading data stored in the phase change memory array, generating the read current based on the state of the phase change memory array, and generating the reference current based on a parasitic matching unit.

And S5, simultaneously mirroring the reading current on the bit line of the phase change memory array and the reference current on the bit line of the parasitic matching array to the comparison circuit, comparing and outputting a reading voltage.

Preferably, the read enable signal received by the receiving end of the inverter is used as the first read enable signal, the read enable signal output by the output end after being inverted by the inverter is used as the second read enable signal, and the first read enable signal is in an active state when being raised to the power supply voltage.

Preferably, the precharge voltage of the precharge circuit is between a first reference voltage and a second reference voltage, the phase change memory array includes a crystalline phase change memory cell and an amorphous phase change memory cell, the first reference voltage is a bit line voltage of the crystalline phase change memory cell, and the second reference voltage is a bit line voltage of the amorphous phase change memory cell.

Preferably, the read current and the reference current keep consistent in a variation curve during pre-charging.

Preferably, the precharge current is greater than the read current.

Preferably, the reference current is between the maximum read current and the minimum read current, the reference current is smaller than a current flowing through a phase change memory cell in a low resistance state in the phase change memory array, and the reference current is larger than a current flowing through a phase change memory cell in a high resistance state in the phase change memory array.

The invention has the beneficial effects that: by adopting the technical scheme, the invention shortens the charging time of the parasitic capacitor of the target phase change memory array in the data reading process, has simple and efficient circuit, accelerates the data reading speed, introduces the parasitic matching array to compensate the parasitic effect, simultaneously carries out the pre-charging operation on the target array and the parasitic matching array, ensures that the charging trends of the reading current and the reference current are consistent, and avoids the generation of misreading.

Drawings

FIG. 1 is a schematic diagram of a high speed data reading circuit of a phase change memory according to an embodiment of the present invention;

FIG. 2 is a schematic diagram of a phase change memory array according to an embodiment of the present invention;

FIG. 3 is a schematic diagram of a parasitic match array in accordance with an embodiment of the invention;

FIG. 4 is a block diagram illustrating a high speed data reading method for a phase change memory according to an embodiment of the present invention;

FIG. 5 is a voltage simulation diagram for reading the phase change memory high resistance cell according to the embodiment of the present invention;

FIG. 6 is a voltage simulation diagram for reading a low resistance cell of a phase change memory according to an embodiment of the present invention.

Detailed Description

The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be obtained by a person skilled in the art without inventive efforts based on the embodiments of the present invention, shall fall within the scope of protection of the present invention.

It should be noted that the embodiments and features of the embodiments may be combined with each other without conflict.

The invention is further described with reference to the following drawings and specific examples, which are not intended to be limiting.

Phase change memory high speed data sensing circuits, as shown in fig. 1, 2, and 3, include,

a precharge control circuit 10 for receiving the first read enable signal RE1 and generating a second read enable signal RE2 and a first precharge signal V based on the first read enable signal _{PRE_A} ；

The clamp circuit 20, the clamp circuit 20 is connected to the precharge control circuit 10, the clamp circuit 20 is further connected to a phase change memory array 60 and a parasitic matching array 70, the clamp circuit 20 clamps the bit line voltages of the phase change memory array 60 and the parasitic matching array 70, respectively, and the clamp circuit 20 reads and mirrors the read current I under the action of the second read enable signal RE2 _read And a reference current I _ref ；

A pre-charging circuit 30 connected to the pre-charging control circuit 10, the clamping circuit 20 and the phase change memory array 60 and the parasitic matching array 70, the pre-charging circuit 30 being used for generating a pre-charging current I _pre Performing a precharge operation on the phase change memory array 60 and the parasitic matching array 70 simultaneously;

a comparison circuit 50 connected to the clamp circuit 20 for comparing the read current I _read And a reference current I _ref Comparing;

a reference current generating circuit 40 connected to the clamp circuit 20, the pre-charge circuit 30 and the parasitic matching array 70, the reference current generating circuit 40 being based on a reference voltage V _ref Generating a reference current I _ref ；

The invention is used for rapidly reading the storage value of the phase change storage array 60, the phase change storage array 60 comprises a plurality of phase change storage units, the phase change storage array 60 is gated by word lines and bit lines, the selected phase change storage unit is used as a target phase change storage unit 601, and furthermore, the unselected phase change storage units are not conducted.

Specifically, the parasitic match array 70 of the present invention is configured to provide parasitic parameter matching, the read current I _read And a reference current I _ref The transient curves are kept consistent in the charging process after the previous period, so that the charging time of the parasitic capacitors is the same, the influence of the parasitic capacitors on the data reading process is avoided, the false reading phenomenon is eliminated, furthermore, the pre-charging process is quick, the voltages of the target bit line and the reference bit line are improved, the reading time of the phase change memory can be reduced, and the problem that the charging time of the parasitic capacitors in the existing phase change memory array is overlong is solved.

Specifically, the phase change memory cell high-speed pre-charge data reading circuit and method provided by the invention adopt a pre-charge mode, and quickly generate a pre-charge signal to charge the bit lines of the target phase change memory cell 601 and the parasitic matching array 70 after the first read enable signal RE1 is effective, so that the voltage rise speed of the read bit line is improved, the charging time of the parasitic capacitor of the phase change memory array 60 in the reading process is shortened, the circuit is simple and efficient, and the data reading speed is accelerated;

further, the parasitic matching array 70 is introduced to generate, so that the parasitic effect is compensated; the reference current generating circuit 40 generates a controllable reference current I _ref And because the precharge operation is performed at the same time in the target array and the parasitic matching array 70, the read current I _read And a reference current I _ref The charging trends are consistent, the generation of misreading is avoided, and the reading time is reduced;

further, the comparison circuit 50 is connected to the clamp circuit 20 to clamp the phase change memory array 60 and the parasitic matching array 70 to the same voltage during the pre-charge stage, control the voltages at the differential output terminals of the comparison circuit 50 to be the same, and when the second read enable signal RE2 is asserted, the clamp circuit 20 reads the read current I after the pre-charge process is terminated _read And a reference current I _ref To the comparison circuit 50;

preferably, the present invention has a simple structure, the precharge circuit 30 does not need external clock control, and does not generate static power consumption, thereby greatly reducing the power consumption of the data reading operation of the phase change memory.

Specifically, the precharge control circuit 10 includes,

the input end of the inverter is connected with the external read enable signal input end;

a source electrode of the first PMOS tube PM1 is connected with a power supply voltage input end VDD, and a grid electrode of the first PMOS tube PM1 is connected with an output end of the phase inverter;

the grid electrode of the first NMOS tube NM1 is connected with the output end of the phase inverter, and the source electrode of the first NMOS tube NM1 is grounded;

a source electrode of the second PMOS tube PM2 is connected with a drain electrode of the first PMOS tube PM 1;

the drain electrode of the second NMOS tube NM2 is connected with the drain electrode of the first NMOS tube NM1, the grid electrode of the second NMOS tube NM2 is connected with the grid electrode of the second PMOS tube PM2, and the source electrode of the second NMOS tube NM2 is grounded;

a source electrode of the third PMOS transistor PM3 is connected to a drain electrode of the second PMOS transistor PM2, and a drain electrode of the third PMOS transistor PM3 is connected to drain electrodes of the first NMOS transistor NM1, the second NMOS transistor NM2, and the third NMOS transistor NM 3;

the drain electrode of the third NMOS tube NM3 is connected with the drain electrodes of the first NMOS tube NM1 and the second NMOS tube NM2, the grid electrode of the third NMOS tube NM3 is connected with the grid electrode of the third PMOS tube PM3, and the source electrode of the second NMOS tube NM2 is grounded.

Specifically, the output signal of the first NMOS transistor NM1 is the first pre-charge signal V in the present invention _{PRE_A} 。

Specifically, the pre-charge control circuit 10 is coupled to the clamping circuit 20 and the pre-charge circuit 30, and is configured to generate the second read enable signal RE2 and the first pre-charge signal V after the first read enable signal RE1 is asserted _{PRE_A} Controlling the clamp circuit 20 to sense and mirror the read current I _read And a reference current I _ref (ii) a Controlling the pre-charge circuit 30 to pre-charge the phase change memory array 60 and the parasitic match array 70 and applying a second pre-charge signal V _{PRE_B} After being valid, the control precharge process is terminated.

In a preferred embodiment, clamp circuit 20 includes a sense bit line clamp and a parasitic matching array clamp coupled to the sense bit line clamp;

the sense bit line clamp includes a sense bit line clamp section,

a source electrode of the fourth PMOS tube PM4 is connected with a power supply voltage input end VDD;

a grid electrode of the fifth PMOS tube PM5 is connected with an output end RE2 of the phase inverter, and a source electrode of the fifth PMOS tube PM5 is connected with a drain electrode of the fourth PMOS tube PM4 and a grid electrode of the fourth PMOS tube PM 4;

a fourth NMOS transistor NM4, the drain of the fourth NMOS transistor NM4 is connected with the drain of the fifth PMOS transistor PM5, the gate of the fourth NMOS transistor NM4 is connected with a clamping voltage input end V _READ ；

A fifth NMOS transistor NM5, a drain of the fifth NMOS transistor NM5 is connected to a source of the fourth NMOS transistor NM4 and a bit line BL of the phase change memory array 60, a gate of the fifth NMOS transistor NM5 is connected to an output terminal of the inverter, and a source of the fifth NMOS transistor NM5 is grounded;

the parasitic matching array clamp includes a first clamp portion,

a source electrode of the sixth PMOS tube PM6 is connected with a source electrode of the fourth PMOS tube PM 4;

a source electrode of the seventh PMOS transistor PM7 is connected to a gate electrode of the sixth PMOS transistor PM6 and a drain electrode of the sixth PMOS transistor PM6, and a gate electrode of the seventh PMOS transistor PM7 is connected to an output end of the inverter;

a sixth NMOS transistor NM6, a drain of the sixth NMOS transistor NM6 is connected with a drain of the seventh PMOS transistor PM7, a gate of the sixth NMOS transistor NM6 is connected with a clamp voltage input terminal V _READ ；

The drain electrode of the seventh NMOS tube NM7 is connected with the source electrode of the sixth NMOS tube NM6, the grid electrode of the seventh NMOS tube NM7 is connected with the output end of the phase inverter, and the source electrode of the seventh NMOS tube NM7 is grounded.

Specifically, the fourth NMOS transistor NM4 and the sixth NMOS transistor NM6 are common-gate amplifier transistors, the voltage of the bit line of the phase change memory array 60 is clamped by the voltage of the source terminals of the fourth NMOS transistor NM4 and the sixth NMOS transistor, and the voltage of the bit line of the phase change memory array 60 is amplified by the fourth NMOS transistor and the sixth NMOS transistor.

In a preferred embodiment, a first node is disposed at a connection between the gate of the second NMOS transistor NM2 and the gate of the second PMOS transistor PM2, a second node is disposed at a connection between the drain of the sixth NMOS transistor NM6 and the drain of the seventh PMOS transistor PM7, and the first node is connected to the second node.

A third node is arranged at the joint of the grid electrode of the third NMOS tube NM3 and the grid electrode of the third PMOS tube PM3, a fourth node is arranged at the joint of the drain electrode of the fourth NMOS tube NM4 and the drain electrode of the fifth PMOS tube PM5, and the third node is connected with the fourth node.

Further, the second node of the sense bit line clamp of the clamp circuit 20 and the fourth node of the parasitic match array clamp are connected to the first node and the third node of the precharge control circuit 10, respectively, and the number of transistors connected to the second node and the fourth node is the same, so the sense bit line clamp and the parasitic match array clamp have the same parasitic parameters.

Specifically, the second node output signal is the second pre-charge signal V _{PRE_B} Drains of the fourth NMOS transistor NM4 and the sixth NMOS transistor NM6 are respectively connected to the bit line BL of the phase change memory array 60 and the bit line BL of the parasitic matching array 70 _REF And connected to the target bit line precharge section and the parasitic matching array precharge section, respectively.

Specifically, the clamp circuit 20 includes a sense bit line clamp section and a parasitic match array clamp section, the clamp circuit 20 is connected to the phase change memory array 60, the parasitic match array clamp section is connected to the parasitic match array 70, and the input clamp voltage V is input _read Controlling the bit line voltages of the phase change memory array 60 and the parasitic match array 70 to be not less than 200mV, preferably according to a set clamp voltage V _read The value of (d) adjusts the bit line voltage.

In a preferred embodiment, the precharge circuit 30 includes a target bit line precharge section and a parasitic matching array precharge section connected to the target bit line precharge section;

the target bit line precharge section includes,

a source electrode of the eighth PMOS tube PM8 is connected with a power supply voltage input end VDD;

the drain electrode of the eighth NMOS transistor NM8 is connected with the gate electrode of the eighth PMOS transistor PM8 and the drain electrode of the eighth PMOS transistor PM8, and the gate electrode of the eighth PMOS transistor PM8 is connected with the first pre-charge signal V _{PRE_A} The source of the eighth NMOS transistor NM8 is connected to the bit line BL of the phase change memory array 60;

the parasitic matching array pre-charge section includes,

a ninth PMOS tube PM9, wherein the source electrode of the ninth PMOS tube PM9 is connected with the power supply voltage input end VDD;

a ninth NMOS transistor NM9, a drain of the ninth NMOS transistor NM9 is connected to a gate of the ninth PMOS transistor PM9 and a drain of the ninth PMOS transistor PM9, and a gate of the ninth NMOS transistor NM9 is connected to a first pre-charge signal V _{PRE_A} The source of the ninth NMOS transistor NM9 is connected to the reference current generating circuit 40.

Specifically, the precharge circuit 30 is limited by the precharge control circuit 10, the output terminal of the precharge circuit 30 is connected to the bit line of the target phase change memory cell 601, and the first precharge signal V is generated _{PRE_A} When active, generates a very large pre-charge current I _pre Precharge current I _pre Much larger than the read current I _read And a reference current I _ref 。

In a preferred embodiment, the comparison circuit 50 includes,

a read current converting section 501, the read current converting section 501 including,

a source electrode of the eleventh PMOS tube PM11 is connected with a power supply voltage input end VDD, and a grid electrode of the eleventh PMOS tube PM11 is connected with a grid electrode of the fourth PMOS tube PM4 and a drain electrode of the fourth PMOS tube PM 4;

the drain electrode of the eleventh NMOS tube NM11 is connected with the gate electrode of the eleventh NMOS tube NM11 and the drain electrode of the eleventh PMOS tube PM11, and the source electrode of the eleventh NMOS tube NM11 is grounded;

a comparison unit 503 connected to the read current conversion unit, the comparison unit 503 including,

a source electrode of the thirteenth PMOS tube PM13 is connected with the power supply voltage input end, and a grid electrode of the thirteenth PMOS tube PM13 is connected with a grid electrode of the eleventh PMOS tube PM 11;

a fourteenth PMOS tube PM14, wherein the source electrode of the fourteenth PMOS tube PM14 is connected with the power supply voltage input end;

the drain electrode of the thirteenth NMOS tube NM13 is connected with the drain electrode of the thirteenth PMOS tube PM13, and the source electrode of the thirteenth NMOS tube NM13 is grounded;

a fourteenth NMOS tube NM14, a drain of the fourteenth NMOS tube NM14 is connected to a drain of the fourteenth PMOS tube PM14, and a gate of the fourteenth NMOS tube NM14 is connected to a gate of the eleventh NMOS tube NM11 and a drain of the eleventh NMOS tube NM 11;

a reference current converting part 502 connected to the comparing part 503, the reference current converting part 502 including,

a source electrode of the twelfth PMOS tube PM12 is connected with the power supply voltage input end, and a grid electrode of the twelfth PMOS tube PM12 is connected with a grid electrode of the fourteenth PMOS tube and a grid electrode of the sixth PMOS tube PM6 and a drain electrode of the sixth PMOS tube PM 6;

a twelfth NMOS tube NM12, a drain of the twelfth NMOS tube NM12 is connected to a gate of the thirteenth NMOS tube NM13 and a gate of the twelfth NMOS tube NM12, and a source of the twelfth NMOS tube NM12 is grounded.

Specifically, as shown in fig. 5 and 6, the comparison circuit 50 is connected to the clamp circuit 20, and is configured to apply the read current I after the first read enable signal RE1 is asserted _read And a reference current I _ref And performing differential comparison, and outputting a first output voltage V1 and a second output voltage V2.

The structure of each unit in the comparison unit 503 may be any one of the conventional ones, and the functions of current conversion and comparison may be realized, and the present embodiment is not limited thereto.

In a preferred embodiment, the reference current generating circuit 40 includes a tenth NMOS transistor NM10, wherein a source of the tenth NMOS transistor NM10 is connected to a source of the ninth NMOS transistor NM10, a source of the sixth NMOS transistor NM6 and a drain of the tenth NMOS transistor NM10, and a bit line BL of the parasitic matching array 70 _REF The tenth NMOS transistor NM10 has its gate connected to the reference voltage input terminal V _REF And the source of the tenth NMOS transistor NM10 is grounded.

Specifically, the reference current generating circuit 40 connects the clamping circuit 20, the pre-charging circuit 30, the parasitic matching array 70, and the reference current generating circuit 40 according to a reference voltage V _ref Is generated as a reference current I _ref 。

Specifically, as shown in fig. 2, the phase change memory array 60 in this embodiment includes,

m target transmission gates RTG, the drain of which is connected to the clamp part of the read bit line and the precharge part of the target bit line, the gate of which is connected to the read enable signal input terminal, and the source of which is connected to the target phase change resistor R of the phase change memory cell _GST ；

The phase change memory cell comprises a target phase change resistor R _GST And a target gate tube WL, the drain electrode of which is connected with a target phase change resistor R _GST The grid electrode of the target gate tube WL is connected with a word line, and the source electrode of the target gate tube WL is grounded;

wherein n and m are both positive integers.

Specifically, as shown in fig. 2 and 3, the phase change memory array 60 is composed of a target transmission gate RTG and a phase change memory cell including a target gate WL and a target phase change resistor R _GST The target gate tube WL grid is controlled by a word line voltage enable signal, and the target phase change resistor R _GST One end of the target gate tube WL is connected with a target transmission gate RTG;

preferably, in this embodiment, the target transmission gate RTG is an NMOS transistor, and a gate of the target transmission gate RTG is connected to the first read enable signal RE1.

In a preferred embodiment, the parasitic matching array 70 includes,

parasitic transmission gate RTG _REF Parasitic transmission gate RTG _REF The drain of the sense bit line clamp section is connected to the target bit line precharge section, and the parasitic transfer gate RTG _REF The gate of the transistor is connected with a read enable signal input end and a parasitic transmission gate RTG _REF Is connected with the parasitic phase change resistor R of the parasitic matching unit 701 _REF ；

n parasitic matching units 701, wherein the parasitic matching units 701 comprise parasitic phase change resistors R _REF And parasitic gate pipe WL _REF Parasitic gate pipe WL _REF Is connected with parasitic phaseVariable resistance R _REF Parasitic gate pipe WL _REF Is connected with a word line and a parasitic gate tube WL _REF The source of (2) is suspended; wherein n is a positive integer;

parasitic matching array 70 is composed of a parasitic transmission gate RTG _REF And a parasitic matching unit 701, the parasitic matching unit 701 comprises a parasitic gate tube WL _REF And parasitic phase change resistance R _REF Parasitic gate pipe WL _REF The gate of the transistor is controlled by a word line voltage enable signal, and a parasitic phase change resistor R _REF One end is connected with a parasitic transmission gate RTG _REF The other end is connected with a parasitic gate tube WL _REF Parasitic gate pipe WL of parasitic matching unit 701 _REF The source is grounded, and the gate transistors in the phase change memory array 60 and the parasitic matching array 70 are all NMOS transistors, and the device types of the gate transistors may be set according to the needs in practical use, which is not limited to this embodiment.

In a preferred embodiment, the parasitic match array 70 has the same parasitic parameters as the bit lines of the target phase change memory cell 601; preferably, the phase change memory array 60 and the parasitic match array 70 simultaneously precharge the bit lines when the precharge enable signal is asserted, with the read current I _read And a reference current I _ref The variation trends are matched, so that data misreading caused by unstable reading current is avoided, and the reading time is shortened.

Specifically, the target phase change memory cell 601 is connected to the same bit line as the unselected phase change memory cell, only one word line and one bit line are turned on at the same time in the word line signals of the n phase change memory cell arrays, and the word line signal of the unselected phase change memory cell is inactive and at a low level.

A phase change memory high-speed data reading method applied to a phase change memory high-speed data reading circuit in any one of the embodiments, as shown in fig. 4, includes,

in step S1, the precharge control circuit 10 outputs a first precharge signal V based on the received first read enable signal RE1 _{PRE_A} When the first pre-charge signal V is applied _{PRE_A} The pre-charge circuit 30 generates a pre-charge current I when the power supply voltage rises _pre For phase change memory array 60 and parasitic matching arrayThe columns 70 are simultaneously subject to a precharge operation;

in step S2, the clamp circuit 20 couples the bit line BL of the phase change memory array 60 to the bit line BL of the parasitic match array 70 _REF Clamping to the same voltage;

step S3, when the second pre-charge signal V output by the clamping circuit _{PRE_B} When the voltage rises to a preset value, the first pre-charge signal V _{PRE_A} Changing from the active state to the inactive state, terminating the precharge operation;

step S4, reading the data stored in the target phase-change memory cell 601, and generating a read current I based on the state of the target phase-change memory cell 601 _read Generating a reference current I based on a parasitic matching unit 701 _ref 。

Step S5, read current I on bit line of phase change memory array 60 _read And the reference current I on the bit line of the parasitic matching array 70 _ref And simultaneously mirrored to the comparator circuit 50 and compared to output a sense voltage, where the output sense voltage represents the current state of the target phase change memory cell 601.

In a preferred embodiment, the inverter receives the read enable signal as a first read enable signal RE1 at the receiving end, and the inverter inverts the read enable signal to output the read enable signal as a second read enable signal RE2 at the output end, and the first read enable signal RE1 is active when the power supply voltage is raised.

In a preferred embodiment, the precharge voltage of the precharge circuit 30 is between a first reference voltage and a second reference voltage, the phase change memory cells include crystalline phase change memory cells and amorphous phase change memory cells, the first reference voltage is the bit line voltage of the crystalline phase change memory cells, and the second reference voltage is the bit line voltage of the amorphous phase change memory cells.

In a preferred embodiment, when the first read enable signal RE1 rises to the power supply voltage, the first read enable signal RE1 is asserted, the selected target phase-change memory cell 601 starts a read operation, and the first pre-charge signal V _{PRE_A} When the voltage rises from 0V to the power supply voltage, the target bit line precharge part is quickly opened to generate a precharge current I _pre Bit lines BL of the phase change memory array 60 are charged and simultaneously sentThe pre-charge part of the generation matching array is opened, and a reference current I is generated on the parasitic matching bit line _ref Read current I _read And a reference current I _ref The curve remains consistent during the precharge phase.

In a preferred embodiment, the precharge current I _pre Greater than the read current I _read In particular, a precharge current I _pre When the precharge enable is enabled, the bit lines of the phase change memory array 60 and the parasitic matching array 70 are charged at the same time, and the bit line voltage of the target phase change memory cell 601 is rapidly increased, so that the current change curve of the bit line of the phase change memory array 60 is the same as that of the bit line of the parasitic matching array 70.

In a preferred embodiment, the reference current I _ref Between the maximum and minimum read currents, reference current I _ref A reference current I less than the current flowing through the phase change memory cell in the low resistance state _ref Greater than the current flowing through the phase change memory cell in the high resistance state.

In a preferred embodiment, the read current I _read Target phase change resistance R based on target phase change memory cell 601 _GST The resistance value of (2) is generated, reference current I _ref Based on a reference voltage V _ref And (4) generating.

In a preferred embodiment:

if the reference voltage V is _ref Is greater than the voltage of the bit line of the target phase-change memory cell 601, and has a reference current I _ref The current flowing through the target phase change memory cell 601 is smaller, and the target phase change memory cell 601 is in a low resistance state;

if the reference voltage V is _ref Is smaller than the voltage of the bit line of the target phase change memory cell 601, and has a reference current I _ref Greater than the current flowing through the target phase change memory cell 601, the target phase change memory cell 601 is in a high resistance state.

In a specific embodiment, when the first read enable signal RE1 is asserted, the first target transmission gate RTG1 is turned on, and the word line WL1 of the phase change memory cell is asserted; in the first pre-charge signal V _{PRE_A} When active, the eighth NMOS transistor NM8 of the pre-charge circuit 30And the ninth NMOS transistor NM9 is turned on to start the pre-charge stage, the pre-charge current I _pre Flows through the bit lines of the phase change memory array 60 and a precharge current I _pre Charging parasitic capacitances in the parasitic matching array 70 such that the read current I _read And a reference current I _ref Ascending curves with the same trend;

further, after the first read enable signal RE1 and the second read enable signal RE2 are asserted, the fifth PMOS transistor PM5 and the seventh PMOS transistor PM7 in the clamp circuit 20 are turned on, the clamp circuit 20 is connected to the comparison circuit 50, and the bit line of the phase change memory array 60 reads the read current I corresponding to the current state of the target phase change memory cell 601 _read And a read current I is supplied through a clamp circuit 20 _read Reading into the comparison circuit 50; the reference current generating circuit 40 generates a reference current according to the reference voltage V _ref Generating a reference current I _ref The clamp circuit 20 will reference the current I _ref Read into the comparison circuit 50, reference current I _ref For applying with the read current I _read And comparing and judging the data stored in the target phase change memory cell 601, wherein the bit line voltage of the target phase change memory cell 601 is the same as the bit line voltage of the parasitic matching cell 701 in the pre-charging stage, and the voltages in the comparison process are different after the pre-charging process is ended.

The reference phase-change current is between the high resistance reading current I of the phase-change memory cell _read And a low resistance read current I _read According to the modified reference voltage V _ref A specific current value is set.

Referring to FIG. 5 and FIG. 6, when the data stored in the target memory cell is 1, the read current I is set _read Greater than the reference current I _ref (ii) a The second output voltage V2 of the comparison circuit 50 will drop to around 0V, while the first output voltage V1 of the comparison circuit 50 will rise close to the supply voltage. When the data stored in the target memory cell is 0, the read current I _read Less than the reference current I _ref (ii) a The second output voltage V2 of the comparison circuit 50 will rise close to the power supply voltage, while the first output voltage V1 of the comparison circuit 50 will drop to around 0V. The comparison circuit 50 outputs a first output voltage V1 and a second output voltageV2 to the latch circuit to obtain the final read result of the target phase change memory cell 601.

In practical use, the inverter may be added to change the correspondence between the output signal of the comparison circuit 50 and the polarity of the output port, or represent different high and low resistance states according to different output signal levels, which is not limited to the embodiment.

The random read time in the prior art is 10ns, the preferred time in the present invention is 3.5ns, compared with the conventional precharge circuit, the precharge module of the present invention does not need additional clock control, and the design of the precharge circuit 30 enables the circuit to improve the read speed compared with the prior art.

In summary, the phase change memory high-speed data reading circuit and method provided by the invention have the following beneficial effects: after the read enable signal is valid, the precharge circuit 30 charges the target phase change memory bit line and the parasitic matching bit line, so that the bit line voltage of the phase change memory array 60 is quickly increased, the parasitic capacitance charging time is shortened, and the data reading time is reduced. Meanwhile, the parasitic matching array 70 provides parasitic parameter matching, the clamp circuits of the target phase change memory array and the parasitic parameter matching array are structurally symmetrical, the number of transistors connected between nodes is equal, and the negative influence of parasitic parameters on the reading operation is greatly eliminated. Read current I _read And a reference current I _ref The transient curves are kept consistent in the charging process after the previous period, so that the influence of parasitic capacitance on the data reading process is avoided, the misreading is avoided, and the data reading speed of the phase change memory is accelerated.

While the invention has been described with reference to a preferred embodiment, it will be understood by those skilled in the art that various changes in form and detail may be made therein without departing from the spirit and scope of the invention.

Claims

1. A phase change memory high speed data read circuit, comprising,

the clamping circuit is connected with the pre-charging control circuit, the clamping circuit is further connected with a phase-change storage array and a parasitic matching array, the clamping circuit is used for clamping the bit line voltages of the phase-change storage array and the parasitic matching array respectively, and the clamping circuit is used for reading and mirroring the reading current and the reference current under the action of the second reading enabling signal;

the pre-charging circuit is connected with the pre-charging control circuit, the clamping circuit and the phase-change storage array and the parasitic matching array and is used for generating pre-charging current to carry out pre-charging operation on the phase-change storage array and the parasitic matching array simultaneously;

2. The phase change memory high speed data readout circuit of claim 1,

the pre-charge control circuit includes a pre-charge control circuit,

the source electrode of the second PMOS tube is connected with the drain electrode of the first PMOS tube;

3. The phase change memory high speed data sensing circuit of claim 2, wherein the clamping circuit comprises a sense bit line clamp and a parasitic matching array clamp connected to the sense bit line clamp;

the drain electrode of the fourth NMOS tube is connected with the drain electrode of the fifth PMOS tube, and the grid electrode of the fourth NMOS tube is connected with a clamping voltage input end;

the parasitic matching array clamp includes a first clamp portion,

a source electrode of the seventh PMOS tube is connected with a grid electrode of the sixth PMOS tube and a drain electrode of the sixth PMOS tube, and the grid electrode of the seventh PMOS tube is connected with an output end of the phase inverter;

the drain electrode of the seventh NMOS tube is connected with the source electrode of the sixth NMOS tube, the grid electrode of the seventh NMOS tube is connected with the output end of the phase inverter, and the source electrode of the seventh NMOS tube is grounded.

4. The high-speed data readout circuit for phase change memory according to claim 3, wherein the fourth NMOS transistor and the sixth NMOS transistor are common gate amplifier transistors, source terminal voltages of the fourth NMOS transistor and the sixth NMOS transistor clamp a bit line voltage of the phase change memory array, and the fourth NMOS transistor and the sixth NMOS transistor amplify the bit line voltage of the phase change memory array.

5. The phase change memory high-speed data readout circuit according to claim 3, wherein a first node is disposed at a connection between the gate of the second NMOS transistor and the gate of the second PMOS transistor, a second node is disposed at a connection between the drain of the sixth NMOS transistor and the drain of the seventh PMOS transistor, and the first node is connected to the second node.

6. The phase change memory high speed data sensing circuit according to claim 5, wherein the number of transistors connected to the second node in the sense bit line clamp and the fourth node in the parasitic match array clamp are the same, and the sense bit line clamp and the parasitic match array clamp have the same parasitic parameters.

7. The phase change memory high-speed data sensing circuit according to claim 3, wherein the precharge circuit comprises a target bit line precharge section and a parasitic matching array precharge section connected to the target bit line precharge section;

the target bit line precharge part includes,

the parasitic matching array pre-charge section includes,

a source electrode of the ninth PMOS tube is connected with the power supply voltage input end;

8. The phase change memory high-speed data readout circuit according to claim 7, wherein the comparison circuit comprises,

a read current converting section including,

a comparison unit connected to the read current conversion unit, the comparison unit including,

a fourteenth NMOS tube, wherein the drain electrode of the fourteenth NMOS tube is connected to the drain electrode of the fourteenth PMOS tube, and the gate electrode of the fourteenth NMOS tube is connected to the gate electrode of the eleventh NMOS tube and the drain electrode of the eleventh NMOS tube;

9. The phase change memory high-speed data readout circuit according to claim 8, wherein the reference current generation circuit comprises a tenth NMOS transistor, a drain of the tenth NMOS transistor is connected to a source of the ninth NMOS transistor, a source of the sixth NMOS transistor and a drain of a seventh NMOS transistor, and a bit line of the parasitic matching array, a gate of the tenth NMOS transistor is connected to a reference voltage input terminal, and a source of the tenth NMOS transistor is grounded.

10. The phase change memory high speed data readout circuit of claim 9, wherein the parasitic matching array comprises,

wherein n is a positive integer.

11. The phase change memory high speed data readout circuit of claim 10, wherein the parasitic match array has the same parasitic parameters as the phase change memory array.

12. A phase change memory high-speed data reading method applied to the phase change memory high-speed data reading circuit of any one of claims 1 to 11, comprising,

13. The method for sensing high speed data of phase change memory according to claim 12, wherein the inverter receives a read enable signal as the first read enable signal, the inverter inverts the read enable signal to output the inverted read enable signal as the second read enable signal, and the first read enable signal is asserted when the power supply voltage is raised.

14. The phase change memory high speed data sensing method of claim 12, wherein the precharge voltage of the precharge circuit is between a first reference voltage and a second reference voltage, the phase change memory array comprises crystalline phase change memory cells and amorphous phase change memory cells, the first reference voltage is a bit line voltage of the crystalline phase change memory cells, and the second reference voltage is a bit line voltage of the amorphous phase change memory cells.

15. The phase change memory high-speed data reading method according to claim 12, wherein the read current and the reference current are kept in agreement with each other in a change curve during precharging.

16. The phase change memory high speed data sensing method according to claim 12, wherein the precharge current is greater than the read current.

17. The method according to claim 12, wherein the reference current is between a maximum read current and a minimum read current, the reference current is smaller than a current flowing through a low resistance phase change memory cell in the phase change memory array, and the reference current is larger than a current flowing through a high resistance phase change memory cell in the phase change memory array.