JPH0782758B2 - Semiconductor memory device - Google Patents

Description

The present invention relates to a semiconductor memory device, and is used for a vertical read-only memory (hereinafter referred to as vertical ROM) having a large storage capacity. It relates to effective technology.

[Prior Art] Storage MOSF selectively made to be enhancement type or depletion type according to storage data of each bit
A vertical ROM in which ETs are connected in series (vertical) for each column address is known from, for example, Japanese Patent Laid-Open No. 59-116993.

In addition, the above vertical ROM and EEPROM (electrically erasable & programmable read only memory)
A current detection type sense amplifier circuit used for such as, for example, issued in October 1985, IEE
JOURNAL OF SOLID-STATE CIRCUITS VOL.SC-20, NO.
5, pp. 971-977.

[Problems to be solved by the invention]

When configuring a read-only memory with a large storage capacity, a vertical ROM suitable for high integration is used. Vertical ROM like this
Then, since the read current is reduced by making the plurality of storage MOSFETs in series, it is conceivable to use the high-sensitivity current detection type sense amplifier circuit as described above.

The current detection type sense amplifier circuit described above is the third one.
As shown in the figure, the common data line CD and the circuit power supply voltage Vc
enhancement-type MOSFET Q39 provided between c and
An enhancement type MOSFET Q40 provided between the base of the MOSFET Q39 and the ground potential of the circuit and the MOSFET Q39.
A bias circuit including a depletion type MOSFET Q41 provided between the base of the circuit and the power supply voltage Vcc of the circuit is included. The output of this bias circuit is the output MOSFETs Q42 and Q43.
Is transmitted to the inverter circuit N2 via.

Multiple memory MOSFs in memory array memory mat MM
The series circuit in which the ETQm is connected in series is connected to the common data line CD via the selection MOSFET Q44 of the Y gate circuit YG. Each storage MOSFET Qm is selectively of enhancement type or depletion type according to the storage data of each bit. The gates of the storage MOSFETs arranged in the same row of the memory mat MM have corresponding word lines W0 ...
Combined with Wm. These word lines W0 to Wm are set to the high level in the non-selected state and set to the low level in the selected state. Therefore, all storage MOs whose gates are tied to word lines other than the designated word line.
The SFET is turned on, and the storage MOSFET whose gate is coupled to the designated word line is turned on only when the storage MOSFET is a depletion type. Therefore, a read current according to the stored data of the selected memory cell is supplied to the common data line CD via the MOSFET Q39 of the bias circuit of the sense amplifier SA.

The depletion type MOSFET Q41 forming the bias circuit of the sense amplifier SA acts as a constant current source by having its gate and drain connected in common. Vertical ROM
Is selected and the designated memory cell is of the depletion type, a read current flows. Therefore, the level of the common data line CD becomes a relatively low level determined by the conductance of the MOSFET Q39 and the conductance ratio of the selection MOSFET Q44 of the Y gate circuit YG and the plurality of storage MOSFETs Qm. As a result, the input level of the inverter circuit N2 is raised, and as a result, the output signal of the inverter circuit N3, that is, the output signal of the sense amplifier SA becomes a logical high level. On the other hand, when the designated memory cell is of the enhancement type, the read current does not flow through the common data line CD, so that the level of the common data line CD remains relatively high. Therefore, the input level of the inverter circuit N2 is lowered, and as a result, the output signal of the inverter circuit N3, that is, the output signal of the sense amplifier SA becomes a logic low level.

As described above, the depletion type MOSFET Q40 is used as a constant current source, and its current value is within the predetermined range.
Unaffected by changes in c. Also, common data line CD
Is set to a level determined by the conductance of the MOSFETs Q39 to Q41 and the conductance ratio of the selection MOSFET Q44 of the Y gate circuit YG and the plurality of storage MOSFETs Qm, and is limited to a relatively small signal amplitude. Therefore, the common data line CD
Also, although a relatively large parasitic capacitance is coupled to the data line in the memory mat, the read operation as a read-only memory is speeded up and has no power supply voltage dependency.

However, when the current detection type sense amplifier as described above is used for a vertical ROM having a large storage capacity, the inventors of the present application have found that the following problems occur. That is, as the storage capacity of the vertical ROM increases, the number of storage MOSFETs that make up the series circuit increases and the storage MOSF
As the ET itself is miniaturized, the read current passed through the common data line CD becomes a small value of, for example, about 10 μA. On the other hand, the electrical characteristics of each MOSFET and the inverter circuit N2 that form the bias circuit have process dependence. From these facts, the amplitude of the input level of the inverter circuit N2 is limited, the center level of the inverter circuit N2 fluctuates due to process variations, and the level determination operation of the sense amplifier SA becomes uncertain, and the vertical ROM read operation is It becomes unstable.

It is an object of the present invention to provide a semiconductor memory device such as a high-sensitivity vertical ROM in which a read operation is speeded up and stabilized.

The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

[Means for solving problems]

The outline of a typical one of the inventions disclosed in the present application will be briefly described as follows. That is, a dummy circuit is provided in the memory array and column selection circuit of the vertical ROM, and the sense amplifier circuit thereof has an enhancement-type first circuit provided between the common data line and the power supply voltage of the circuit.
An enhancement type second MOSFET provided between the MOSFET and the base of the first MOSFET and the ground potential of the circuit, the base of which is coupled to the common data line, and the first MOSFET.
A depletion type third MOSFET provided between the base of the MOSFET and the power supply voltage of the circuit, the base of which is commonly connected to the source of the MOSFET, and supplies a reference current or a read current to the dummy circuit and the common data line, respectively. Two sets of bias circuits and a differential amplifier circuit that receives the output signals of these bias circuits are provided.

[Work]

According to the above-mentioned means, the level amplitude of the common data line is limited by the bias circuit having less power supply dependency, thereby eliminating the power supply dependency of the sense amplifier circuit and speeding up the read operation as the vertical ROM. By providing the dummy circuit, the process dependence of the sense amplifier circuit can be eliminated and the reading operation of the vertical ROM can be stabilized.

〔Example〕

FIG. 2 shows a circuit block diagram of an embodiment of a vertical ROM to which the present invention is applied. Although not particularly limited, each circuit element shown in the figure is formed on one semiconductor substrate such as single crystal silicon by a known semiconductor integrated circuit manufacturing technique. In the following figures, the MOSFET with an arrow added to its channel (back gate) is a P-channel MOSFET, and the MOSFET with a straight line added to its channel is a depletion type N-channel MO.
It is SFET. MO that is not added to the channel part
The SFET is an enhancement type N-channel MOSFET.

Although not particularly limited, the vertical ROM memory cell of this embodiment is formed by an N-channel MOSFET. Therefore, this vertical ROM is formed on a semiconductor substrate made of single crystal P-type silicon. The N-channel MOSFET is formed on the surface of the P-type semiconductor substrate such as a source region, a drain region, and a semiconductor substrate surface between the source region and the drain region via a thin gate insulating film. It is composed of a gate electrode made of silicon. The P-channel MOSFET is formed in the N-type well region formed on the P-type semiconductor substrate.

The memory array of the vertical ROM is composed of two memory mats MMU and MML, although not particularly limited thereto. Pre-gate circuit PG corresponding to these memory mats MMU and MML
U and PGL are provided, and these pre-gate circuits PG
A Y gate circuit YG is provided commonly to U and PGL.

Memory mats MMU and MML are regularly arranged 2 ×
(N + 2) × (m + 1) memory MOSFETs (memory cells)
Composed of Qm. Of these memory MOSFET Qm,
2 × (m + 1) storages connected to the dummy data line Dd
The MOSFET Qm is a dummy memory cell. One of the m + 1 dummy memory cells connected in series (two in each memory mat) is a depression type MOSFET, and its gate is supplied with the ground potential of the circuit. The other dummy memory cells are enhancement type MOSFETs, and the circuit power supply voltage Vcc is supplied to their gates. In addition, the information storage MOSFET Qm other than the storage MOSFET Qm that is the dummy memory cell, for example, by selectively performing ion implantation to each channel portion by a mask that is optionally created for each user,
It is a depletion type or an enhancement type and holds stored data of logical "1" or logical "0". In the memory mats MMU and MML (in the present embodiment, a dotted line is added to the channel portion), the gates of the 2 × (n + 2) storage MOSFETs Qm arranged in the same row have corresponding word lines W0. ~ Wm respectively. In addition, m arranged in the same column of the memory mats MMU and MML
+1 memory MOSFET Qm is formed in series, and 2 ×
(N + 2) series circuits are configured. These series circuits are, on the one hand, coupled to the circuit ground potential.
In addition, these series circuits, in the other, through the corresponding selection MOSFETs Q15 to Q26 or Q27 to Q38 of the pre-gate circuit PGU or PGL, two sets each to the corresponding data line D0 to Dn or the dummy data line Dd. Be combined.

The word lines W0 to Wm of the memory mats MMU and MML are commonly connected to each other and coupled to the X address decoder XDCR as row selection lines XO to Xm. These row selection lines XO to Xm are set to the logic high level in the non-selected state and to the logic low level in the selected state. As a result, the MOSFET Qm coupled to the non-selected row selection lines XO to Xm and the word lines W0 to Wm is turned on regardless of the stored data. In addition, the row selection lines XO to Xm that are in the selected state
And the memory MOSFET Qm coupled to the words W0 to Wm is turned on only when the memory MOSFET Qm is of depletion type. At this time, when the storage MOSFET Qm is of the enhancement type, the gate thereof is set to the low level, so that the storage MOSFET Qm is turned off. Therefore, when the designated storage MOSFET Qm is of the depression type, that is, when the storage MOSFET Qm holds the storage data of logic "1", the Y gate circuit YG and the pregate circuit PG are
A discharge path of the corresponding data line is formed via a series circuit of the selection MOSFET of U or PGL and the memory mat MMU or MML. On the other hand, when the designated storage MOSFET Qm is the enhancement type, that is, when the storage MOSFET Qm holds the storage data of logic "0", the above discharge path is not formed.

The storage MOSFET Qm of the dummy memory cell column coupled to the dummy data line Dd is turned on regardless of which word line is selected, so that a discharge path via the dummy data line Dd is formed.

X address signals AX0 to AXi-1 are supplied to the X address decoder XDCR via external terminals AX0 to AXi-1. Also, a timing signal φce is supplied from a timing generation circuit TG described later. The timing signal .phi.ce is formed according to the chip enable signal () supplied as a control signal, and is selectively set to a logic high level in the selected state of the vertical ROM.

The X address decoder XDCR is operated in the selected state of the vertical ROM in which the timing signal φce is at a logical high level, and X address signals AX0 to AXi supplied from the outside are supplied.
-1 is decoded to bring one row selection line XO to Xm and word line W0 to Wm designated by these address signals into a selected state of high level. As mentioned above, the row select line XO
-Xm and word lines W0-Wm are set to the logic high level in the non-selected state and to the logic low level in the selected state.

Pre-gate circuits PGU and PGL have memory mats MMU and M
2 × (n + 2) sets of selection MOSFETs Q15 / Q16 to Q25 / Q26 or Q27 / Q28 to Q37 / Q38 provided corresponding to the series circuit of ML
It is composed respectively. The switch MOSFETs of each set are formed in series, and one of them is commonly connected to two sets of corresponding data lines D0 to Dn as described above.

Pre-gate circuit PGU odd-numbered selection MOSFETs Q15 to Q25
Gates are commonly connected, and AND gate circuit AG1
Coupled to the output terminal of. MO for selecting these odd numbers
The SFETs Q15 to Q25 are alternately of enhancement type or depletion type with the MOSFET Q17 at the head. On the other hand, the gates of the even-numbered selection MOSFETs Q16 to Q26 of the pre-gate circuit PGU are similarly commonly connected.
It is connected to the output terminal of AG2. These even-numbered selection MOSFETs Q16 to Q26 are alternately depletion type or enhancement type, with the MOSFET Q16 at the head. That is, one of the two selection MOSFETs in each set is an enhancement type, and the other is a depletion type.

A selection signal UM is supplied from the predecoder PDCR to one input terminal of each of the AND gate circuits AG1 and AG2. The predecoder PDC is connected to the other input terminal of the AND gate circuit AG1.
The selection signal LC is supplied from R. The selection signal RC is supplied from the predecoder PDCR to the other input terminal of the AND gate circuit AG2. These selection signals UM, LC
And RC are formed by the predecoder PDCR based on the highest X address signal AXi and Y address signal AYj supplied from the outside. That is, the selection signal UM is set to the logic low level in the non-selected state, and the designated storage MOSF
Set to a logic high level when ETQm is placed in the memory mat MMU. Further, the selection signal LC is set to a logic low level in the non-selected state, and is set to a logic high level when the designated storage MOSFET Qm is included in the series circuit arranged on the left side across the corresponding data lines D0 to Dn. It Further, the selection signal RC is set to a logic low level in the non-selected state, and the designated storage MOSFET Qm corresponds to the data line D0.
It is set to a logic high level when it is included in a series circuit arranged on the right side across ~ Dn. As a result, the output signal UL of the AND gate circuit AG1 is output when the selection signals UM and LC are both at the logic high level, that is, the designated storage MO.
When SFETQm is included in the series circuit arranged on the left side of the corresponding data line D0 to Dn of the memory mat MMU, it is set to the logic high level. Similarly, the output signal UR of the AND gate circuit AG2 is arranged when the selection signals UM and RC are both at the logic level, that is, the designated storage MOSFET Qm is arranged on the right side of the corresponding data line D0 to Dn of the memory mat MMU. A logic high level when included in a serial circuit.

In the pre-gate circuit PGU, the depletion type selection MOSFETs Q16, Q17, Q20, Q21, Q24 and Q25 are always turned on. Therefore, when the output signal UL of the AND gate circuit AG1 is set to a logic high level, the enhancement type selection MOSFETs Q15, Q19 and Q23 etc. are turned on all at once, and the left side of each data line D0 to Dn of the memory mat MMU. From the series circuit arranged at, one storage MOSFET Qm designated by the word lines W0 to Wm is selected. Also, the output signal UR of the AND gate circuit AG2 is set to a logical high level, so that the enhancement type selection MOSFETs Q18, Q22 and Q26 are turned on all at once, and the right side of each data line D0 to Dn of the memory mat MMU. From the series circuit arranged at, one storage MOSFET Qm designated by the word lines W0 to Wm is brought into the selected state.

On the other hand, like the pre-gate circuit PGU, the pre-gate circuit PGL
The gates of the odd-numbered selection MOSFETs Q27 to Q37 are commonly connected and further coupled to the output terminal of the AND gate circuit AG3. These odd numbered selection MOSFETs Q27-Q37 are
Starting from SFETQ29, they are alternately enhancement type or depletion type. On the other hand, the gates of the even-numbered selection MOSFETs Q28 to Q38 of the pre-gate circuit PGL are similarly connected in common and further coupled to the output terminal of the AND gate circuit AG4. These even-numbered selection MOSFETs Q28-Q38
Are alternately of the depression type or the enhancement type with the MOSFET Q28 at the head.

The selection signal LM is supplied from the predecoder PDCR to one input terminal of the AND gate circuits AG3 and AG4. The predecoder PDC is connected to the other input terminal of the AND gate circuit AG3.
The selection signal LC is supplied from R. In addition, the predecoder PDCR is connected to the other input terminal of the AND gate circuit AG4.
From, the selection signal RC is supplied. The selection signal LM, like the other selection signals UM, LC and RC, is the highest X address signal AXi supplied from the outside by the predecoder PDCR.
And the Y address signal AYj. That is, the selection signal LM is at a logic low level in the non-selected state, and is at a logic high level when the designated storage MOSFET Qm is arranged in the memory mat MML. As a result, the output signal LL of the AND gate circuit AG3 becomes the selection signal LM.
And LC are logically high levels originally, that is, when the designated storage MOSFET Qm is included in the series circuit arranged on the left side of the corresponding data line D0 to Dn of the memory mat MML, the logical high level is obtained. . Similarly, the output signal LR of the AND gate circuit AG4 is stored in the memory when the selection signals LM and RC are both at the logic high level, that is, the designated storage.
The MOSFET Qm corresponds to the data line D0 to Dn of the memory mat MML.
It is set to a logic high level when it is included in the series circuit arranged on the right side of.

In the pre-gate circuit PGL, the depletion type selection MOSFETs Q28, Q29, Q32, Q33, Q36 and Q37 are always turned on. Therefore, when the output signal LL of the AND gate circuit AG3 is set to the logical high level, the enhancement type selection MOSFETs Q27, Q31, Q35, etc. are turned on all at once, and the left side of each data line D0 to Dn of the memory mat MML. From the series circuit arranged at, one storage MOSFET Qm designated by the word lines W0 to Wm is brought into the selected state. In addition, the output signal LR of the AND gate circuit AG4 is set to a logical high level, so that the enhancement type selection MOSFETs Q30, Q34 and Q38 are simultaneously turned on, and the right side of each data line D0 to Dn of the memory mat MML. From the series circuit arranged at, one storage MOSFET Qm designated by the word lines W0 to Wm is brought into the selected state.

To the predecoder PDCR, via the external terminals AXi and AYj,
The highest X address signal AXi and Y address signal AYj are supplied. Further, the timing signal φce is supplied from the timing generation circuit TG.

The predecoder PDCR is selectively operated in the selected state of the vertical ROM in which the timing signal φce is at a logic high level, and decodes the highest X address signal AXi and Y address signal AYj supplied from the outside. Then, the selection signals UM, LM, LC and RC are set to a logical high level in a predetermined combination.

The data lines D0 to Dn to which the memory MOSFETs Qm specified by the word lines W0 to Wm of the memory mat MMU or MML are selectively connected are the selection MOSFETs Q12 to Q13 of the Y gate circuit YG.
Through, and is selectively connected to the common data line, and further connected to one input terminal of the sense amplifier SA. In addition, the dummy data line Dd to which the dummy storage MOSFET Qm is coupled
Is directly connected to the other input terminal of the sense amplifier SA as the dummy data line Dd via the MOSFET Q14 of the Y gate circuit YG.

The Y gate circuit YG is composed of n + 2 selection MOSFETs Q12 to Q14. Of these selection MOSFETs, MOSF
Corresponding column selection signals Y0 to Yn are supplied from the Y address decoder YDCR to the gates of ETQ12 to Q13, respectively.
These column selection signals Y0 to Yn are set to a logical low level in the non-selected state, and the Y address signal AY in the selected state.
One corresponding to the data line designated by 0 to AYj-1 is selectively set to the logic high level. The timing signal φce is supplied from the timing generation circuit TG to the gate of the MOSFET Q14. From this, the dummy data line Dd is
While the timing signal φce is at the logic high level and the vertical ROM is in the selected state, it is constantly connected to the other input terminal of the sense amplifier SA via the MOSFET Q14.

The Y address decoder YDCR receives the Y address signals AY0 to AYj− excluding the most significant bit via the external terminals AY0 to AYj−1.
1 is supplied. Further, the above timing signal φce is supplied from the timing generation circuit TG.

The Y address decoder YDCR is selectively operated in the selected state of the vertical ROM in which the timing signal φce is at a logic high level, and is supplied from the outside with the Y address signal.
AY0 to AYj-1 are decoded, and the column selection signals Y0 to Yn corresponding to the data lines designated by these address signals are brought to the selected state of logical high level.

As will be described later, the sense amplifier SA includes two sets of bias circuits that supply a read current and a reference current to the common data line CD and the dummy data line Dd, respectively, and differential amplification that receives output signals of these bias circuits. It is a current detection type sense amplifier circuit including a circuit. The timing signal φse is supplied to the sense amplifier SA from the timing generation circuit TG. This timing signal φse is set to a logical low level when the vertical ROM is not selected.
Is selected and the memory MO specified on the common data line CD
It is set to a logical high level at the timing when the read signal according to the storage data of SFETQm is established.

The sense amplifier SA is selectively activated by a logic high level of the timing signal φse, and a read signal from the storage MOSFET transmitted via the common data line CD is transmitted as a reference to the dummy data line Dd. Judges and amplifies based on the signal. The output signal of the sense amplifier SA is transmitted to the data output buffer DOB.

The input terminal of the data output buffer DOB is coupled to the output terminal of the sense amplifier SA, and the output terminal thereof is coupled to the data output terminal DO. Also, the data output buffer DOB
From the timing generator TG to the timing signal φoe
Is supplied. The timing signal φoe is formed according to the output enable signal ▲ ▼ which is supplied as a control signal from the outside. The timing signal φoe is set to a logic low level in the non-selected state of the vertical ROM, and the selected RO
M is brought into the selected state, and the read signal output from the designated memory MOSFET Qm is amplified to the logic high level by the sense amplifier SA and established.

The data output buffer DOB is selectively activated by the logic level of the timing signal φoe,
The read signal output from SA is further amplified and sent from the data output terminal DO to an external device. When the timing signal φoe is set to the logic low level, the output of the data output buffer DOB is in the high impedance state.

The timing generation circuit TG includes a chip enable signal ▲ ▼ and an output enable signal ▲ ▼ which are externally supplied as control signals via external terminals ▲ ▼ and ▲ ▼.
Based on the above, the above various timing signals are formed and supplied to each circuit.

FIG. 1 shows a circuit diagram of an embodiment of the sense amplifier SA of the vertical ROM of FIG. In the figure, the memory mat
The case where the memory MOSFET Qm coupled to the data line D0 is selected in the MMU is shown as an example. Therefore, the circuits related to the data line D0 and the dummy data line Dd of the memory mat MMU, the pre-gate circuit PGU, and the Y gate circuit YG are duplicated. Descriptions of these duplicated portions will be omitted.

In FIG. 1, the common data line CD is an enhancement type N-channel MOSFET Q6 (first MOSF) of the sense amplifier SA.
ET) source. The drain of this MOSFET Q6 is coupled to the circuit power supply voltage Vcc. An enhancement type N-channel MOSFET Q7 (second MOSFET) is provided between the gate of the MOSFET Q6 and the ground potential of the circuit.
The gate of the MOSFET Q7 is coupled to the source of the MOSFET Q6, that is, the common data line CD. A depletion type N-channel MOSFET Q8 (third MOSFET) is provided between the gate of the MOSFET Q6 and the power supply voltage Vcc of the circuit. this
The gate of MOSFET Q8 is the source of MOSFET Q8, the MOSFET
Bound to the gate of Q6. These MOSFETs Q6 to Q8 form a first bias circuit for the common data line CD.
The source of the MOSFET Q8 and the drain of the MOSFET Q7, which are connected in common, are used as the output terminal of this bias circuit, and further form one differential MOSFET of the differential amplifier circuit N-channel
Coupled to the gate of MOSFET Q3.

The depletion-type N-channel MOSFET Q8 of the first bias circuit is always in a weekly ON state when its gate and source are commonly connected and the gate-source voltage is 0V. Further, since the drain-source voltage is set to a predetermined value, the MOSFET Q8 operates in a saturated state, so that it functions as a constant current source that is not affected by a relatively small change in the power supply voltage Vcc.

In the non-selected state of the vertical ROM, all the selection MOSFETs of the Y gate circuit YG are turned off and the common data line CD is in a floating state. At this time, assuming that the source potential of the MOSFET Q8 of the sense amplifier SA, that is, the output voltage of this bias circuit is Vs, the parasitic capacitance Cs coupled to the common data line CD is Vs−
It is charged up to V _TH (V _TH is the threshold voltage of MOSFET Q6). Further, this charge potential turns on the MOSFET Q7. In other words, the output voltage Vs of the bias circuit is set by the ratio of the conductances of the MOSFETs Q7 and Q8 that are turned on, and the parasitic capacitance Cs of the common data line CD is charged to a voltage according to the output voltage Vs. The output voltage Vs of the first bias circuit determines the operating point of the differential amplifier circuit. Therefore, MOSFETs Q7 and Q8 have the most efficient operating point, namely the sense amplifier.
It is designed to have a conductance that maximizes the sensitivity of SA.

On the other hand, in FIG. 1, the dummy data line Dd is coupled to the source of the enhancement type N-channel MOSFET Q9 (first MOSFET) of the sense amplifier SA. The drain of this MOSFET Q9 is coupled to the circuit supply voltage Vcc. MOSFET Q9
An enhancement-type N-channel MOSFET Q10 (second MOSFET) is provided between the gate of and the ground potential of the circuit. The gate of the MOSFET Q10 is coupled to the source of the MOSFET Q9, that is, the dummy data line Dd. MOSFET Q9
A depletion-type N-channel MOSFET Q11 (third MOSFET) is provided between the gate of the gate and the power supply voltage Vcc of the circuit. The gate of MOSFET Q11 is coupled to the source of MOSFET Q11, the gate of MOSFET Q9. These MOSF
ETQ9 to Q11 form a second bias circuit for the dummy data line Dd. The source of the MOSFET Q11 and the drain of the MOSFET Q10, which are commonly connected, are used as the output terminal of the bias circuit, and are further coupled to the gate of the N-channel MOSFET Q4 that constitutes the other differential MOSFET of the differential amplifier circuit.

The depression type N-channel MOSFET Q11 of the second bias circuit is always in a weekly ON state when its gate and source are commonly connected and the gate-source voltage is 0V. Also, its drain
By setting the source-to-source voltage to the desired value, MOSFET Q1
Since 1 operates in a saturated state, it functions as a constant current source that is not affected by a relatively small fluctuation of the power supply voltage Vcc.

In the non-selected state of the vertical ROM, the MOSFET Q14 is turned off by the low level of the timing operation φce, and the dummy data line Dd is floated. At this time, the sense amplifier
When the source potential of the MOSFET Q11 of SA, that is, the output voltage of this bias circuit is Vd, the parasitic capacitance Cd coupled to the dummy data line Dd is charged to Vs−V _TH (V _TH is the threshold voltage of MOSFET Q9). Further, this charge potential turns on the MOSFET Q10. In other words, the output voltage Vd of the bias circuit is set by the ratio of the conductances of the MOSFETs Q10 and Q11 that are turned on, and the parasitic capacitance Cd of the dummy data line Dd is charged to the potential according to the output voltage Vd. The output voltage Vd of the second bias circuit determines the operating point of the differential amplifier circuit together with the voltage Vs. Therefore, MOSFETs Q10 and Q11 are designed to have a conductance that makes this operating point most efficient.

In this embodiment, further, the bias voltages Vs and Vd, in other words, the precharge levels of the common data line CD and the dummy data line Dd are equalized to speed up the read operation. Therefore, the conductance ratio of the MOSFETs Q7 and Q8 is made equal to the conductance ratio of the MOSFETs Q10 and Q11. As a result, the minute currents that have begun to flow through the common data line CD and the dummy data line Dd at the start of the selection state described later can be regarded as read as they are. That is, the amplification operation by the sense amplifier SA is performed immediately after the occurrence of reading.

The conductance of MOSFETs Q9, Q10 and Q11 is MOSFE.
It is half the conductance of TQ6, Q7 and Q8.

When the vertical ROM is selected, the common data line CD has Y
A series circuit including the selected storage MOSFET Qm is connected via the selection MOSFETs of the gate circuit YG and the pre-gate circuit PGU. At this time, when the designated storage MOSFET Qm is of the enhancement type, that is, when the storage data of logic “0” is held, the discharge potential is not formed, and therefore the charge potential of the common data line CD is maintained as it is. On the other hand, when the designated storage MOSFET Qm is of the depletion type, that is, when the storage data of logic "1" is held, a discharge path is formed through this storage MOSFET Qm, and the potential of the common data line CD decreases. In this embodiment, when the discharge path is formed, the conductance of the MOSFET Q7 is reduced and the output voltage Vs of the bias circuit rises. Further, as the output voltage Vs rises, the conductance of the MOSFET Q6 increases and the read current for the common data line CD increases. In other words, the lowering of the potential of the common data line CD increases the read current by the amount that the conductance of the MOSFET Q7 is reduced. The ratio limits the high level of the output voltage Vs. That is, the designated storage MOSFET Qm is of the depletion type or the enhancement type according to the stored data, so that the output voltage Vs is relatively high (lower than the normal high level) or relatively low (higher than the normal low level). ) Low level. In addition, the high level of this output voltage Vs /
Since the low-level voltage difference, that is, the signal amplitude is made relatively small, for example, about 1V, the charge and discharge operations are speeded up even though a relatively large capacitive load is coupled to the common data line CD. To be done. Further, as described above, since the MOSFET Q8 functions as a constant current source, the output voltage Vs is
It will not be affected by fluctuations in Vcc.

When the vertical ROM is set to the selected state, the selection MOSFET and the storage MOSFET Qm that form the dummy circuit of the memory mat including the selected memory cell are coupled to the dummy data line Dd. The dummy data line Dd is an enhancement type N-channel MOSFET Q9 (first MOSFET) of the sense amplifier SA.
To be combined with the source. As mentioned above, the dummy data line
The storage MOSFET Qm of the dummy memory cell coupled to Dd is an enhancement type MOSFET in which one of the memory cell columns receives the circuit ground potential at its gate, and the rest receives the circuit power supply voltage Vcc at its gate. Since it is a type MOSFET, a discharge path is always formed by the dummy data line Dd when the vertical ROM is selected.

In this embodiment, the common data line CD and the dummy data line
When a discharge path is formed on both sides of Dd, it becomes as follows. That is, since the conductance of each of the MOSFETs Q9, Q10 and Q11 is set to half the conductance of the MOSFETs Q6, Q7 and Q8, the current flowing through the dummy data line Dd becomes approximately half the current flowing through the common data line CD. On the other hand, if the difference in the conductance of the bias circuit is ignored, the current flowing through the dummy data line Dd becomes the common data line.
It is substantially the same as the minimum current flowing through the CD. The current flowing through the common data line CD is the lowest current when a discharge path is formed when only the selected storage MOSFET is the depletion type and the other is the enhancement type. Therefore, in one dummy cell, one of the memory MOSFETs Qm, which is a dummy memory cell, is a depletion type MOSFET and the other is an enhancement type MOSFET.

Therefore, the current flowing through the dummy data line Dd is half the minimum current that may flow through the common data line CD. In other words, the speed at which the bias voltage Vd drops due to the formation of the discharge path is
Vs is half the slowest falling speed.

The output voltage Vd of the second bias circuit is a predetermined voltage determined by the ratio of the conductance of the MOSFETs Q9 to Q11 forming the second bias circuit and the conductance of the selection MOSFET and the storage MOSFET Qm forming the dummy circuit. .
This voltage value is used as a reference potential for determining the logic level of the common data line CD in the differential amplifier circuit described later. Needless to say, this reference potential is not affected by the fluctuation of the power supply voltage Vcc. Further, since the selection MOSFET and the storage MOSFET Qm that form these dummy circuits are formed close to the information storage selection MOSFET and the storage MOSFET Qm, similar process variations are exhibited.

The differential amplifier circuit of the sense amplifier SA has the basic configuration of two differential MOSFETs Q3 and Q4 whose sources are commonly connected. An N-channel MOSFET Q5 receiving the timing signal φse at its gate is provided between the commonly connected sources of the differential MOSFETs Q3 and Q4 and the ground potential of the circuit. This timing signal φse is the vertical RO signal as described above.
It is set to logical low level when M is not selected, and vertical ROM
Is set to a selected state, and is set to a logical high level at the timing when the read signal from the designated storage MOSFET Qm is established on the common data line CD. When the vertical ROM is selected and the timing signal φse is set to the logic high level, the MO
The SFETQ5 is turned on, and the operating current is supplied to the differential MOSFETs Q3 and Q4.

A P-channel MOSFET Q1 for load is provided between the drain of the differential MOSFET Q3 and the power supply voltage Vcc of the circuit. A similar P-channel MOSFET Q2 for load is provided between the drain of the differential MOSFET Q4 and the power supply voltage Vcc of the circuit. These MOSFETs Q1 and Q2 have their gates connected in common and are further coupled to the drain of MOSFET Q2, thereby forming a current mirror form and forming an active load circuit. The drain of the MOSFET Q3 serves as the output terminal of this differential amplifier circuit and is coupled to the input terminal of the inverter circuit N1.
The output signal of the inverter circuit N1 is used as the output signal of the sense amplifier SA and is supplied to the data output buffer DOB.

The differential amplifier circuit based on the differential MOSFETs Q3 and Q4 is
As a current switch circuit in which the vertical ROM is set to the selected state and the timing signal φse is set to the logic high level to selectively set the operating state, and the reference potential Vd formed by the dummy data line Dd is used as the logic threshold. To work. That is, as mentioned above, the specified memory
When the MOSFET Qm is the enhancement type, that is, when the designated storage MOSFET Qm is configured to hold the storage data of logic "0", the discharge path of the common data line CD is not formed and the output of the first bias circuit is output. Data Vs
Is set to a relatively low level. Therefore, the differential MO
The SFET Q3 is turned off, and the drain voltage of the differential MOSFET Q3, that is, the output signal of this differential amplifier circuit becomes a relatively high level. As a result, the output signal of the inverter circuit N1, that is, the output signal of the sense amplifier SA becomes a logic low level.

On the other hand, when the designated memory MOSFET Qm is of the depletion type, that is, the designated memory MOSFET Qm is a logic "1".
When the stored data is stored, the discharge path of the common data line CD is formed, and the output voltage Vs of the first bias circuit is set to a relatively high level.
Therefore, the differential MOSFET Q3 is turned on and the differential MOSFET
The drain voltage of Q3, that is, the output signal of the differential amplifier circuit becomes a relatively low level. As a result, the output signal of the inverter circuit N1, that is, the output signal of the sense amplifier SA is
It becomes a logical high level.

That is, the output signal of the sense amplifier SA is determined only when the vertical ROM is in the selected state and the timing signal φse is at the high level, and the level thereof is the designated storage MOSF.
Depending on whether the storage data of ETQm is logic "0" or logic "1", it is selectively set to a logic low level or a logic high level.

As described above, the sense amplifier SA of the vertical ROM of this embodiment is
Is composed of two sets of bias circuits that supply a read current or a reference current to the common data line CD and the dummy data line Dd, respectively, and a differential amplifier circuit that receives output signals of these bias circuits. These bias circuits are depletion type N-channel MOSFs that are used as constant current sources.
Includes ET respectively. Further, the dummy selection MOSFET and the storage MOSFET Qm coupled to the dummy data line Dd are formed close to the selection MOSFET and the information storage MOSFET Qm of the column selection circuit, respectively. Therefore, the common data line CD is
It has a relatively small signal amplitude determined by the conductance ratio of the MOSFET constituting the bias circuit and the conductance ratio of the selection MOSFET and the storage MOSFET Qm, and is not affected by the fluctuation of the power supply voltage Vcc. Therefore, the reading operation of the vertical ROM is speeded up and stabilized even though a relatively large capacitive load is coupled to the common data line CD. The potential of the dummy tape line Dd supplied as the reference potential of the differential amplifier circuit is the common data line.
It exhibits the same process variation as the CD read signal.
Therefore, the operation of determining the logic level of the read signal of the sense amplifier SA is stabilized, and the read operation of the vertical ROM is further stabilized.

As shown in the above embodiment, the present invention is applied to the vertical ROM.
When applied to a semiconductor memory device such as the above, the following effects can be obtained. That is, (1) a vertical ROM sense amplifier circuit is provided between a common data line or a dummy data line and a power supply voltage of the circuit, and an enhancement type first MOSFET and the first MOSFET.
Enhancement type second MOSFET and the first MOSFET which are provided between the base and the ground potential of the circuit and whose base is coupled to the common data line or the dummy data line.
Of a depletion type third MOSFET which is provided between the base and the power supply voltage of the circuit and whose base is commonly connected to its source, and supplies a read current or a reference current to the common data line or the dummy data line, respectively. By configuring with two sets of bias circuits and a differential amplifier circuit that receives the output signals of the respective bias circuits, it is possible to obtain an effect that the level amplitude of the common data line can be limited by the bias circuit having less power supply dependency.

(2) According to the above item (1), the charging and discharging operations of the common data line can be speeded up, and the amplifying operation of the sense amplifier circuit and the reading operation as the vertical ROM can be speeded up.

(3) According to the above item (1), it is possible to suppress the power supply dependency of the read signal level and stabilize the amplification operation of the sense amplifier circuit and the read operation of the vertical ROM.

(4) By forming the selection MOSFET and the storage MOSFET coupled to the dummy data line close to the selection MOSFET and the information storage MOSFET that form the column selection circuit, respectively, the read signal and the dummy data line are used. By making the formed reference potentials exhibit the same process variation, it is possible to stabilize the logical judgment operation of the read signal by the sense amplifier circuit, stabilize the read operation of the vertical ROM, and improve the sensitivity. can get.

Although the invention made by the present inventor has been specifically described based on the embodiments, the present invention is not limited to the above embodiments and various modifications can be made without departing from the scope of the invention. Nor. For example, in the sense amplifier SA of FIG. 1, the common data line CD and the dummy data line
High resistance load means may be provided between Dd and the ground potential of the circuit. Further, the reference potential formed by the dummy data line Dd may be set to the intermediate level of the read signal by changing the sizes of the MOSFETs Q9 to Q11 that form the second bias circuit, for example. Sense amplifier
The SA differential amplifier circuit need not be based on an active load using a current mirror circuit, and its specific configuration is not limited by this embodiment. The configuration of the memory mat and each selection circuit of FIG. 2 may be, for example, three or more series circuits of the storage MOSFET Qm connected to one data line, and the selection method is also limited by this embodiment. Not something. Further, various embodiments such as a circuit block configuration of the vertical ROM of FIG. 2 and a combination of control signals and timing signals can be adopted.

In the above description, the case where the present invention made by the present inventor is mainly applied to the vertical ROM which is the field of application which is the background has been described, but the present invention is not limited thereto, and for example, to an EPROM or an EEPROM. Can also be applied. The present invention can be widely applied to various semiconductor memory devices including at least non-volatile memory cells.

〔The invention's effect〕

The following is a brief description of an effect obtained by the representative one of the inventions disclosed in the present application. That is, the vertical ROM sense amplifier circuit includes two sets of bias circuits each including a depletion type MOSFET serving as a constant current source and supplying a read current or a reference current to a common data line or a dummy data line, respectively. Of the differential amplifier circuit that receives the output signal of the bias circuit of, and is connected to the dummy data line.
Selection MOSF that configures column selection circuit for SFET and memory MOSFET
By forming them in close proximity to the ET and the information storage MOSFET, limit the level amplitude of the common data line so that the read signal and the reference potential formed by the dummy data line exhibit similar process variations. Therefore, it is possible to realize a high-sensitivity vertical ROM that speeds up and stabilizes the read operation.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing an embodiment of a sense amplifier circuit of a vertical ROM to which the present invention is applied, and FIG. 2 shows an embodiment of a vertical ROM including the sense amplifier circuit of FIG. FIG. 3 is a circuit block diagram showing an example of a conventional vertical ROM sense amplifier circuit. SA: Sense amplifier circuit, DOB: Data output buffer, YG: Y gate circuit, PGU, PGL: Pregate circuit, MMU, MML: Memory mat, YDCR: Y address decoder, PDCR: Predecoder, XDCR: X address decoder, TG: Timing generation circuit. Qm ... memory MOSFET (memory cell), Q1-Q2 ... P-channel MOSFET, Q3-Q44 ... N-channel MOSFET (of which depletion type N-channel MOSFET is the one with a straight line added to the channel), N1-N3 ...... Inverter circuit, AG1 to AG4 …… And gate circuit, Cs, Cd …… Parasitic capacitance, R1 …… Resistance.

Claims (1)

[Claims] 1. A memory array comprising a plurality of series circuits in which a plurality of storage MOSFETs selectively made enhancement type or depletion type according to the storage data of each bit are connected in series for each column address, A vertical read-only memory including a column selection circuit that selectively connects the series circuit to a common data line according to an address signal supplied from the outside, and a plurality of series circuits forming the memory array and / or A dummy circuit including a similar series circuit and / or switch MOSFETs formed in proximity to a plurality of switch MOSFETs forming the column selection circuit is provided, and the common data line and the first power supply voltage are provided in the sense amplifier circuit. And an enhancement-type first MOSFET provided between the base of the first MOSFET and the second power supply voltage. A depletion-type enhancement type second MOSFET having a base coupled to the common data line and a base provided between the base of the first MOSFET and the first power supply voltage, and the base of which is commonly connected to its source. A first bias circuit configured to include a third MOSFET and supplying a read current to the common data line, and a second bias circuit configured to have a circuit configuration similar to that of the first bias circuit and which supplies a reference current to a dummy circuit. Circuit,
A semiconductor memory device comprising: a differential amplifier circuit that receives output signals of the first and second bias circuits.