JP3202042B2 - Semiconductor storage device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device, and more particularly to a technique which is effective when applied to a semiconductor memory device of a system in which reading of a memory element is sensed by referring to a reference voltage formed by a dummy memory element. Things.

[0002]

2. Description of the Related Art A ROM is known in which storage MOSFETs of a depletion type or an enhancement type are connected in series (vertical) according to stored information. Such a vertical ROM is disclosed, for example, in JP-A-59-116.
No. 993.

[0003]

In the above-mentioned ROM, a dummy storage MO is used for reading the storage MOSFET.
An SFET is used. Such a dummy storage MOS
When an FET is used, if a dummy storage MOSFET or a dummy data line to which the dummy storage MOSFET is connected has a DC failure, it is discarded as all defective products. Therefore, the inventors of the present application considered providing a plurality of dummy data lines and performing defect repair of the dummy data lines. An object of the present invention is to provide a semiconductor memory device which improves the production yield. It is another object of the present invention to provide a semiconductor memory device in which a dummy data line has a redundant function and enables an efficient test thereof. The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.

[0004]

The following is a brief description of an outline of a typical invention among the inventions disclosed in the present application. That is, for reading from a memory array in which storage elements are arranged in a matrix, a plurality of dummy data lines to which dummy storage elements for forming a reference voltage are connected are prepared, and a defect is selected from among the plurality of dummy data lines by a selector. One non-existent dummy data line is selected and supplied to a differential sense amplifier to sense stored information.

[0005]

According to the above-mentioned means, when a defect is found in a dummy data line, it can be repaired by switching to a spare data line by a selector.

[0006]

1 shows a vertical ROM to which the present invention is applied.
1 is a main part circuit diagram of one embodiment. Each circuit element in FIG. 1 is formed on a single semiconductor substrate such as single crystal silicon, although not particularly limited by a known semiconductor integrated circuit manufacturing technique. Although not particularly limited, the vertical ROM of this embodiment is configured by an N-channel MOSFET. Therefore, the integrated circuit is formed on a semiconductor substrate made of single-crystal P-type silicon. The N-channel MOSFET is made of polysilicon formed on the surface of the semiconductor substrate between the source region and the drain region, and between the source region and the drain region, with a thin gate insulating film interposed therebetween. Composed of simple gate electrodes.

The memory array includes memory blocks MB0 and MB1 as exemplarily shown by broken lines in FIG. Each of the memory blocks MB0 and MB1 includes a plurality of storage MOSFETs Qm connected in series. Each of the storage MOSFETs Qm is formed as a depression type or an enhancement type according to stored information. Although not particularly limited, the storage MOSFET Qm
Are initially formed in a depletion type and are selectively enhanced according to stored information. That is, after forming a wiring such as aluminum on the surface of the channel region of the depletion type MOSFET,
By introducing an impurity of a conductivity type opposite to that of the substrate gate, writing is performed to form an enhancement type storage MOSFET having a positive threshold voltage. In this case, in almost the final step of the semiconductor integrated circuit, writing can be performed by the ion implantation method. As a result, the manufacturing process of the semiconductor integrated circuit can be shared, and the manufacturing efficiency can be improved.

In this embodiment, one series storage MOSFET is provided for each data line D0 in each of the memory blocks MB0 and MB1.
Memory block MB0 provided for one data line D0
Is connected to the data line D0 via a switch MOSFET Q1 which receives a selection signal formed by a decoder circuit DCR0 described later. Another data line D1 of the memory block MB0
Similarly, switch MOSFETs Q2 and Q3 are provided in series MOSFETs corresponding to Dn.
Each series circuit of the memory block MB1 is also connected to the data lines D0 to Dn via switch MOSFETs Q4 to Q6 receiving a selection signal formed by the corresponding decoder circuit DCR1.

The gates of the storage MOSFETs Qm corresponding to the lateral direction among the storage MOSFETs of the memory blocks MB0 and MB1 connected in series are commonly connected to word lines W0 to Wm, respectively. The word lines W0 to Wm of these memory blocks MB0 and M1 are connected to switch MOSFETs Q7 to Q9 and Q13, respectively.
Through Q15 to a common predecoder XPDCR
, Respectively.

The selection signal formed by the decoder circuit DCR0 is supplied to the gates of the switch MOSFETs Q7 to Q9 corresponding to one memory block MB0. Memory block MB1 shown as another example
The selection signal formed by the decoder circuit DCR1 is supplied to the gates of the switch MOSFETs Q13 to Q15 corresponding to. In this configuration, the common predecoder circuit XPDCR forms a common selection signal for a plurality of memory blocks such as the memory blocks MB0 and M1, so that the circuit can be simplified. it can. In addition, the serial storage M
Since the word lines can be arranged in accordance with the pitch between the gates of the OSFET Qm, the memory blocks and the word line selection signal lines can be arranged at a high density.

The data lines D0 to Dn are connected to a common data line CD via switch MOSFETs Q19 to Q21 which receive a selection signal formed by a column decoder YDCR. Although not particularly limited, there are 512 data lines D0 to Dn and word lines W0 to Wm.
Is 512, one memory block MB0 has a storage capacity of about 256K bits. Therefore, when configuring a vertical ROM having a storage capacity of about 4 Mbits, a total of 16 memory blocks similar to the above are provided.

The common data line CD is connected to a sense amplifier S
Connected to A input terminal. The sense amplifier SA performs its sensing operation with reference to a reference voltage Vref formed by a dummy array DC composed of a storage circuit similar to a storage MOSFET in a serial form in the memory block. That is, the dummy array DC is the dummy storage M
All of the OSFETs Qm are constituted by enhancement MOSFETs, and the gates thereof are constantly turned on when the power supply voltage Vcc is constantly supplied to their gates. Then, the combined conductance is set to about の of the combined conductance of the storage MOSFETs in the memory block in the serial form. Vertical RO of this embodiment
M is configured as a static circuit. That is,
The sense amplifier SA has a read current source, and senses whether or not a current flows through the common data line CD and the data line and the selected serial storage MOSFET Qm with reference to the current flowing in the dummy array DC. Thereby, the read operation is performed. In this embodiment, although there is no particular limitation for the defect relief in the dummy array DC, two sets of the dummy storage MOSFETs (×
2) It is prepared, and if a defect occurs in one, the other is used instead. The selector SEL selects one of the two sets of dummy storage MOSFETs according to the selection signal S, and transmits the selected signal to the differential sense amplifier SA as the reference voltage Vr.

In this embodiment, although not particularly limited, in the memory block MB0, in order to prevent the potential of the word lines W0 to Wm from being lowered due to the non-selected state, each word line W0 is prevented. Or MOSF for pull-up between Wm and power supply voltage Vcc.
ETQ10 to Q12 are provided. These MOS
In order to turn on the FETs Q10 to Q12 when the memory block MB0 is in the non-selected state, in other words, to perform the pull-up operation when the memory block MB0 is in the non-selected state, the decoder circuit DC
An inverter circuit N1 receiving an output signal of R0 is provided. The output signal of this inverter circuit N1 is
It is transmitted to the gates of ETQ10 to Q12.

Similarly, in the other memory block MB1, each word line W0 to Wm is connected to the power supply voltage in order to prevent the potential of the word line W0 to Wm from being lowered due to the non-selected state. The pull-up MOSFETs Q13 to Q15 are provided between Vcc and Vcc. These MOSFETs Q13 to Q15
Is controlled by the output signal of the inverter circuit N2 receiving the output signal of the decoder circuit DCR1, so that the word lines W0 to Wm are pulled up when the memory block MB1 is in a non-selected state.

The address selection operation of the vertical ROM of this embodiment will be described below. The predecoder XPDCR decodes a row (X) -based address signal (not shown) to set a selected level to a low level and a non-selected level to a high level. That is, as described above, the word lines W0 to Wm
In the case of 12 word lines, one word line selected for the 512 word lines is set to low level, and the other
Set the word lines to high level. Decoder circuit DCR
0 and the like form a selection signal for the corresponding memory block MB0 and the like. Therefore, for example, the decoder circuit DCR0
When the output signal is set to a high selection level, a word line selection signal formed by the predecoder circuit XPDCR is transmitted to each of the word lines W0 to Wm of the memory block MB0 via the switch MOSFETs Q7 to Q9. Therefore, if the storage MOSFET Qm coupled to the selected word line in the memory block MB0 is of the depletion type, a current path is formed in the series circuit, and if it is of the enhancement type, no current path is formed. At this time, depending on the selection level of the decoder circuit DCR0,
The output signal of the inverter circuit N1 becomes low level, and the pull-up MOSFETs Q10 to Q12 are turned off.

Each series circuit of the memory block MB0 is coupled to data lines D0 to Dn via switch MOSFETs Q1 to Q3 which are turned on by the selection level of the decoder circuit DCR0. Column decoder Y
For example, in the case where the data lines D0 to Dn include the above-mentioned 512 data lines, one of the 512 data lines is selected and coupled to the common data line CD. As a result, the storage information of one storage MOSFET is read.

When the selected storage MOSFET Qm is the above-mentioned enhancement type MOSFET, the word line is substantially read from a high level (non-selection level) such as the power supply voltage Vcc to a low level such as the ground potential of the circuit. And starts when the level reaches the threshold voltage Vth or less. At this time, it is necessary that the level of the other word lines is a non-selected level. In this embodiment, in the memory block MB1 which is not selected at this time, the corresponding decoder circuit DCR1
Is at the low level of the non-selection level, the output signal of the inverter circuit N2 goes to the high level, and the pull-up MOSFETs Q16 to Q18 are turned on. As a result, in the non-selected memory block MB1 and the like, all the word lines W0 to wm are set to the high-level non-selected level.

Therefore, even when the memory block MB0 is in the non-selected state, since all the word lines W0 to Wm have been previously set to the high-level non-selected level as described above, the predecoder circuit XPDCR Is
In effect, the operation of pulling out the level of one selected word line from the high level to the low level is performed. As described above, the switch MOSFET (1 of Q7 to Q9)
When a signal voltage is applied through two MOSFETs, a drive voltage (transfer voltage) such as a power supply voltage Vcc is applied between the gate and the source of the signal.
ET can be turned on under a large conductance characteristic. As a result, the fall of the word line to the selected level, in other words, the extraction of the accumulated charge stored in the parasitic capacitance of the word line to be selected can be performed at high speed. As a result, the actual read start timing of the selected storage MOSFET Qm can be advanced.

As described above, when the memory block is set in the non-selected state, the pull-up MOSFET is turned on, and all the word lines W0 to Wm are set to the high-level non-selected level, whereby the selected state is set. In this case, the substantial read operation of the storage MOSFET Qm can be accelerated. When a memory access occurs,
In other words, when the read operation is performed, 5
Since one of the twelve word lines is pulled out from the high level to the low level, the peak current flowing through the ground potential line of the circuit becomes very small. Therefore, noise generated on the ground potential line of the circuit can be minimized.
This makes it possible to increase the operation margin of the sense amplifier SA that senses whether or not a current flows in the series circuit.

In the above-described vertical ROM, when a DC failure occurs in one of the dummy storage elements, a dummy storage element for redundancy is used instead of the dummy storage element determined to be defective by the switching signal S. As a result, the defect can be relieved in the dummy array DC, and the product yield can be increased.

FIG. 2 is a main part circuit diagram of another embodiment of the semiconductor memory device according to the present invention. Although this embodiment is not particularly limited, a horizontal ROM or an EPROM
(Erasable & Programmable Read Only
Memory). In the figure, for the sake of simplicity, the circuit symbols given to each circuit element partially overlap those in FIG. 1, but it should be understood that each has a separate circuit function. . This is the same in the following drawings.

FIG. 2 shows two word lines W as representatives.
0, W1 and three data lines D0, D1 to Dn are exemplarily shown, and storage elements M are arranged in a matrix at respective intersections. The signals of the data lines D0 to Dn selected by the column switch CW are transmitted to the sense amplifier SA. In the case of a horizontal ROM, the storage element M changes the threshold voltage of the storage MOSFET by a selective ion implantation technique into the channel region below the gate electrode as described later, or changes the gate insulating film. Alternatively, storage information is written by selectively connecting a gate or a drain to a word line or a data line. In the case of an EPROM, a stacked gate structure or the like is used in which a floating gate is provided below a control gate coupled to a word line, and hot carriers are injected into the floating gate to perform writing.

In order to sense the signal of the storage element selected as described above, two dummy data lines DD0 and DD1 are provided, although not particularly limited. The above word line W
0, W1, etc., correspond to these dummy data lines DD0, DD1.
Are also extended so as to intersect with the dummy storage element D
Is provided. The dummy data lines DD0 and DD1 are
It is coupled to the input terminal on the reference potential side of the sense amplifier SA via the switch MOSFETs Q1 and Q2 forming the selector.

In this embodiment, a resistor RD having a resistance value equivalent to that of the dummy storage element is prepared in order to detect pass / fail of the two dummy data lines.
It is selectively connected to the input terminal on the reference potential side of the sense amplifier SA via the ETQ3. The selection control circuit SLC is not particularly limited, but ultimately forms a control signal for selecting one of the dummy data lines DD0 or DD1 by using a program element such as a fuse unit as described later.

Although there is no particular limitation, verification of good / bad of the dummy data line is performed as follows. For example, a signal a is generated by the selection control circuit SEL to turn on the switch MOSFET Q1, and the dummy data line DD
Using 0, the reading of the storage element M of the memory array is performed. At this time, if a failure occurs in the read signal, the selection control circuit SLC generates c in place of the signal a and switches the switch MOSFET in place of the switch MOSFET Q1.
Turn ETQ3 on. From this, the read operation is performed again, and if the read signal does not match the expected value, it is determined that the memory array is defective. At this time, if a redundant circuit is provided on the memory array side, the data line or word line is switched to a spare word line or data line. On the other hand, the switch MOSFET Q1
If the read failure is eliminated by switching from to Q3, it is determined that the dummy data line DD0 is defective,
This is to switch to the spare dummy data line DD1. That is, the selection control circuit SLC generates the signal b to turn on the switch MOSFET Q2 to connect the dummy data line DD1 to the input terminal on the reference potential side of the sense amplifier SA.

Resistance element DR equivalent to the above dummy storage element
May be omitted. That is, the switch MOSFET Q
If a failure occurs while the storage element is being read while the storage element 1 is turned on, the MOSFET Q2 is turned on instead of the switch MOSFET Q1, and if the failure is not resolved by performing the same storage element read operation, It is determined that the defect is on the memory cell side, and if the defect is eliminated, it can be determined that the dummy data line DD0 is defective. In this case, when there is a defect in the dummy data lines DD0 and DD1, it is erroneously determined to be a defect on the memory array side. However, in this case, the defect is not relieved even if switching to the spare data line is performed. In the end, there is no problem because it is discarded as defective. However, there still remains a problem that it takes a long time to finally determine that the device is defective. In this regard, if a resistor DR equivalent to the above-described dummy storage element is provided, a defect on the dummy data line side can be determined in a short time.

FIG. 3 is a specific circuit diagram of an embodiment including a specific circuit of the selection control circuit. If the selection control circuit switches the switches by means of a fuse, there is a problem that once the connection is cut, it cannot be restored. In addition, when cutting is performed using a laser beam for simplification of the fuse circuit, the read test must be temporarily interrupted, and the read test must be performed again after the fuse cutting process. Becomes complicated.

In this embodiment, the selector can be temporarily switched in the probing process so that an efficient read test can be performed. In FIG.
Dummy data lines DD0 and DD1, and a MOSFET Q3 equivalent to a dummy storage element are provided. This MOSF
ETQ3 is the switch MOSFET Q in FIG.
3 and the function of the resistor DR. That is, when the MOSFET Q3 is turned on, the resistance R
It has an on-resistance value equivalent to D. This MOS
The output signal of the inverter circuit N1 receiving the selection signal RS is supplied to the gate of the FET Q3.

The output signals of AND gate circuits G2 and G3 are supplied to the gates of switch MOSFETs Q1 and Q2 for selecting the dummy data lines DD0 and DD1, respectively. A selection signal RS is supplied to one input of these AND gate circuits G1 and G2. As a result, when the selection signal RS is set to low level (logic 0), the output signals of the AND gate circuits G2 and G3 become low level, turning off the switch MOSFETs Q2 and Q3 and turning on the switch MOSFET Q3. The reference voltage formed thereby is transmitted to the reference potential side of the sense amplifier SA. That is, if a read failure of the storage element occurs, by setting the selection signal RS to low level, a MOSFET Q3 equivalent to the dummy data line DD0 or DD1 is selected instead of the dummy data line DD0 or DD1, and the dummy data line side or the memory It can be determined whether the array is defective.

The selection of the dummy data lines DD0 and DD1 is determined by the following circuit. Fuse means F
Channel MOSFET Q4 and N-channel MOS
It is connected in series with the FET Q5. These MOSFET Q
The chip selection signal CE is supplied to the gates of 4 and Q5. Although not particularly limited, the MOSFETs Q4 and Q5 are provided with a capacitor for holding a voltage. This capacitor may use the input capacitance or the wiring capacitance of the inverter circuit N2. The potential at the connection point between the fuse means F and the capacitor is amplified and output by the inverter circuit N2. This amplified output signal is generated by a MOSFET provided between its input and the ground potential point of the circuit.
By being fed back to the gate of Q6, a latch operation is performed for the low level of the input signal.

In a state where the fuse means F is not cut,
The output signal is maintained at a high level. Therefore, a low-level output signal is formed through the inverter circuit N2. When the low-level output signal is thus formed, the feedback MOSFET Q6 is maintained in the off state. On the other hand, if the fuse means F is cut, the chip select signal CE changes synchronously when the memory is set to the selected state. During the level change of the signal CE, the P-channel MOSFET Q4
And the N-channel MOSFET Q5 are simultaneously turned on, so that a through current flows to the ground potential of the circuit. As a result, even if the capacitor holds the electric charge, the capacitor is pulled out to the low level by the through current, so that the inverter circuit N2 forms a high-level output signal. In response to this high level output signal, MOSFET Q
6 is turned on, and the input level of the inverter circuit N2 is fixed at a low level such as the ground potential of the circuit. The control signal formed according to whether the fuse means F is cut or not is supplied to one input of the NOR gate circuit G1.

In this embodiment, the following circuit is provided to enable temporary switching from the dummy data line DD0 to DD1 without cutting the fuse means F. Pad PA to which control voltage is applied from a probe
For P, a P-channel MOSFET as described above
A series circuit comprising Q7 and an N-channel MOSFET Q8 is provided, and a chip select signal CE is supplied to the gates of these MOSFETs Q7 and Q8. A capacitor similar to the above is provided between the pad PAD and the ground potential of the circuit.
An inverter circuit N3 receiving the voltage of pad PAD is provided, and feedback MOSFE controlled by an output signal thereof is provided.
TQ9 is provided between the input terminal and the ground potential point of the circuit.
The output signal of this latch circuit is output through an inverter circuit N4 and supplied to the other input of the NOR gate circuit G1. On the other hand, the output of the NOR gate circuit G1 is directly connected to the switch MOS corresponding to the dummy data line DD0.
The FET Q1 is supplied to an AND gate circuit G2 for selecting the FET Q1,
On the other hand, a switch MOSFET Q2 inverted by an inverter circuit N5 and corresponding to a dummy data line DD1.
Is supplied to an AND gate circuit G3 for selecting

Verification of good / bad of the dummy data line is performed as follows. For example, when the signal RS is at a high level, the output signal of the inverter circuit N2 is at a low level because the fuse means F is not blown. Further, when a low-level signal is supplied from the probe to the pad PAD, the output signal of the inverter circuit N4 also goes low. As a result, the output signal of the NOR gate circuit G1 goes high, the output signal of the AND gate circuit G2 goes high, and the switch MOSFET Q
With 1 turned on, a read test of the memory array using the dummy data line DD0 is performed. In this state, if a defect occurs in the read signal, the signal RS is set to a low level. Then, as described above, the switch MOSFET
Q1 is turned off, MOSFET Q3 is turned on instead, and the read operation is performed again by the reference signal formed by the on-resistance value of the MOSFET Q3. If the read signal does not match the expected value, it means that there is a defect on the memory array side. judge. Then, the signal RS is returned to the high level, and a high-level signal is supplied from the pad PAD. Then, the output signal of the inverter circuit N4 goes high, and the output signal of the NOR gate circuit G1 goes low. As a result, the output signal of the AND gate circuit G3 becomes high level in place of the AND gate circuit G2, and the switch MOSFET Q2 is turned on. That is, the read operation is performed using the spare dummy data line DD1 in place of the dummy data line DD0 determined to be defective.

When the read operation of the memory array is completed using the spare dummy data line DD1, the defective data line on the memory array side is switched to the spare data line based on the result, and the fuse process is performed in the same process. The means F is cut off and fixedly switched to the dummy data line DD1. This can save the trouble of switching to the spare dummy data line during the test and performing the read test again. If a defect occurs in the spare dummy data line DD1, it is determined that the storage device cannot be repaired at that time.

In a normal operation state, the pad is placed in a floating state. However, even if an intermediate potential is generated in the pad PAD or the capacitor, the signal is pulled down to a low level due to a through current caused by the MOSFETs Q7 and Q8 when the signal CE changes every memory access, and when the signal CE becomes lower than the logic threshold potential of the inverter circuit N3, the output signal becomes lower. It goes high, turning on the MOSFET Q9 that fixes the input potential to the ground potential. Thereafter, when power is supplied, a low-level output signal is formed. At this time, the output signal of the AND gate circuit G2 or G3 goes high depending on whether the fuse means F is cut or not, and the dummy data line DD0 or DD1 is selected.

FIG. 4 shows a horizontal RO to which the present invention is applied.
A circuit diagram of an embodiment of the main part of M is shown. The ROM of this embodiment is not particularly limited, but is formed on a single semiconductor substrate such as single crystal silicon by a known CMOS circuit manufacturing technique. Although not particularly limited,
The integrated circuit is formed on a semiconductor substrate made of single-crystal P-type silicon. An N-channel MOSFET is formed on a semiconductor substrate (channel region) between a source region and a drain region and between the source region and the drain region through a thin gate insulating film with a thin gate insulating film. It is composed of a gate electrode made of silicon. The P-channel MOSFET is formed in an N-type well region formed on the surface of the semiconductor substrate. Thereby, the semiconductor substrate forms a common substrate gate of the plurality of N-channel MOSFETs formed thereon.
The N-type well region has a P-channel M formed thereon.
Construct the substrate gate of the OSFET.

The memory array M-ARY includes a plurality of word lines W0 to Wn arranged in the horizontal direction shown as an example.
At the intersection of a plurality of data lines (bit lines or digit lines) D00 to D01 arranged in the vertical direction.
OSFET Qm is formed. In this embodiment, a common source line CS0 extending in parallel with a pair of data lines D00 and D10 is provided between the pair of data lines D00 and D10 in order to increase the density of storage elements and reduce power consumption during a read operation. . The source of the storage MOSFET Qm whose drain is connected to the pair of data lines D00 and D10 corresponding to the common source line CS0 is connected in common. The data line D10 is connected to an adjacent common source line CS1 by a storage MOSFET whose source is connected to the common source line CS1.
Are connected in common. The above common source line CS
The drains of the other storage MOSFETs corresponding to 1 are:
Connected to data line D01. The drain of the storage MOSFET whose source is coupled to the common source line CS2 provided adjacent to the data line D10 is commonly coupled. As described above, the data lines and the common source lines are alternately arranged, and are commonly connected to the drains of the storage MOSFETs to which different Y addresses are assigned, except for the end data line D00.

Data line D00 is coupled to common data line CD0 via MOSFET Q11 forming a Y gate (column switch). The corresponding common source line CS0 is coupled to the ground potential point of the circuit via switch MOSFET Q12. Further, the common source line C
The other data line D10 corresponding to S0 is connected to the common data line CD1 via the MOSFET Q13 forming the Y gate.
Is combined with These switch MOSFETs Q11 to Q11
The gate of Q12 has a Y decoder circuit YDCR to be described later.
Are commonly supplied.

The data line D10 is a MOS gate constituting a Y gate to which another Y address (Y2) is assigned.
Coupled to common data line CD1 via FET Q14. A common source line CS1 disposed on the right of the data line D10 is coupled to a ground potential point of the circuit via a switch MOSFET Q15. This common source line CS1
Is connected to the common data line CD0 via the MOSFET Q16 forming the Y gate.
Is combined with A selection signal Y1 formed by the Y decoder circuit YDCR is supplied to the gates of these MOSFETs Q14 to Q16. Hereinafter, data lines, common data lines, and switch MOSFETs are formed by repeating similar patterns.

The gates of the storage MOSFETs arranged on the same row are respectively coupled to corresponding word lines W0 to Wn. The word lines W0 to Wn are supplied with a selection signal formed by an X decoder circuit XDCR to be described later. In this embodiment, the data lines D00 to D01 and the common source lines CS0 to CS2,
Although not particularly limited, depletion type MOSFETs Q1 to Q7 are provided between the power supply voltage Vcc. The depletion-mode MOSFETs Q1, Q3, Q5, Q7, etc., corresponding to the data lines D00 to D01, supply a bias voltage and act as load means thereof, and depletion-mode MOSFETs Q2, corresponding to the common source lines CS0 to CS2, Q4, Q6
Etc. operate as a MOSFET that supplies a bias voltage that sets the common source line to a non-selection level.

The gates of the storage MOSFETs arranged on the same row are respectively coupled to corresponding word lines W0 to Wn. The word lines W0 to Wn are supplied with a selection signal formed by an X decoder circuit XDCR to be described later. In this embodiment, the data lines D00 to D01 and the common source lines CS0 to CS2,
Although not particularly limited, depletion type MOSFETs Q1 to Q7 are provided between the power supply voltage Vcc. The depletion-mode MOSFETs Q1, Q3, Q5, Q7, etc., corresponding to the data lines D00 to D01, supply a bias voltage and act as load means thereof, and depletion-mode MOSFETs Q2, corresponding to the common source lines CS0 to CS2, Q4, Q6
Etc. operate as a MOSFET that supplies a bias voltage that sets the common source line to a non-selection level.

For example, by the Y decoder circuit YDCR,
When the selection signal Y1 is generated, the switch MOSFET
By turning on Q14 to Q16,
The data lines D10 and D01 and the common source line CS1 are selected. In this case, the storage memories M arranged between the data lines D10 and D01 and the common source line CS1 respectively.
Only the OSFET has to be selected. However, if the potentials of the common source lines CS0 and CS2 are set to a low level such as the ground potential of the circuit, they are arranged between the data line D10 and the common source line CS0 and between the data line D01 and the common source line CS2. Storage MOSFET
Also appears on the data lines D10 and D01. Therefore, by providing the depletion type MOSFETs Q2, Q4, Q6 and the like also on the common source line as described above, only the selected common source line CS0 is supplied with the circuit ground potential by the switch MOSFET Q15, and the unselected common source line CS0 is provided. By making the potentials of the source lines CS0 and CS2 equal to the bias potential of the data lines, the data lines D10 and D01 and the common source lines CS0 and C
This is to turn off the storage MOSFET irrespective of information stored in the storage MOSFET disposed between the storage MOSFET and S2.

The addressing of the memory array M-ARY having the above configuration is performed by the following circuit blocks. An X address signal AX composed of a plurality of bits supplied from an external terminal is supplied to an X address buffer XADB, and a complementary address composed of an internal address signal having the same phase as the address signal supplied from the external terminal and an internal address signal having a phase opposite thereto. Form a signal. These complementary address signals are decoded by X decoder XDCR, and this X decoder XDCR
R forms a selection signal for one word line. In this embodiment, the X address buffer XADB and the X decoder XDCR are collectively represented as XADB · DCR. Y consisting of multiple bits supplied from an external terminal
The address signal AY is supplied to the Y address buffer YADB, and forms a complementary address signal composed of an internal address signal having the same phase as the address signal supplied from the external terminal and an internal address signal having the opposite phase. These complementary address signals are decoded by a Y decoder YDCR, and a selection signal for two data lines is formed by the Y decoder YDCR. In this embodiment, the Y address buffer YAD
B and Y decoder YDCR are collectively represented as YADB · DCR.

In the read operation, both of the common source lines arranged adjacent to the non-selected data lines have the output signals of the Y decoder YDCR at a low level, so that both switch MOSFETs are turned off. You.
Therefore, a large number of storage MOSFETs are connected to one word line.
Are connected, only the current according to the stored information flows through the storage MOSFET whose data line is selected, so that power consumption can be reduced.
In addition, by the selection operation according to the Y address of the common source line, the storage MOSFETs with different Y addresses assigned to the data lines can be coupled.
Can be arranged at high density.

In this embodiment, the following dummy cell is provided in order to accurately identify a read signal from the storage MOSFET having only a small threshold voltage. Although not particularly limited, for example, two dummy MOSs whose gates are respectively coupled to the word lines W0 to Wn
FETs Qd and Qd 'are provided in a parallel configuration. These MOSFETs Qd and Qd 'are arranged in parallel with each other by being arranged between a pair of common source lines CS arranged with the dummy data line DD interposed therebetween. The one dummy MOSFET Qd is formed similarly to the storage MOSFET having the relatively low threshold voltage. The other dummy MOSFET Qd 'is formed similarly to the storage MOSFET having the relatively high threshold voltage. Dummy M having this high threshold voltage
The OSFET Qd ′ is a storage MOSFET to be turned off with respect to a word line selection level (about 2 V).
Is provided for compensating for a high-level drop caused by a leak current generated in the circuit.

Referring to FIG.
Although one dummy data line DD provided with d and Qd ′ is exemplarily shown as a representative, at least one similar dummy data line is provided as a spare. Those dummy data lines selected by the same selector SEL through the switch MOSFET Q20 forming a dummy column switch are connected to the input terminal of a preamplifier (current mirror type sense amplifier) DPA described later. The signal of the selected dummy data line is current-amplified by the preamplifier DPA and supplied to the reference input terminals (-) of the differential amplifiers A0 and A1. Common source line CS is coupled to the ground potential point of the circuit via switch MOSFETs Q19 and Q21. The above switch MOSFET Q19
The selection signal YD formed by the Y decoder circuit YDCR is supplied to the gates of Q21 to Q21.

The sense amplifiers of this embodiment are composed of current amplifier circuits (preamplifiers) PA0 and PA formed of current mirror circuits.
1 and differential amplifiers A0 and A1 for receiving the output signal. In the figure, a specific circuit of the preamplifier PA0 is exemplarily shown as a representative, and is constituted by the following circuit elements. The common data line CD0 is a depletion type MOSFET whose gate is coupled to the ground potential of the circuit.
P-channel MOSF in diode form via Q23
It is coupled to the drain of ETQ22. As a result, the MOSFETs Q22 and Q23 are connected to the selected data line.
A read current is supplied via the common data line CD0 and the switch MOSFET forming the Y gate.
In this case, a bias voltage corresponding to the threshold voltage is applied to the selected data line by the threshold voltage of the depletion type MOSFET Q1 or the like. A bias voltage corresponding to the threshold voltage of the depletion type MOSFET Q23 is also applied to the common data line CD0 (CD1). The memory array M-AR
Depletion type MOSFETs Q1 to Q7 provided on the Y data line and the common source line, and a depletion type MOSFET Q2 forming the preamplifier PA0.
By forming 3 under the same manufacturing conditions, both potentials of the data line and the common data line (input terminal of the preamplifier PA0) can be set equal.

Thus, in the read operation of the storage MOSFET Qm, the current flowing through the MOSFETs Q23 and Q22 forming the preamplifier PA0 becomes the current flowing in the storage MOSFET Qm selected according to the word line and data line selection operation. Thus, a high-speed read operation can be realized. That is, although the data line has a parasitic capacitance having a relatively large capacitance value due to the coupling of a large number of storage MOSFETs, the differential amplifier A
0 is stored in the storage MOSFET Qm.
, The parasitic capacitance can be substantially neglected.

The MOSFET Q22 is provided with a current mirror type P-channel MOSFET Q24. This MOSFET Q24 is
By setting the size to be larger than that of the above, a read amplification current is formed in accordance with the size ratio. The amplified current obtained from the drain of the MOSFET Q24 is supplied to the input terminal (+) of the differential amplifier S0. N-channel MOS connected in the form of a diode between the drain of MOSFET Q24 and the ground potential of the circuit
FET Q29 is connected. Thereby, the preamplifier P
The static operation of A0 becomes possible. The load means of the static circuit may use a resistance element or a plurality of MOSFETs in other connection forms in addition to the MOSFET Q29.

In this embodiment, the selected information storage M
When the OSFET Qm is off, the MOSFET Q
22 rise of the drain voltage, in other words,
In order to switch the MOSFET Q22 to the off state at high speed, the following circuit elements are added. The resistance R forms a constant current 2i by setting the resistance value larger than the power supply voltage Vcc. This current 2i is shunted by MOSFETs Q27 and Q28 whose gates are coupled to the ground potential of the circuit as described above, although not particularly limited.
By setting the element sizes of the MOSFETs Q27 and Q28 equal, half the current i
The current flows through the FETs Q27 and Q28. MO above
The current i flowing through the SFET Q27 is made to flow through the diode-shaped P-channel MOSFET Q25. By setting the resistance value of the resistor R relatively large as described above, the MOSFET Q25
It is operated near the threshold voltage. This MOSF
A P-channel MOSFET Q26 having the same element size in the form of a current mirror is provided for the ETQ 25. As described above, the MOSFET Q26
Since the FET Q25 is operated near the threshold voltage, it is operated in the saturation region. This MOSFET Q
The drain of 26 is connected to the common gate and drain (node N1) of the MOSFET Q22. The drain of MOSFET Q28 is also coupled to node N1.

Thus, the current i flowing through the MOSFET Q27 is equal to the current mirror type MOSFET
It is supplied to the drain of MOSFET Q28 via Q25 and Q26. Even if such a current path is provided, the current i does not flow between the source and the drain of the MOSFET Q22. Therefore, since the component of the current i does not appear in the current mirror circuit (MOSFETs Q22 and Q24) for read current amplification, an accurate read current amplification operation is performed. The input terminal (+) of the differential amplifier S0 to which the amplified current is supplied is provided with a resistance element for current / voltage conversion (not shown). The inverting input terminal (-) of the differential amplifier A0 has a preamplifier DPA similar to the above.
, A reference signal obtained from the dummy data line DD selected by the selector SEL is supplied. Further, a sense amplifier including a preamplifier PA1 and a differential amplifier circuit A1 is provided for the other common data line CD1.

The storage MOSFET Qm in the memory array M-ARY is not particularly limited, but is written by an ion implantation method. The writing process by such an ion implantation technique is a nearly final process of a semiconductor integrated circuit formed on a semiconductor wafer, for example, an ion implantation process through a gate electrode of a MOSFET which is a memory cell after forming a data line made of aluminum. It is implemented by. By doing so, the previous process can be shared irrespective of the write information, so that the manufacturing process can be rationalized. Even in such a horizontal ROM, a voltage correction circuit TMC similar to the above is provided in order to correct the input level of the sense amplifier SA due to process variation. As a result, a high-speed and stable read operation in which process variations are corrected can be realized.

The operation and effect obtained from the above embodiment are as follows. That is, (1) reading from a memory array in which storage elements are arranged in a matrix is performed by preparing a plurality of dummy data lines to which dummy storage elements forming a reference voltage are coupled, and selecting a plurality of dummy data lines by a selector. In this case, one dummy data line having no defect is selected and supplied to the differential sense amplifier to sense storage information. By switching to the spare data line, the repair can be performed, so that the effect of increasing the product yield can be obtained. (2) By providing a resistance circuit equivalent to the dummy storage element provided on the dummy data line and forming a reference potential of the sense amplifier by this, it is possible to easily determine whether the dummy data line is good or defective. The effect is obtained. (3) By the control signal supplied at the time of probing,
By temporarily switching the dummy data line, the dummy data line having a defect after the read test is completed can be switched at the same time as the defective data line is switched to the spare data line. This makes it possible to perform an effective test and defect remedy.

Although the invention made by the inventor has been specifically described based on the embodiment, the invention of the present application is not limited to the embodiment, and various modifications can be made without departing from the gist of the invention. Needless to say. For example, as the storage element, the above-described vertical ROM or horizontal R
EE that enables electrical erasure in addition to OM and EPROM
Various embodiments such as those constituting a PROM can be adopted. The address selection method, the configuration of the memory array, and the reading method can employ various embodiments. The number of spare dummy data lines may be two or more. The switching to the dummy data line can be performed in various embodiments such as a method using a fuse unit, a method using wire bonding, and a method using an electrically writable storage element. The present invention can be widely used for a semiconductor memory device using a differential type sense amplifier as described above.

[0055]

The effects obtained by typical ones of the inventions disclosed in the present application will be briefly described as follows. That is, for reading from a memory array in which storage elements are arranged in a matrix, a plurality of dummy data lines to which dummy storage elements for forming a reference voltage are connected are prepared, and a defect is selected from among the plurality of dummy data lines by a selector. By selecting one non-existent dummy data line and supplying it to the differential sense amplifier to sense the stored information, if there is a defect in the dummy data line, the selector sets the spare data. By switching to the line, the relief can be performed, so that the product yield can be increased.

[Brief description of the drawings]

FIG. 1 is a main part circuit diagram showing one embodiment of a vertical ROM to which the present invention is applied.

FIG. 2 is a main part circuit diagram showing another embodiment of the semiconductor memory device according to the present invention.

FIG. 3 is a specific circuit diagram of one embodiment including a selection control circuit in the semiconductor memory device according to the present invention.

FIG. 4 is a main part circuit diagram showing one embodiment of a horizontal ROM to which the present invention is applied.

[Explanation of symbols]

W0-Wn ... word line, D0-Dn ... data line, DD
0, DD1 ... Dummy data line, MB0, MB1 ... Memory block, XPDCR ... Predecoder circuit, DCR0,
DCR1: Decoder circuit, YDCR: Column decoder circuit, SA: Differential sense amplifier, SEL: Selector, S
LC: selection control circuit, CW: column switch, DR: resistor, PAD: pad, F: fuse means, G1: NOR gate circuit, G2, G3: AND gate circuit, N1 to N5
... Inverter circuit, M-ARY ... Memory array, XAD
B ・ DCR ... X address buffer / decoder, YADB
DCR: Y address buffer decoder, PA0, P
A1, DPA: preamplifier, A0, A1: differential amplifier.

────────────────────────────────────────────────── ─── Continued on the front page (72) Inventor Takeshi Furuno 5-20-1, Kamisumihonmachi, Kodaira-shi, Tokyo Inside the Musashi Plant, Hitachi, Ltd. (56) References JP-A 64-80069 (JP, A) JP-A-1-279498 (JP, A) JP-A-1-235098 (JP, A) JP-A-2-196444 (JP, A) (58) Fields investigated (Int. Cl. ⁷ , DB name) H01L 27/10 G11C 17/12 H01L 21/82 H01L 21/8246 H01L 27/112

Claims (5)

(57) [Claims] 1. A memory array in which storage elements are arranged in a matrix, a plurality of dummy data lines in which dummy storage elements forming a read reference voltage of the storage elements are coupled, and a plurality of dummy data lines. A selector for selecting one dummy data line having no defect, and a difference for sensing storage information of a selected storage element in the memory array with reference to a reference voltage of the selected dummy data line via the selector. A semiconductor memory device comprising a dynamic sense amplifier. 2. The method according to claim 1, wherein the selection signal for selecting one dummy data line from the plurality of dummy data lines is formed based on whether or not fuse means is cut.
Semiconductor storage device. 3. A resistance means equivalent to a dummy storage element is selectively connected to a reference potential side of the differential type sense amplifier, and a read result of a data line based on the resistance means is connected to the plurality of dummy sense elements. 3. The semiconductor memory device according to claim 1, wherein the quality of the dummy data line is determined by comparing a read result based on the data line. 4. The semiconductor memory device according to claim 1, further comprising a circuit for switching a defective dummy data line to a redundant data line using an electrode to which a predetermined potential is applied during probing. 5. The semiconductor memory device according to claim 4, further comprising a circuit for switching a defective dummy data line to a redundant data line by cutting the fuse means.