JPH04251495A - Semiconductor memory - Google Patents

Abstract

PURPOSE:To decrease the bit line current of a read port and to improve data reading speed by detecting potential difference between bit lines by a differential sense amplifier in the case of reading a memory. CONSTITUTION:Two memory arrays MA1 and MA2 are provided while respectively providing peculiar bit lines BLa1, BLb1, BLar and BLbr composed of a single line and allocating high-order side P1a and P1b of word lines to one memory array and low-order side P2a and P2b of word lines to the other. A sense amplifier SA1a detects whether potential difference is generated between the bit lines BLar and BLbr in the case of reading the memory or not and further, a data formation part EC1a forms a read data Oa by comparing this detected result with an address signal selected at that time point. Thus, even when the voltage amplitude of the bit line is small, reading is enabled, current consumption is reduced and reading speed can be improved.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated device suitable as a multi-port static RAM, and more particularly to a semiconductor device equipped with a memory array having a single bit line.

0002

2. Description of the Related Art FIG. 10 shows an example of a multi-port static RAM having a plurality of read bit lines. As shown in the figure, this static RAM has a pair of bit lines (W, inverted W) as a write port.
and two bit line pairs (BLm
, inverted BLm), (BLn, inverted BLn), and three word lines (Word W, Wo
By connecting rd Ra, Word Rb) to a decoder, it is possible to write data to one of three different addresses in the same cycle and read that data from the other two addresses simultaneously (W+R+R 3 ports). example).

Another example of a multi-port static RAM having a plurality of read bit lines is shown in FIG. As shown in the figure, in this static RAM, the write port is configured as a pair of bit lines (W, inverted W), and the read port is configured as a single line (BLn, inverted BL).
m), the same function as in FIG. 10 is realized (example of W+R+R3 ports).

In the case of the static RAM shown in FIG. 10, by connecting the read port bit line pair BLn and inverted BLn to each input of the differential amplifier, the voltage amplitude of the bit line pair is suppressed and the bit line current is reduced. , data can be read out at high speed, but on the other hand, there is a problem with high integration because the number of elements per cell is large. On the other hand,
In the case of the static RAM shown in Figure 11, the number of elements per cell is small, which is advantageous for high integration, but on the other hand, the read port has only one bit line, so it is difficult to read data. cannot connect a differential amplifier, so a single-bit sense amplifier must be used. In order to operate a single-bit type sense amplifier, the bit line voltage amplitude at the read port must be made larger than that of a differential type sense amplifier, which inevitably increases the bit line current and increases the data read speed. It becomes a hindrance.

[0005]

[Problems to be Solved by the Invention] As mentioned above, the cell structure shown in FIG. 11 is advantageous in order to increase the integration of multi-port static RAM. Since the port has only one bit line, a single-bit sense amplifier must be connected, resulting in problems such as an increase in bit line current and a decrease in data read speed.

The present invention has been made in view of the above-mentioned problems, and its purpose is to provide a multi-port static RAM as shown in FIG. 11 described above.
An object of the present invention is to reduce the bit line current of a read port and increase the data read speed in a semiconductor memory device having a memory cell in which the bit line of one read port is a single line.

[0007]

[Means for Solving the Problems] A diagram illustrating the principle of the invention according to claim 1 is shown in FIG. As shown in the figure, this semiconductor memory device has a unique bit line (BLal) consisting of a single line.
, BLbl), and (BLar, BLbr), and one is assigned the upper side of the word line (P1a, P1b), and the other is assigned the lower side of the word line (P2a, P2b). memory array (MA1, MA
2) and the memory array (MA1) on the upper side of the word line
and the memory array (MA2) on the lower side of the word line, there are differential sense amplifiers (SA1a, SA1b) that operate based on the difference in bit line voltage between the two, and based on the output of the differential sense amplifier. Each memory cell (MC1 to M
A data forming circuit (EC1a, EC1b) that forms read data (Oa, Ob) of Cn) is provided.

A diagram illustrating the principle of the invention according to claim 2 is shown in FIG. As shown in the figure, this semiconductor memory device includes a memory array (MA1) having single bit lines (BLal, BLbl), and one input of which is a bit line (BLal, BLbl) of the memory array (MA1). ) is connected to the differential sense amplifier (SA1), and the other input is connected to the capacitor (C1), and the potential of the bit line and the potential of the capacitor can be set to the same potential. equalizer circuit (
In the figure, it is characterized by comprising an equalizer transistor T1).

[0009]

[Operation] An explanatory diagram of the operation of the invention according to claim 1 is shown in FIG. In this invention, since the bit line of each read port is a single line and each read address is also one per cycle, the bit line B of the two memory arrays MA1 and MA2 is
The sense amplifier SA1a detects whether a potential difference occurs between Lar and BLal, and the data forming section EC1a compares this detection result with the address signal selected at that time, thereby forming read data Oa. I have to.

That is, according to the present invention, since the potential difference between the bit lines BLar and BLal is detected by the differential sense amplifier SA1a when reading the memory, data can be read even if the voltage amplitude of the bit lines is small. can. Therefore, since the voltage amplitude of the bit line is small, compared to using an inverter type sense amplifier,
The time for detecting the bit line current and read data becomes faster, and the memory array area can be reduced without significantly worsening the read time and current consumption compared to the memory cell shown in FIG.

FIG. 4 is a diagram illustrating the operation of the invention according to claim 2. In this invention, when precharging the bit line BLal, by turning on the equalizer transistor T1 with the equalizer pulse PE, the differential sense amplifier S
Each input of A1 is equalized to a precharge potential. Thereafter, after the bit line BLal and the input of the sense amplifier SA1 are sufficiently precharged, the precharge transistor T2 and the equalizer transistor T1 are turned off, and the word line P1a is selected.

At this time, the read port bit line BLa1
If is discharged, sense amplifier SA
1's input IN2 is lower than the precharge potential, whereas the input IN1 of the sense amplifier SA1 maintains the precharge potential, the potential difference between the two is amplified and the output Sout of the sense amplifier SA1 has a predetermined value. A high potential appears. The Sout level at this time is assumed to be V1.

On the other hand, bit line B of the read port
If La1 is not discharged, the input IN2 of the sense amplifier SA1 is held at a precharged potential, so the output Sout of the sense amplifier SA1 becomes a predetermined low potential. The Sout level at this time is assumed to be V2. Therefore, when the output Sout of the sense amplifier SA1 is V1, it becomes "H", and the output Sout of the sense amplifier SA1 becomes "H".
By setting the threshold level Vth of the inverter IV at the next stage of the sense amplifier so that ut is "L" when it is V2, data can be read from the corresponding memory cell.

In the case of the invention of claim 2, although the bit line voltage can be made to have a low amplitude, compared to the invention of claim 1, the bit line capacitance is reduced by the fact that the bit line is not divided.・Both resistances are large, which causes a slight delay in both precharge and discharge. However, in the case of the invention of claim 1, the sense amplifier is arranged in the middle of the memory array, which makes the layout complicated, whereas in the case of the invention of claim 2, the sense amplifier is arranged at the end of the memory array. This has the advantage of simplifying the layout.

[0015]

DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 5 shows a configuration diagram of a first embodiment of the present invention, and FIG. 6 shows an explanatory diagram of its operation. As shown in the figure, this semiconductor memory device has a unique bit line BL1 consisting of a single line.
, BL2, and one has the upper half of the word line (~WN) and the other has the lower half of the word line (~WN).
between the two memory arrays MA1 and MA2 to which W1~) are respectively assigned, and the memory array MA2 on the upper side of the word line and the memory array MA1 on the lower side of the word line, due to the difference in bit line voltage between the two. The memory contents of each memory cell MC1 to MCN are determined based on the operating differential sense amplifiers SA1 to SAN, the output SAO of the differential sense amplifiers, and address information (in this case, the contents of the most significant address bit MAB). Corresponding read data DAT
A data formation circuit EDN (in the figure, E-NO
R).

The semiconductor memory device shown in the figure is shown in FIG.
This is a 3-port static RAM shown in , and each read port has one bit line. However, for the sake of explanation, in order to make it easier to understand the operation of the bit lines, memory cells MC1 to MCN are shown with transistor T1 and capacitance. C
It shall be equivalently expressed as 1. In FIG. 5, an address signal is input to address decoder AD, and a precharge signal is input to terminal PCLK to precharge bit lines BL1 and BL2 to arbitrary potentials.

Next, when the precharge signal ends, the terminal LG is set to "H" level to activate the sense amplifier. At this time, the bit lines BL1 and BL2 have the same potential, and the output SAO of the sense amplifier SA1 does not reach the power supply voltage level. At this time, the value of the output SAO must be designed to be lower (“L”) than the EOR threshold (VTH) of the data forming circuit EDN.

Now, suppose that the most significant bit MAB of the address is “
“L” and the decode signal of address decoder AD is W.
1, memory cell C1 is selected and transistor T1 is turned on. At this time, the capacity C
If the bit line BL1 is charged with electric charge, the potential of the bit line BL1 does not change, and the potential of the bit line BL2 also does not change. the result,
The output signal SAO of the sense amplifier is taken into the data forming circuit EDN as it is "L". On the other hand, address signal MA
Since B is "L", "H" is output as the output signal DATA of the data forming circuit EDN.

Further, in the above state, if the capacitor C1 is not charged, the potential of the bit line BL1 will decrease by the amount of the charge of the capacitor C1, creating a potential difference with the bit line BL2. , the output signal SAO of the sense amplifier is input to the data formation circuit EDN, and the output signal DATA becomes "L" level. Next, a case where the most significant address bit MAB is "H" and the decode signal from the address decoder AD is output to the word line WN will be described. As described above, a precharge start signal is applied to the terminal PCLK, and an address signal is applied to the address decoder AD. Then, bit lines BL1, B
L2 is precharged to an arbitrary potential via precharge transistors PE1 and PE2.

At this time, since the bit lines BL1 and BL2 are at the same potential, the output signal SAO of the sense amplifier is "L", but since the most significant address bit MAB is "H",
Signal MAB (“L”) inverted by inverter EI1
), the bias transistor EP1 is turned on, and the potential of the output signal SAO of the sense amplifier becomes “H” level (ER
It is pulled up to a voltage at which O is recognized as a minimum "H" level.

At this time, if the output of address decoder AD is being output to word line WN, transistor TN is turned on. If the capacitor CN is charged, the potential of the bit line BL2 does not change and the output SAO of the sense amplifier remains at "H" level by the transistor EP1. The output signal DATA becomes "H".

On the other hand, when the capacitor CN is not charged, the potential of the bit line BL2 decreases by the amount of charge of the capacitor CN, and a potential difference occurs between the bit lines BL1 and BL2, causing the output signal of the sense amplifier to decrease. becomes “L” level,
The output signal DATA of the data forming circuit EDN becomes "L". In this case, transistor EP1 and sense amplifier SA
It is preferable to adjust the ratio of 1 so that a large current does not flow.

Next, FIG. 7 shows a configuration diagram of a second embodiment of the present invention.
Shown below. In this embodiment, the data forming circuit E uses transfer gates TG1 and TG2 consisting of MOSFETs.
It constitutes the DN. After precharging the bit line,
The operation up to discharging the bit line is similar to the first embodiment, but in this embodiment, the transfer gate of the selected memory array is selected based on the contents of the most significant bit MAB of the input read address. TG1,
By opening TG2, either of the two outputs of the sense amplifier SA is output as read data DATA.

Next, FIG. 8 shows a configuration diagram of a third embodiment of the present invention.
FIG. 9 shows an explanatory diagram of its operation. In this embodiment, two inverters IV01 and IV0 with different threshold values Vth are used.
2 and E-OR constitute a data forming circuit EDN. The operation from precharging the bit line to discharging the bit line is the same as in the first embodiment, but in this embodiment, as shown in FIG.
The output SAO of the sense amplifier SA1 is distinguished between "H" and "L" by utilizing the difference in threshold values of the two inverters IV01 and IV02, and read data DATA is formed.

As described above, according to the semiconductor memory device of the above embodiment, a differential sense amplifier is arranged between the memory array divided into two parts, and one end of the divided bit line is connected to each of the inputs of the differential sense amplifier. By connecting the data formation circuit to the output of the sense amplifier, the bit line voltage amplitude is smaller than when using a conventional single-bit sense type amplifier, resulting in lower power consumption and lead-in performance due to a reduction in bit line current. Access time can be shortened.

Furthermore, according to the second aspect of the invention, in addition to the effects of the above embodiments, layout design can be simplified. In each of the above embodiments, the present invention is applied to a multi-port static RAM, but the present invention can be widely applied to semiconductor memory devices having memory cells in which one read port has a single bit line. .

[0027]

[Effect of the invention] As is clear from the above explanation, claim 1
According to the invention, in a semiconductor memory device having a memory cell in which one read port has a single bit line, such as a highly integrated multi-port static RAM,
By reducing the bit line current of the read port, power consumption can be reduced and data read speed can be increased.

Furthermore, according to the invention of claim 2, in addition to the effects of the invention of claim 1, the layout design becomes easy.

[Brief explanation of the drawing]

FIG. 1 is a diagram illustrating the principle of the invention according to claim 1.

FIG. 2 is an explanatory diagram of the operation of the invention of claim 1.

FIG. 3 is a diagram illustrating the principle of the invention according to claim 2.

FIG. 4 is an explanatory view of the operation of the invention according to claim 2.

FIG. 5 is a configuration diagram of the first embodiment.

FIG. 6 is an explanatory diagram of the operation of the first embodiment.

FIG. 7 is a configuration diagram of a second embodiment.

FIG. 8 is a configuration diagram of a third embodiment.

FIG. 9 is an explanatory diagram of the operation of the third embodiment.

FIG. 10 is a configuration diagram of a conventional device.

FIG. 11 is a configuration diagram of a conventional device.

[Explanation of symbols]

MA1, MA2...Memory array MC1, MCn...Memory cells BLal, BLbl, BLar, BLbr...Bit line S
A1a, SA1b...Sense amplifiers Oa, Ob...Read data EC1a, EC1b...Data forming section MAB...Address highest signal

Claims (2)

[Claims] Claim 1: Unique bit line (BL
al, BLbl) and (BLar, BLbr), respectively, and one side has the upper side of the word line (P1a, P1b
), and the other has two memory arrays (MA1, P2b) assigned to the lower side of the word line (P2a, P2b), respectively.
MA2) and the memory array (MA2) on the upper side of the word line
2) and the memory array (MA1) on the lower side of the word line, there are differential sense amplifiers (SA1a, SA1b) that operate based on the difference in bit line voltage between the two, and the output of the differential sense amplifier. 1. A semiconductor memory device comprising: a data forming circuit (EC1a, EC1b) that forms the storage contents of each memory cell based on the data. 2. Bit line consisting of a single line (BLal,
A memory array (MA1) having a memory array (BLbl), and a differential sense amplifier having one input connected to the bit line (BLal) of the memory array and the other input connected to a capacitance (C1). A semiconductor memory device comprising: (SA1) and an equalizer circuit (T1) capable of setting the potential of the bit line and the potential of the capacitor to the same potential.