CN112967740A - Super-high speed read circuit and read method for nonvolatile memory - Google Patents
Super-high speed read circuit and read method for nonvolatile memory Download PDFInfo
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- CN112967740A CN112967740A CN202110142149.3A CN202110142149A CN112967740A CN 112967740 A CN112967740 A CN 112967740A CN 202110142149 A CN202110142149 A CN 202110142149A CN 112967740 A CN112967740 A CN 112967740A
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/06—Sense amplifiers; Associated circuits, e.g. timing or triggering circuits
- G11C7/065—Differential amplifiers of latching type
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/12—Bit line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, equalising circuits, for bit lines
Abstract
The invention relates to a nonvolatile memory ultra-high speed reading circuit, which comprises a memory cell array, a reading reference array and a sensitive amplifier, wherein the sensitive amplifier is a latch type sensitive amplifier and comprises: the first transmission gate is used for controlling whether to receive the electric signals read out by the selected memory cells of the memory cell array; a second transmission gate for controlling whether to receive the read reference electrical signal generated by the read reference array; the latch module comprises two input ends, one input end is connected with the first transmission gate, the other input end is connected with the second transmission gate, and the latch module is used for comparing the difference of the electric signals of the two input ends and amplifying the electric signals of the two input ends in a comparison stage; the first transmission gate and the second transmission gate are respectively provided with a pre-charging module, and the pre-charging modules are used for keeping electric signals of the first transmission gate and the second transmission gate within a preset range in a pre-charging stage. The invention can shorten the reading time.
Description
Technical Field
The present invention relates to the field of integrated circuit technology, and more particularly, to a super high speed read circuit and read method for a nonvolatile memory.
Background
The read operation of the nonvolatile memory is performed by measuring the resistance value of the selected memory cell. A preset voltage or current is added to the selected memory cell, and the current flowing through the memory cell or the voltage at two ends is read at the same time; the read current or voltage is then compared to a reference read current or voltage to determine the phase state of the memory cell. The reference read voltage generation circuit is used for generating a reference read current or voltage, and the sense amplifier is used for generating a read current and comparing the read current with the reference read current.
When the memory array is larger than a certain size, the read current will be changed drastically after the read operation starts due to the parasitic effect in the array, and the conventional current comparison type sense amplifier (see the prior published patent document CN106875963A) can obtain the correct comparison result only after the read current tends to be stable, thereby limiting the read speed. For example, when applied to a 512Kb per sense amplifier memory array design, the read time is about 40 ns.
Disclosure of Invention
The invention aims to provide a nonvolatile memory ultra-high speed reading circuit and a reading method, which can shorten the reading time.
The technical scheme adopted by the invention for solving the technical problems is as follows: there is provided a non-volatile memory ultra high speed sensing circuit, including a memory cell array, a read reference array and a sense amplifier, wherein bit lines in the memory cell array are connected to the sense amplifier, the sense amplifier is connected to the read reference array, and compares read reference electrical signals of the read reference array with electrical signals sensed by selected memory cells in the memory cell array to generate read electrical signals of the selected memory cells, the sense amplifier is a latch-type sense amplifier, including: the first transmission gate is connected with the memory cell array and is used for controlling whether to receive the electric signals read out by the selected memory cells in the memory cell array; the second transmission gate is connected with the read reference array and used for controlling whether to receive the read reference electric signal generated by the read reference array or not; the latch module comprises two input ends, one input end is connected with the first transmission gate, the other input end is connected with the second transmission gate, and the latch module is used for comparing the difference of the electric signals of the two input ends and amplifying the electric signals of the two input ends in a comparison stage; the first transmission gate and the second transmission gate are respectively provided with a pre-charging module, and the pre-charging modules are used for keeping electric signals of the first transmission gate and the second transmission gate within a preset range in a pre-charging stage.
The latch-type sensitive amplifier also comprises a balancing module which is used for enabling the input electric signals of the two input ends of the latch module to be equal in the standby stage.
The latch module amplifies a larger electric signal of the electric signals of the two input ends to a first preset value and amplifies a smaller electric signal of the electric signals of the two input ends to a second preset value during amplification.
The latch module comprises a first NMOS (N-channel metal oxide semiconductor) tube, a second NMOS tube, a second PMOS (P-channel metal oxide semiconductor) tube and a third PMOS tube; the grid electrode of the first NMOS tube is connected with the first transmission gate, the source electrode of the first NMOS tube is connected with the grounding end of the latch module, and the drain electrode of the first NMOS tube is connected with the drain electrode of the second PMOS tube; the grid electrode of the second NMOS tube is connected with the second transmission gate, the source electrode of the second NMOS tube is connected with the grounding end of the latch module, and the drain electrode of the second NMOS tube is connected with the drain electrode of the third PMOS tube; the grid electrode of the second PMOS tube is connected with the first transmission gate, and the source electrode of the second PMOS tube is connected with the power supply end of the latch module; the grid electrode of the third PMOS tube is connected with the second transmission gate, and the source electrode of the third PMOS tube is connected with the power supply end of the latch module; the drain electrode of the first NMOS tube is also connected with the second transmission gate, and the drain electrode of the second NMOS tube is also connected with the first transmission gate.
The latch-type sensitive amplifier also comprises a control module, and the control module is used for controlling the working state of the latch module.
The control module comprises a first PMOS tube and a third NMOS tube, the grid electrode of the first PMOS tube is connected with the reading control inverted signal, the source electrode of the first PMOS tube is connected with the power supply end, and the drain electrode of the first PMOS tube is connected with the power supply end of the latch module; and the grid electrode of the third NMOS tube is connected with the reading control signal, the source electrode of the third NMOS tube is grounded, and the drain electrode of the third NMOS tube is connected with the grounding end of the latch module.
The preset range is between the threshold electric signals of the memory unit in the amorphous state and the crystalline state or is lower than the amorphous threshold voltage of the phase change memory resistor.
The read reference array is another memory cell array that does not enter the selected phase.
The word line address signal of the other memory cell array which does not enter the selected phase is always in the unselected state.
The other memory cell array which does not enter the selected stage shares a word line address signal with the memory cell array, and the bit line address signal of the other memory cell array which does not enter the selected stage is always in a non-selected state.
The read reference array comprises a reference unit, a bit line matching module, a transmission gate parasitic parameter matching module and a word line matching module; the reference unit is connected between the reference word line and the reference bit line and used for providing a reference resistance value; the bit line matching module is connected between the reference bit line and the unselected word line and used for providing leakage parasitics on the bit lines to match the leakage parasitics of the memory cells on the bit lines in the memory cell array; the transmission gate parasitic parameter matching module is connected to the reference bit line and used for providing transmission gate parasitic parameters to match the transmission gate parasitic parameters in the memory cell array; the word line matching module is connected between the reference word line and the unselected bit line and used for providing leakage parasitics on the word line to match leakage parasitics of the memory cells on the word line in the memory cell array.
The technical scheme adopted by the invention for solving the technical problems is as follows: also provides a reading method of the ultra-high speed reading circuit of the nonvolatile memory, which comprises the following steps:
a pre-charging stage: opening a first transmission gate and a second transmission gate, and charging input ends of the first transmission gate and the second transmission gate through the pre-charging module so that electric signals at two ends of the latching module are maintained within a preset range;
selecting a stage: stopping precharging, selecting a memory cell in the memory cell array, and generating difference in electric signals at two ends of the latch module due to difference of resistance and threshold voltage in the memory cell array and a read reference array;
a comparison stage: and the latch module enters a working state, compares the electric signals at the two ends to obtain a comparison result, amplifies the electric signals at the two ends and generates a read electric signal of the selected storage unit.
The pre-charging phase is preceded by a standby phase: the balancing module enables the input electric signals of the two input ends of the latch module to be equal in a standby stage.
Advantageous effects
Due to the adoption of the technical scheme, compared with the prior art, the invention has the following advantages and positive effects: the invention realizes the reading time of about 1ns by adopting the voltage latch type sensitive amplifier and matching technologies such as pre-charging, bit lines, word lines, transmission gate parasitic leakage and the like, and the speed is improved by more than 40 times compared with the traditional technology.
Drawings
FIG. 1 is a schematic structural view of a first embodiment of the present invention;
FIG. 2 is a schematic diagram of a sense amplifier according to a first embodiment of the present invention;
FIG. 3 is a schematic diagram of a read reference array according to a first embodiment of the present invention;
fig. 4 is a read timing chart of the first embodiment of the present invention;
FIGS. 5 and 6 are graphs of simulation results of the first embodiment of the present invention;
fig. 7 is a schematic structural view of a second embodiment of the present invention.
Detailed Description
The invention will be further illustrated with reference to the following specific examples. It should be understood that these examples are for illustrative purposes only and are not intended to limit the scope of the present invention. Further, it should be understood that various changes or modifications of the present invention may be made by those skilled in the art after reading the teaching of the present invention, and such equivalents may fall within the scope of the present invention as defined in the appended claims.
The embodiment of the invention relates to a nonvolatile memory ultra-high speed reading circuit, which comprises a memory cell array, a read reference array and a sense amplifier, wherein bit lines in the memory cell array are connected with the sense amplifier, the sense amplifier is connected with the read reference array, and a read reference electric signal of the read reference array is compared with an electric signal read by a selected memory cell of the memory cell array to generate a read electric signal of the selected memory cell.
In this embodiment, the memory cell array includes a WL driver module, which is responsible for applying a word line address signal X1～n(digital) conversion to analog control signal WL1～nAnd output to one end of a gate tube SEL when X is1～nIs effective at high level, when X1～nAnd is inactive when low. Wherein the bit line address signal Y of the memory cell1～nControls the switching of the local transmission gate LTG. When Y is1～nIs effective at high level, when Y is1～nAnd is inactive when low.
As shown in fig. 2, the sense amplifier is a voltage latch type sense amplifier, and includes a first transmission gate TG1, a second transmission gate TG2, a voltage balancing module, a control module, a latch module, and a precharge module.
The transmission gate TG1 is connected with the memory cell array and used for controlling whether to receive voltage signals read by the selected memory cells of the memory cell array; the second transmission gate TG2 is connected to the read reference array for controlling whether to receive a read reference voltage signal generated by the read reference array.
And the latch module comprises two input ends, one input end is connected with the first transmission gate TG1, the other input end is connected with the second transmission gate TG2, and the latch module is used for comparing the difference of the voltage signals of the two input ends and amplifying the voltage signals of the two input ends in a comparison stage. When the latch module is used for amplifying the larger voltage signal in the voltage signals of the two input ends to VDD and amplifying the smaller voltage signal in the voltage signals of the two input ends to VSS, so that a comparison result can be obtained quickly.
In this embodiment, the latch module includes a first NMOS transistor NM1, a second NMOS transistor NM2, a second PMOS transistor PM2, and a third PMOS transistor PM 3; the grid electrode of the first NMOS transistor NM1 is connected with the first transmission gate TG1, the source electrode is grounded, and the drain electrode is connected with the drain electrode of the second PMOS transistor PM 2; the grid electrode of the second NMOS transistor NM2 is connected with the second transmission gate TG2, the source electrode is grounded, and the drain electrode is connected with the drain electrode of the third PMOS transistor PM 3; the grid electrode of the second PMOS pipe PM2 is connected with the first transmission gate TG1, and the source electrode is connected with a power supply end VDD; the grid electrode of the third PMOS pipe PM3 is connected with the second transmission gate TG2, and the source electrode is connected with a power supply end VDD; the drain of the first NMOS transistor NM1 is further connected to the second transmission gate TG2, and the drain of the second NMOS transistor NM2 is further connected to the first transmission gate TG 1.
And the precharge module is respectively arranged at one end of the first transmission gate TG1 and one end of the second transmission gate TG2 and is used for keeping the voltage signals of the first transmission gate TG1 and the second transmission gate TG2 within a preset range in the precharge stage, wherein the preset range is between the threshold electric signals of the memory cell in an amorphous state and a crystalline state or is lower than the amorphous threshold voltage of the phase change memory resistor.
In this embodiment, the pre-charge module includes a fourth NMOS transistor NM4 and a fifth NMOS transistor NM5, wherein the gate of the fourth NMOS transistor NM4 is connected to the pre-charge signal PC, the source is connected to the first transmission gate TG1, and the drain is connected to the voltage V1PC(ii) a The gate of the fifth NMOS transistor NM5 is connected to the pre-charge signal PC, the source is connected to the second transmission gate TG2, and the drain is connected to the voltage VPC. Wherein the voltage VPCThe threshold voltage is set between the amorphous state and the crystalline state threshold voltage of the memory cell or lower than the amorphous state threshold voltage of the phase change memory resistor.
And the voltage balancing module is used for enabling the voltage signals input by the two input ends of the latch module to be equal in a standby stage so as to prepare for next reading. In this embodiment, the voltage balancing module includes a sixth NMOS transistor NM6, a gate of the sixth NMOS transistor NM6 is connected to the read control inverted signal, a source of the sixth NMOS transistor NM6 is connected to the end of the latch module connected to the first transmission gate TG1, and a drain of the sixth NMOS transistor NM6 is connected to the end of the latch module connected to the second transmission gate TG 2.
And the control module is used for controlling the working state of the latch module. In this embodiment, the control module includes a first PMOS transistor PM1 and a third NMOS transistor NM3, wherein a gate of the first PMOS transistor PM1 is connected to the read control inverted signal, a source is connected to the power supply terminal VDD, and a drain is connected to the power supply terminal of the latch module; the gate of the third NMOS transistor NM3 is connected to the read control signal, the source is grounded, and the drain is connected to the ground of the latch module.
As shown in fig. 3, the read reference array in this embodiment is used to provide reference value and parasitic leakage matching for the sense amplifier, and includes a reference cell 31, a bit line matching module 32, a transmission gate parasitic parameter matching module 34, and a word line matching module 33.
A word line matching module 33 connected to the reference word line WLRAnd the unselected bit line DESBL is used for providing leakage parasitics on the word lines to match the leakage parasitics of the memory cells on the word lines in the memory cell array; the word line matching module comprises (a-1) memory cells connected in parallel, wherein a is the number of bit lines connected to the same word line in the memory cell array.
The reference cell 31 comprises a reference resistor RREFAnd a gate tube SEL, wherein one end of the gate tube SEL is connected with the reference word line WLRThe other end is connected with the reference resistor RREFOne end of (a); the reference resistance RREFIs connected to the reference bit line BL at the other endR. The resistance value of the reference resistor is set between the highest value of the low-resistance-state resistor and the lowest value of the high-resistance-state resistor. The gate tube SEL and the gate tube in the storage unit are of the same type.
A bit line matching block 32 is connected to the reference bit line BLRAnd unselected bit lines DESWL, for providing leakage parasitics on the bit lines to match the leakage parasitics of the bit lines in the memory cell array; the bit line matching module comprises (n-1) storage units connected in parallelAnd n is the number of word lines connected to the same bit line in the memory cell array.
The transmission gate parasitic parameter matching module 34 includes a transmission gate LTG0A local transmission gate parasitic parameter matching unit LTG; the transmission gate LTG0Is connected to the reference bit line BLRAnd local reference bit line LBLRTo (c) to (d); the local transmission gate parasitic parameter matching unit LTG is connected to the local reference bit line LBLRAnd unselected bit lines DESWL for providing transfer gate parasitic parameters to match local transfer gate parasitic parameters in the memory cell array.
The local transmission gate parasitic parameter matching unit LTG comprises (m-1) third transmission gates connected in parallel, wherein m is the number of bit lines connected to the same local bit line in the memory cell array; the structure and size of each third transmission gate and the transmission gate LTG in the read reference circuit0The local transmission gates are the same as the local transmission gates in the memory cell array; one end of each third transmission gate is connected with the local reference bit line LBLRThe other end of the unselected bit line DESWL is connected with the unselected bit line DESWL, and the control end of the unselected bit line DESWL is grounded.
In the case of using the nonvolatile memory ultra-high speed read circuit of the present embodiment, the read sequence is illustrated in fig. 4, taking X1 and Y1 as high levels as an example of a selected memory cell, and the read sequence includes the following steps:
a standby stage: the word line address signal X1, the bit line address signal Y1, the read control signal RE, the precharge select signal EN, and the precharge signal PC are all 0. The sixth NMOS transistor is turned on, and the voltage VOUT1/VOUT2 is equal, namely, the voltage signals input at the two input ends of the latch module are equal.
A pre-charging stage: bit line address signals Y1, RE, EN, PC are high, and the sense amplifier pair LBL1And LBLRCharging to make voltage signal VLBL1Sum voltage signal VLBLRNot higher than VPC. The voltage signal V is generated by the first transmission gate TG1 and the second transmission gate TG2 being openedLBL1Sum voltage signal VLBLRV conducted to sense amplifiers respectivelyOUT1And VOUT2。
Selecting a stage: the X1 signal goes high, the PC signal goes low, precharge is stopped, and the memory cell is selected, due to the difference in resistance and threshold voltage of the reference cell in the memory array and the read reference array, the V of the sense amplifierOUT1And VOUT2A difference is generated where the voltage difference is small.
A comparison stage: y1, X1, EN go low, the memory cell is no longer selected, the first transmission gate TG1 and the second transmission gate TG2 are closed, and V of the sense amplifier is turned offOUT1And VOUT2The small voltage difference between them is amplified quickly, the higher voltage signal is amplified to VDD and the lower voltage signal is amplified to VSS, thus obtaining the correct comparison result.
As shown in fig. 5, the simulation result of reading the amorphous phase change resistor (R ═ 2M Ω) by using the readout circuit of the present embodiment is 1.19ns, and as shown in fig. 6, the simulation result of reading the crystalline phase change resistor (R ═ 10K Ω) by using the readout circuit of the present embodiment is 1.12ns, and the simulation result shows that the read time is about 1ns when the readout circuit is applied to the memory array design of 16Mb per sense amplifier, and the speed is improved by more than 40 times compared with the conventional technology.
The second embodiment of the present invention also relates to a nonvolatile memory super speed read circuit, which is different from the first embodiment in that another memory cell array that does not enter the selected phase is used as the read reference array in this embodiment, as shown in fig. 7. The X signal of the memory cell array which does not enter the selected stage is always low; or the memory cell array not entering the selected stage and the memory cell array share the same X signal, but the Y signal of the memory cell array entering the selected stage is not selected, so that the memory cell in the memory cell array not entering the selected stage is not selected. When reading, the memory cell array which does not enter the selected phase always is unselected, so that the memory cell array corresponds to a read reference array.
It is not difficult to find that the invention realizes the reading time of about 1ns by adopting the voltage latch type sensitive amplifier and matching the technologies of pre-charging, bit line, word line, transmission gate parasitic leakage and the like, and the speed is improved by more than 40 times compared with the traditional technology.
Claims (13)
1. A non-volatile memory ultra high speed sensing circuit comprising a memory cell array, a read reference array and a sense amplifier, bit lines in the memory cell array being connected to the sense amplifier, the sense amplifier being connected to the read reference array for comparing read reference electrical signals of the read reference array with electrical signals sensed by selected memory cells of the memory cell array to generate read electrical signals for the selected memory cells, the sense amplifier being a latch-type sense amplifier comprising: the first transmission gate is connected with the memory cell array and is used for controlling whether to receive the electric signals read out by the selected memory cells in the memory cell array; the second transmission gate is connected with the read reference array and used for controlling whether to receive the read reference electric signal generated by the read reference array or not; the latch module comprises two input ends, one input end is connected with the first transmission gate, the other input end is connected with the second transmission gate, and the latch module is used for comparing the difference of the electric signals of the two input ends and amplifying the electric signals of the two input ends in a comparison stage; the first transmission gate and the second transmission gate are respectively provided with a pre-charging module, and the pre-charging modules are used for keeping electric signals of the first transmission gate and the second transmission gate within a preset range in a pre-charging stage.
2. The ultra high speed readout circuit of nonvolatile memory according to claim 1, wherein said latch type sense amplifier further comprises a balancing module for equalizing input electric signals at two input terminals of said latch module in a standby phase.
3. The ultra high speed readout circuit of claim 1, wherein the latch module amplifies a larger one of the electrical signals at the two input terminals to a first predetermined value and amplifies a smaller one of the electrical signals at the two input terminals to a second predetermined value.
4. The ultra high speed read circuit of the nonvolatile memory according to claim 1, wherein the latch module comprises a first NMOS transistor, a second PMOS transistor, and a third PMOS transistor; the grid electrode of the first NMOS tube is connected with the first transmission gate, the source electrode of the first NMOS tube is connected with the grounding end of the latch module, and the drain electrode of the first NMOS tube is connected with the drain electrode of the second PMOS tube; the grid electrode of the second NMOS tube is connected with the second transmission gate, the source electrode of the second NMOS tube is connected with the grounding end of the latch module, and the drain electrode of the second NMOS tube is connected with the drain electrode of the third PMOS tube; the grid electrode of the second PMOS tube is connected with the first transmission gate, and the source electrode of the second PMOS tube is connected with the power supply end of the latch module; the grid electrode of the third PMOS tube is connected with the second transmission gate, and the source electrode of the third PMOS tube is connected with the power supply end of the latch module; the drain electrode of the first NMOS tube is also connected with the second transmission gate, and the drain electrode of the second NMOS tube is also connected with the first transmission gate.
5. The non-volatile memory ultra high speed sensing circuit according to claim 1, wherein the latch type sense amplifier further comprises a control block for controlling an operation state of the latch block.
6. The ultra-high speed readout circuit of the nonvolatile memory according to claim 5, wherein the control module comprises a first PMOS transistor and a third NMOS transistor, a gate of the first PMOS transistor is connected to the inverted signal of the read control, a source of the first PMOS transistor is connected to the power supply terminal, and a drain of the first PMOS transistor is connected to the power supply terminal of the latch module; and the grid electrode of the third NMOS tube is connected with the reading control signal, the source electrode of the third NMOS tube is grounded, and the drain electrode of the third NMOS tube is connected with the grounding end of the latch module.
7. The non-volatile memory ultra-high speed readout circuit according to claim 1, wherein the predetermined range is between threshold electrical signals of the memory cell in the amorphous and crystalline states or below an amorphous threshold voltage of the phase change memory resistance.
8. The non-volatile memory ultra high speed readout circuit according to claim 1, wherein the read reference array is another memory cell array which does not enter a selected phase.
9. The nonvolatile memory ultra high speed reading circuit according to claim 8, wherein the word line address signal of the other memory cell array which does not enter the selected phase is always in a non-selected state.
10. The nonvolatile memory ultra high speed read circuit according to claim 8, wherein the other memory cell array not entering the selected phase shares a word line address signal with the memory cell array, and the bit line address signal of the other memory cell array not entering the selected phase is always in a non-selected state.
11. The non-volatile memory ultra high speed sensing circuit according to claim 1, wherein the read reference array comprises a reference cell, a bit line matching module, a transmission gate parasitic parameter matching module and a word line matching module; the reference unit is connected between the reference word line and the reference bit line and used for providing a reference resistance value; the bit line matching module is connected between the reference bit line and the unselected word line and used for providing leakage parasitics on the bit lines to match the leakage parasitics of the memory cells on the bit lines in the memory cell array; the transmission gate parasitic parameter matching module is connected to the reference bit line and used for providing transmission gate parasitic parameters to match the transmission gate parasitic parameters in the memory cell array; the word line matching module is connected between the reference word line and the unselected bit line and used for providing leakage parasitics on the word line to match leakage parasitics of the memory cells on the word line in the memory cell array.
12. A method of reading out a non-volatile memory ultra high speed read out circuit according to any of claims 1 to 11, comprising the following stages:
a pre-charging stage: opening a first transmission gate and a second transmission gate, and charging input ends of the first transmission gate and the second transmission gate through the pre-charging module so that electric signals at two ends of the latching module are maintained within a preset range;
selecting a stage: stopping precharging, selecting a memory cell in the memory cell array, and generating difference in electric signals at two ends of the latch module due to difference of resistance and threshold voltage in the memory cell array and a read reference array;
a comparison stage: and the latch module enters a working state, compares the electric signals at the two ends to obtain a comparison result, amplifies the electric signals at the two ends and generates a read electric signal of the selected storage unit.
13. A method for sensing according to claim 12, wherein the pre-charge phase is preceded by a standby phase: the balancing module enables the input electric signals of the two input ends of the latch module to be equal in a standby stage.
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| CN116206648A (en) * | 2022-01-27 | 2023-06-02 | 北京超弦存储器研究院 | Dynamic memory, read-write method thereof and memory device |
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