JP2014220026A - Semiconductor device and method of switching data line - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device capable of contributing to improving operation margin during a data read operation while improving utilization efficiency of a substrate area.SOLUTION: A semiconductor device includes: first and second memory cell arrays; a first decoder circuit connecting one of a plurality of memory cells to a first circuit node in response to address information supplied to an address circuit; a second decoder circuit connecting one of the plurality of memory cells to a second circuit node in response to address information; a sense amplifier circuit; a current mirror circuit supplying a current mirror current to each of the first and second circuit nodes; a first selection circuit connecting one of a reference voltage input terminal and the first circuit node to a first input terminal of the sense amplifier circuit according to a first area signal; and a second selection circuit connecting one of the reference voltage input terminal and the second circuit node to a second input terminal of the sense amplifier according to a second area signal.

Description

  The present invention relates to a semiconductor device and a data line switching method.

  2. Description of the Related Art In recent years, magnetoresistive memory MRAM (Magnet Random Access Memory) has attracted attention among various types of memory devices that store data as the speed and capacity of semiconductor devices increase.

  Patent Document 1 discloses ROM (Read Only Memory) or EPROM (Erasable Programmable ROM) as a data storage area (paragraph [0021]). In this document, a plurality of dummy data lines (reference bit lines) in which a plurality of dummy cells (reference cells) for generating a reference voltage for sensing data are combined are prepared, and one dummy without a defect exists. A technique for selecting a data line with a selector and supplying it to a sense amplifier is disclosed.

  Patent Document 2 discloses the above-described MRAM as a data storage area. This document discloses a technique for generating a reference voltage for sensing data in a memory cell using a dummy cell (reference cell) that stores data “0” and a dummy cell that stores data “1”. In the technique disclosed in Patent Document 2, a common redundant data line is provided for a dummy data line in which a plurality of dummy cells are coupled and a normal data line (bit line), and defects and dummy data generated in the normal data line are provided. Replace both defects in the line.

  Patent Document 3 discloses the above-described MRAM as a data storage area. In this document, a reference cell and a spare reference cell for generating a reference voltage for sensing data of a memory cell are prepared, and both are used by appropriately switching in accordance with manufacturing variations and deterioration with time of reference cell characteristics. Technology is disclosed.

  Patent Document 4 discloses the above-described MRAM as a data storage area. This document discloses a method and circuit box for selecting a reference cell from among all cells.

  Non-Patent Document 1 relates to the MRAM described above. This document discloses a technique in which a specific reference cell is always selected and supplied to a sense amplifier from a reference word line in which a plurality of reference cells for generating a reference voltage for sensing data in a memory cell are coupled. Yes.

JP-A-5-136361 JP 2002-222589 A JP 2004-062922 A JP 2012-209004 A

Kenji Tsuchida, et. Al., "A 64Mb MRAM with Clamped-Reference and Adequate-Reference Schemes", ISSCC2010 / SESSION14 / NON-VOLATILE MEMORY / 14.2, 9 February 2010, p.258-260

  Each disclosure of the above prior art document is incorporated herein by reference. The following analysis was made by the present inventors.

  The technique disclosed in Patent Document 1 has a problem that the use efficiency of the substrate area is low because dummy data lines that are not selected always exist, and the dummy data lines are supplied to a large number of sense amplifiers.

  The technology disclosed in Patent Document 2 can effectively utilize redundant data lines, but simply replaces dummy data lines having defects with redundant data lines, and the characteristics of the dummy cells of the redundant data lines. There is a problem that can not cope with the variation.

  The technique disclosed in Patent Document 3 has a degree of freedom in which a better reference cell characteristic can be selected as appropriate, but has a problem that the use efficiency of the substrate area is poor because the number of reference bit lines is doubled.

  Patent Document 4 does not disclose a specific circuit configuration for selecting a reference cell from all cells. In the technique disclosed in Patent Document 4, the first reference current Iref1 and the second reference current Iref2 are generated by different current sources, a plurality of current sources are required, and the utilization efficiency of the substrate area is improved. bad.

  According to a first aspect of the present invention, a first memory cell array including a plurality of resistance change type first memory cells, a second memory cell array including a plurality of resistance change type second memory cells, a first circuit node, A second circuit node, an address circuit to which address information is supplied, and one memory cell of the plurality of first memory cells in accordance with the address information supplied to the address circuit. And a second decoder circuit for connecting one memory cell of the plurality of second memory cells to the second circuit node according to the address information supplied to the address circuit. A first reference voltage input terminal to which a variable voltage is supplied, a first sense amplifier circuit including first and second input terminals, and each of the first and second circuit nodes. A first current mirror circuit that supplies one current mirror current, and one of the first reference voltage input terminal and the first circuit node is connected to the first input terminal of the first sense amplifier circuit according to a first region signal. A first selection circuit to be connected and a second selection circuit for connecting one of the first reference voltage input terminal and the second circuit node to the second input terminal of the first sense amplifier circuit according to a second region signal A semiconductor device is provided.

  According to a second aspect of the present invention, a step of extracting a reference cell group from a plurality of resistance change type first memory cell groups arranged in a matrix at intersections of a plurality of word lines and a plurality of bit lines; Extracting the first memory cell from the reference cell group as a reference cell; and if there is at least one defective memory cell in the remaining memory cell group other than the extracted reference cell group, the at least one defect Replacing a memory cell with a memory cell other than the first memory cell extracted as a reference cell in the extracted reference cell group.

  According to each aspect of the present invention, there is provided a semiconductor device and a data line switching method that contributes to an improvement in an operation margin during a data read operation while improving the utilization efficiency of the substrate area.

3 is a diagram illustrating an example of a circuit configuration of a read circuit according to the first embodiment. FIG. It is a figure which shows an example of the structure which tests the semiconductor device 1 which concerns on 1st Embodiment. 1 is a diagram illustrating an example of an overall configuration of a semiconductor device 1 according to a first embodiment. 2 is a diagram illustrating an example of a configuration of a main part of a memory cell array and a peripheral control circuit thereof in the semiconductor device 1. FIG. FIG. 5 is a diagram illustrating an example of a circuit configuration of a column selector 41 illustrated in FIG. 4. 3 is a diagram illustrating an example of a circuit configuration of a column decoder 32. FIG. 3 is a diagram illustrating an example of a circuit configuration of a first write circuit 43 and a second write circuit 44. FIG. 3 is a diagram illustrating an example of a circuit configuration of a switch 45. FIG. It is a figure which shows an example of the signal voltage obtained from a memory cell, and its frequency distribution. 4 is a flowchart showing an example of operations of the semiconductor device 1 and the test device 2. 4 is a flowchart showing an example of an operation related to selection / determination of a reference bit line by the test apparatus 2; It is a figure which shows an example of the reference bit line selection result which concerns on 1st Embodiment. It is a figure which shows an example of the reference word line selection result concerning 1st Embodiment. It is a figure which shows an example of the signal voltage obtained from a memory cell, and its frequency distribution. It is a flowchart which shows an example of the operation | movement which concerns on selection / determination of the reference cell by the test apparatus 2a which concerns on 2nd Embodiment. It is a figure which shows an example of the reference cell selection result which concerns on 2nd Embodiment. It is a figure which shows an example of the circuit structure of the column decoder 32a. It is a figure which shows an example of a structure of the main part of the memory cell array of the semiconductor device 1c which concerns on 4th Embodiment, and its periphery control circuit.

[First Embodiment]
Each embodiment of the present invention relates to an STT-RAM (Spin Transfer Torque Random Access Memory) among the magnetoresistive memories MRAM. The first embodiment will be described in detail with reference to the drawings.

  FIG. 1 is a diagram illustrating an example of a circuit configuration of the read circuit 42 according to the first embodiment.

  The read circuit 42 can be used for reading the reference data stored in the reference cell in addition to reading the normal data stored in the memory cell, and extracts an optimal reference cell from a reference cell group including a plurality of reference cells. Available to do. In particular, this circuit includes two nodes (A01 / A02, A03 / A04) to which current is supplied from the same current source, and a variable reference voltage input terminal VR to which a variable voltage is supplied. Details will be described later.

  FIG. 2 is a diagram illustrating an example of a configuration for testing the semiconductor device 1 according to the present embodiment.

  The test system shown in FIG. 2 includes a semiconductor device 1 and a test device 2 connected to the semiconductor device 1.

  The semiconductor device 1 includes a read circuit 42 (not shown) shown in FIG. The variable reference voltage input terminal VR of the read circuit 42 is configured to receive a variable voltage output from the test apparatus 2. The semiconductor device 1 includes a chip control circuit 23. The chip control circuit 23 generates an internal control signal necessary for selecting a reference bit line (reference cell group). Details will be described later in FIG.

  The test apparatus 2 is means for measuring electrical characteristics of the semiconductor device 1 and performing various settings based on the measurement results. That is, the test apparatus 2 is a means for testing the semiconductor device 1 using a probe test or a test board of the semiconductor device 1. The test apparatus 2 switches the operation mode of the semiconductor device 1 by giving a memory control signal to the semiconductor device 1. Specifically, the test apparatus 2 causes the semiconductor device 1 to transition to the test mode with a memory control signal.

  The test device 2 changes the semiconductor device 1 to the test mode, selects and determines the reference bit line of the semiconductor device 1, and sets the selected reference bit line in the semiconductor device 1. Although details will be described later, the selection / determination of the reference bit line by the test apparatus 2 is roughly as follows. First, data “0” and “1” are written in advance for each of the plurality of spare bit lines (reference cell group). Thereafter, for each of the plurality of spare bit lines, the characteristics of the memory cell selected by each spare bit line are measured. Thereafter, the characteristics of the memory cell selected by each spare bit line are evaluated, and a spare bit line (reference cell) that can be used as a reference bit line is selected. Thereafter, the test apparatus 2 sets the selected reference bit line in the semiconductor device 1. When reading data, the test apparatus 2 uses a reference voltage obtained from a memory cell (reference cell) selected from the determined reference bit line. When the user uses the semiconductor device 1 (during normal operation of the semiconductor device 1), the controller that controls the semiconductor device 1 can use the reference voltage obtained in the above-described test. Data can be read from the semiconductor device 1 using the voltage.

  Therefore, the test apparatus 2 can read data from the semiconductor device 1 using the read circuit 42 shown in FIG. 1 and the like, and extracts an optimal reference cell from the reference cell group based on the read data (FIG. 15). Details).

  The internal configuration of the test apparatus 2 will be described below.

  The test apparatus 2 includes a control unit 10, a data control unit 11, a memory device control unit 12, and a VR voltage generation unit 13.

  The control unit 10 is a unit that controls each unit of the data control unit 11, the memory device control unit 12, and the VR voltage generation unit 13, and the entire test apparatus 2. The controller 10 evaluates the characteristics of the spare bit lines included in the semiconductor device 1 and determines the final reference bit line by giving a memory control signal and a variable reference voltage VR described later to the semiconductor device 1. .

  The data control unit 11 is a unit that supplies the semiconductor device 1 with a data signal necessary for selecting a reference bit line and receives a data signal output from the semiconductor device 1. The memory device control unit 12 controls the operation of the semiconductor device 1 by supplying a memory control signal (for example, a write enable signal / WE) to the semiconductor device 1. The VR voltage generation unit 13 supplies the variable reference voltage VR to the semiconductor device 1. Note that the VR voltage generation unit 13 changes the voltage value of the variable reference voltage VR supplied to the semiconductor device 1 in accordance with an instruction from the control unit 10. The variable reference voltage VR is used when determining the quality of the memory cell.

  FIG. 3 is a diagram illustrating an example of the overall configuration of the semiconductor device 1.

  The semiconductor device 1 shown in FIG. 3 includes a memory cell array (20a to 20h) using an STT-RAM that performs spin injection magnetization reversal writing as a resistance change type memory cell. As described above, the semiconductor device 1 includes a plurality of memory cell arrays, and each memory cell array includes a plurality of resistance change memory cells. The memory cell array may be composed of a plurality of banks (20a to 20h). Each bank may be controlled by an access operation independent of each other. One memory cell includes a magnetoresistive element and a selection transistor (for example, a MOS transistor).

  The semiconductor device 1 includes external clock terminals CK and / CK, a clock enable terminal CKE, command terminals / CS, / RAS, / CAS, / WE, data input / output terminals DQ, power input terminals VDD, VSS, external (external terminals). For example, a variable reference voltage input terminal VR to which a variable voltage is supplied from the test apparatus 2) is provided. In the present specification, a signal having “/” at the beginning of a signal name means an inverted signal of the corresponding signal or a low active signal. Therefore, CK and / CK are complementary signals.

  The clock generation circuit 21 receives external clock signals CK and / CK and a clock enable signal CKE. The clock generation circuit 21 generates an internal clock signal required inside the semiconductor device 1 and supplies it to each unit.

  Command terminals / CS, / RAS, / CAS and / WE receive chip select signal / CS, row address strobe signal / RAS, column address strobe signal / CAS and write enable signal / WE, respectively. These command signals are supplied to the command decoder 22. The command decoder 22 decodes the input command signal and supplies it to the chip control circuit 23.

  The mode register 24 is an area where the operation mode of the semiconductor device 1 is set. This area is not limited to the register, and may be configured by memory elements such as a memory cell, a CAM (Content Addressed Memory), a fuse, and an antifuse. The chip control circuit 23 inputs the decoding result of the command signal by the command decoder 22 and the operation mode set in the mode register 24. The chip control circuit 23 generates various internal control signals based on these pieces of information, and array control circuit 25, RW (read / write) amplifier 26, latch circuit 27, data input / output buffer 28, column address buffer 29, bank And supplied to the row address buffer 30.

  Further, the chip control circuit 23 generates a control signal necessary for accessing the memory cell and a control signal necessary for selection / determination of the reference bit line by the test apparatus 2 and supplies the control signal to a circuit for controlling the memory cell array. To do. The chip control circuit 23 generates a reference data write signal RF and reference voltage selection signals RL and RR. These control signals will be described sequentially.

  The address signal ADD includes a bank address that specifies a bank, a row address that specifies a word line, and a column address that specifies a bit line. Of the address signal ADD, the bank and row address are supplied to the bank and row address buffer 30, and the column address is supplied to the column address buffer 29. That is, the column address buffer 29 and the bank / row address buffer 30 are address circuits to which address information is supplied.

  The bank and row address buffer 30 specifies one of the banks 0 to 7 and outputs a row address. The row address output from the bank and row address buffer 30 is decoded by the row decoder 31, and one of the word lines is selected according to the decoding result.

  The column address output from the column address buffer 29 is decoded by the column decoder 32, and a bit line corresponding to the column address is selected according to the decoding result. A data latch circuit (not shown) in the memory cell array corresponding to the selected bit line is connected to an RW (read / write) amplifier 26 via a plurality of I / O (Input / Output) lines 33.

  The RW amplifier 26 is a read amplifier circuit and a write amplifier circuit that are connected to a data input / output terminal DQ, which is an external terminal, via a latch circuit 27 and a data input / output buffer 28. Here, the internal clock signal is supplied from the clock generation circuit 21 to the latch circuit 27 and the data input / output buffer 28, and the input / output timing of data between the memory cell array and the data input / output terminal DQ is controlled.

  The internal voltage generation circuit 34 receives the voltages VDD and VSS and generates an internal voltage to be supplied to each part including the chip control circuit 23.

  The control information storage area 35 is an area accessible by the chip control circuit 23, and includes a first storage area for storing defective address information and a second storage area for storing reference address information. The defect address information is address information indicating the position of the memory cell where the defect exists. Reference address information is address information indicating the position of a reference bit line (reference cell). In FIG. 3, the control information storage area 35 is illustrated as an area different from the memory cell array (20a to 20h), but this area 35 may be configured as an area in the memory cell array (20a to 20h). The control information storage area 35 may be configured by storage elements such as memory cells (particularly nonvolatile memory such as flash memory and STT-RAM memory), CAM (Content Addressed Memory), fuses, and antifuses.

  The variable reference voltage VR supplied from the test apparatus 2 is supplied to a circuit that controls the memory cell array. Details of the circuit using the variable reference voltage VR will be described later. Since the variable reference voltage VR is unnecessary when the semiconductor device 1 is in normal operation, the variable reference voltage input terminal VR is configured not to be in a floating state. For example, a measure such as connecting a pull-down resistor having a high resistance that does not affect the voltage accuracy of the variable reference voltage VR supplied to the circuit that controls the memory cell array is taken.

  FIG. 4 is a diagram showing an example of the configuration of main parts of the memory cell array and its peripheral control circuit of the semiconductor device 1.

  Memory cell regions 40-1 to 40-4 correspond to the memory cell array (for example, 20a) shown in FIG.

  Row decoders (RD) 31-1 and 31-2 correspond to the row decoder 31 shown in FIG.

  Column selectors (CS) 41-1 to 41-4 and column decoders (CD; Column Decoder) 32-1 and 32-2 correspond to the column decoder 32 shown in FIG.

  Further, the configuration shown in FIG. 4 is included in the semiconductor device 1 of FIG. 3, but the following configurations not shown in FIG. 3, ie, read circuits (RC) 42-1 and 42-2, , First write circuit (WC1; Write Circuit 1) 43-1 and 43-2, second write circuit (WC2; Write Circuit 2) 44-1 and 44-2, and switches (SW) 45-1 and 45-2. -2 and voltage clamp transistors 46-1 to 46-4 which are N-channel MOS transistors. In the following description, when there is no special reason for distinguishing the memory cell regions 40-1 to 40-4, they are denoted as “memory cell array 40”. The same notation is used for the column selector, column decoder, row decoder, read circuit, first and second write circuits, switch, and voltage clamp transistor.

  Each of the memory cell regions 40-1 to 40-4 includes m word lines, sr spare word lines, n bit lines, and sc spare bit lines. m, sr, n, and sc are each positive integers, and the same applies in the following description. Memory cells are arranged at the intersections of the word lines (including spare word lines) and bit lines (including spare bit lines). That is, the semiconductor device 1 includes a memory cell group including a plurality of resistance change memory cells arranged in a matrix at intersections of a plurality of word lines and a plurality of bit lines.

  The column selector 41 is controlled by the column decoder 32, and selects one bit line from n + sc bit lines. The row decoder 31 selects one word line from m + sr word lines and connects the corresponding memory cell to the bit line. The column selector 41 connects the memory cell located at the intersection of the selected bit line and word line and the read circuit 42 via a voltage clamp transistor 46 to which the clamp voltage VC is supplied. The clamp voltage VC is a signal supplied by the array control circuit 25 when reading data from the memory cell array. In this way, the row decoder 31 or the column decoder 32 circuit one memory cell among a plurality of memory cells in accordance with the address information supplied to the address circuit (column address buffer 29 or bank and row address buffer 30). A function of connecting to a node (nodes A01 to A04 shown in FIG. 4) is provided.

<Read operation>
When the left two memory cell arrays 40-1 or 40-2 are selected in the read operation (data read operation) of the semiconductor device 1, the left node (node A01 or A02 in FIG. 4) of the read circuit 42 is selected. ) Is input with a read signal voltage corresponding to data held in the memory cell selected by the row decoder 31-1 and the column decoder 32-1.

  On the other hand, the right-side node (node A03 in FIG. 4) of the read circuit 42-1 is connected to the reference bit line included in the upper right memory cell array 40-3 selected by the row decoder 31-2 and the column decoder 32-2. A read signal voltage corresponding to data “0” held in the connected memory cell is input. Further, the read signal voltage corresponding to the data “1” held in the memory cell connected to the reference bit line included in the lower right memory cell array 40-4 is input to the right input node of the read circuit 42-2 (FIG. 4). Node A04) shown in FIG.

  The signal voltages read from the memory cells connected to these reference bit lines are short-circuited (short-circuited) by the switch 45-2 selected by the connection signal SR. As a result, an almost intermediate voltage between the read signal voltages of the data “0” and “1” is input to the read circuit 42 as the reference voltage (the reference voltage is applied to the nodes A03 and A04).

  The read circuit 42 compares and amplifies the read signal voltage from the memory cell included in the left memory cell array 40-1 or 40-2 and the reference voltage obtained from the right memory cell arrays 40-3 and 40-3. And output to the input / output lines IO0 and IO1, respectively. As described above, the read circuit 42 uses the intermediate voltage of the signal read from the reference cell as the reference voltage when determining the data of the signal voltage read from the memory cell selected by the row decoder 31 and the column decoder 32.

  The above description is the operation when the left memory cell array 40-1 or 40-2 is selected.

  When the right memory cell array 40-3 or 40-4 is selected, the left-right relationship is reversed and the vertical relationship of the data held in the memory cells connected to the reference bit line is reversed. More specifically, the read signal voltage corresponding to the data “0” is obtained from the memory cell connected to the reference bit line included in the memory cell array 40-2 in the lower left. Further, a read signal voltage corresponding to the data “1” is obtained from the memory cells connected to the reference bit line included in the upper left memory cell array 40-1.

  Further, when the right memory cell array 40-3 or 40-4 is selected, the switch 45-1 selected by the connection signal SL shorts the nodes A01 and A02. The connection signals SR and SL are signals that the array control circuit 25 controls activation / deactivation as appropriate according to the position of the memory cell array from which data is to be read when reading data from the memory cell array. .

<Write operation>
In the write operation (data write operation) of the semiconductor device 1, when the left memory cell array 40-1 or 40-2 is selected, the first write circuit 43-2 and the second write circuit 44 by the write control signal WL. −1 is activated, and data “0” or “1” is written into the memory cell selected by the row decoder 31-1 and the column decoder 32-1, according to the data input from the input / output lines IO0 and IO1.

  The above description is the operation when the left memory cell array 40-1 or 40-2 is selected.

  When the right memory cell array 40-3 or 40-4 is selected, the left-right relationship is reversed. More specifically, when the right memory cell array 40-3 or 40-4 is selected, the first write circuit 43-1 and the second write circuit 44-2 are activated by the write control signal WR, Data “0” or “1” is written into the memory cell selected by the row decoder 31-2 and the column decoder 32-2 in accordance with the data input from the input / output lines IO0 and IO1.

  The write control signals WL and WR are signals for controlling activation / deactivation as appropriate according to the position of the memory cell array to which data is to be written when the data is written into the memory cell array.

<Reference data write operation (during test)>
When the reference data (data “0” or “1”) is written to the left memory cell 40-1 or 40-2, the reference data write signal RF is activated in addition to the write control signal WL. The reference data write signal RF is a signal that the chip control circuit 23 controls activation / deactivation according to an instruction from the test apparatus 2.

  By activating the write control signal WL and the reference data write signal RF, the row decoder 31 stores data “0” in the lower left memory cell array 40-2 and data “1” in the upper left memory cell array 40-1. −1 and the memory cell selected by the column decoder 32-1.

  The above description is the operation when the left memory cell array 40-1 or 40-2 is selected. When the right memory cell array 40-3 or 40-4 is selected, the left-right relationship is reversed and the vertical relationship of the reference data is reversed. More specifically, when the write control signal WR and the reference data write signal RF are activated, the data “0” is transferred to the upper right memory cell array 40-3 and the data “0” is transferred to the lower right memory cell array 40-4. 1 "is written to the memory cells selected by the row decoder 31-2 and the column decoder 32-2.

  Note that the reference data can be written simultaneously (in parallel) to the left and right memory cell arrays. The reference data is written separately in the left memory cell arrays 40-1 and 40-2 and the right memory cell arrays 40-3 and 40-4. Therefore, reference data (data “0” or “1”) in the left and right memory cell arrays is simultaneously compared and amplified by the read circuit 42 and output to the input / output lines IO0 and IO1 to determine whether the reference data has been correctly written. Can be easily confirmed.

  FIG. 5 is a diagram illustrating an example of a circuit configuration of the column selector 41 (CS 41-1, 41-2, 41-3, 41-4) illustrated in FIG.

  The column selector 41 includes n + sc N-channel MOS transistors whose gates receive n + sc column selection signals. The column decoder 32 selects one of n + sc bit lines by switching the column selection signal. In order to avoid a voltage drop due to the threshold voltage Vt of the N-channel MOS transistor, the column selection line may be made complementary and a CMOS (Complementary Metal Oxide Semiconductor) transistor configuration may be used.

  FIG. 6 is a diagram showing an example of the circuit configuration of the column decoder 32 (CD32-1, 32-2) shown in FIG.

  The column decoder 32 includes n negative AND circuits (NAND), n + 2sc inverter circuits (INV), address comparison circuits 50-1 and 50-2, selection circuits 51-1 to 50-3, Selectors 52-1 to 52-3. The configuration shown in FIG. 6 is a configuration in which the number of spare bit lines is three (sc = 3), but the number of selection circuits and selectors is increased or decreased according to the increase or decrease of spare bit lines.

  The column decoder 32 has a function of replacing a defective bit line by using sc spare bit lines and a function of using a selected one of the sc spare bit lines as a reference bit line. Prepare.

<Defect replacement>
A case where a spare bit line is replaced with a defective bit line will be described. In this case, the column decoder 32 replaces the selected bit line with a spare bit line when the address of the selected bit line matches the address (defective address) programmed in the address comparison circuits 50-1 and 50-2. The defect address information is stored in the control information storage area 35 (first storage area) in the chip. Based on this stored information, the bit line to be replaced is selected.

<Reference bit line settings>
A spare area defined by sr or sc is used as an area (reference cell) for generating a reference voltage used for a read operation in addition to being used as the defect replacement destination. Here, address information (reference cell address) for designating the reference cell is acquired in the test process, and this information is stored in the control information storage area 35 (second storage area) in the chip. Based on this stored information, a reference cell is selected (that is, one of the selection circuits 51-1 to 51-3 is designated for selecting a reference cell, and the rest is designated for selecting a spare bit line).

  When one selected from the spare bit lines is used as a reference bit line, any of the selection circuits 51-1 to 51-3 corresponding to the spare bit line used as the reference bit line among the plurality of spare bit lines. Is selected by the reference cell address stored in the control information storage area 35 in the chip. For example, when the spare bit line shown in FIG. 6 that is connected to the selector 52-1 is used as the reference bit line, the selector 52-1 activates the reference timing signal FL or FR. In response to this, the selection circuit 51-1 is programmed to select the spare bit line.

  When the data is read from the memory cell array, the reference timing signal FL or FR is activated or deactivated appropriately according to the position of the memory cell array including the spare bit line used as the reference bit line by the array control circuit 25. It is a signal to control. More specifically, when the reference voltage is obtained from the memory cell connected to the spare bit line included in the left memory cell array 40-1 or 40-2, the reference timing signal FL is activated. On the other hand, when the reference voltage is obtained from the memory cell connected to the spare bit line included in the right memory cell array 40-3 or 40-4, the reference timing signal FR is activated. Spare bit lines that are not used as reference bit lines are associated with the address comparison circuits 50-1 and 50-2 on a one-to-one basis.

  The circuit configuration shown in FIG. 6 can also be applied to the row decoder 31 shown in FIG. 3 (31-1 and 31-2 in FIG. 4), and the basic circuit configuration is the same as each other. That is, the row decoder 31 is configured to accommodate m address signals, not n address signals, and is configured to accommodate sr spare word lines, not sc spare bit lines. Composed.

  As described above, the row decoder 31 and the column decoder 32 are provided with the address information supplied to the address circuit (column address buffer 29 or bank and row address buffer 30) and the address of the defective data line (bit line or word line). An address comparison circuit for comparing information is provided. In addition, the row decoder 31 and the column decoder 32 use a spare word line (spare word line) prepared in advance as a word line for repairing a defective word line in accordance with a control signal (reference timing signal FL or FR). Whether a reference cell is used as a word line to which a reference cell is connected, and a spare data line prepared in advance (spare bit line) is used as a data line for repairing a defective data line. A circuit for switching whether to use as a connected data line is provided. Details of these switching results will be described later.

  FIG. 7 is a diagram illustrating an example of a circuit configuration of the first write circuit 43 (WC 143-1 and 43-2 in FIG. 4) and the second write circuit 44 (WC 244-1 and 44-2 in FIG. 4).

  Each of the first write circuit 43 and the second write circuit 44 includes two inverter circuits (INV), one tri-state inverter circuit (TS_INV), and three NAND circuits (NAND). Is done. There is no difference in the basic circuit configuration of the first write circuit 43 and the second write circuit 44.

  The difference between the first write circuit 43 and the second write circuit 44 is that the reference data written to the memory cell is different. More specifically, the first write circuit 43 applies the voltage VSS to the input node of the NAND circuit in order to write the data “0”. On the other hand, the second write circuit 44 inputs the voltage VDD to the input node of the NAND circuit in order to write the data “1”.

  In FIG. 7, when the write control signal WL is in the selected high level and the reference data write signal RF is in the inactive low level, the first write circuit 43-2 and the second write circuit 44-1 are turned on. Data according to the voltages of the output lines IO0 and IO1 is output to the memory cell array 40-1 or 40-2.

  On the other hand, when the write control signal WL is in the selected high level and the reference data write signal RF is in the active high level, the first write circuit 43-2 outputs the low level data corresponding to the reference data “0”. Is output to the memory cell array 40-2. At this time, the second write circuit 44-1 outputs high-level data corresponding to the reference data “1” to the memory cell array 40-1. Note that when the data according to the voltages of the input / output lines IO0 and IO1 or the reference data is written to the right memory cell arrays 40-3 and 40-4, the write control signal WR becomes the high level of the selected state.

  FIG. 8 is a diagram illustrating an example of a circuit configuration of the switch 45 (SWs 45-1 and 45-2 in FIG. 4).

  FIG. 8A shows a circuit configuration of the switch 45-1, and FIG. 8B shows a circuit configuration of the switch 45-2. Each of the switches 45-1 and 45-2 includes an inverter circuit (INV) and a transfer gate (TG). The switch 45-1 is a switch circuit connected between the node A01 and the node A02. The switch 45-2 is a switch circuit connected between the node A03 and the node A04.

  The switch 45-1 connects both ends of the transfer gate when the connection signal SL becomes high level. Similarly, the switch 45-2 connects both ends of the transfer gate when the connection signal SR becomes high level.

  Here, RC42-1 and 42-2 shown in FIG. 4 will be described in detail with reference to FIG.

  The readout circuit 42 shown in FIG. 1 includes P-channel MOS transistors 60-1 to 60-3, N-channel MOS transistors 61-1 and 61-2, a constant current source 62, and inverter circuits 63-1 and 63. -2, transfer gates 64-1 to 64-4, and a sense amplifier 65.

  The sources (first main electrodes) of the P-channel MOS transistors 60-1 to 60-3 are connected to the voltage VDD. The gates (control electrodes) of the P-channel MOS transistors 60-1 and 60-2 are connected in common and also connected to the drain (second main electrode) of the P-channel MOS transistor 60-2. Similarly, the gates of P-channel MOS transistors 60-1 and 60-3 are connected to each other and to the drain of P-channel MOS transistor 60-2. Two current mirror circuits are formed by the P-channel MOS transistors 60-1 to 60-3. That is, the current flowing through the P-channel MOS transistor 60-2 is duplicated and flows from the P-channel MOS transistors 60-1 and 60-3.

  The sources of the N-channel MOS transistors 61-1 and 61-2 are connected to the voltage VSS. The gates of N-channel MOS transistors 61-1 and 61-2 are connected in common and also connected to the drain of N-channel MOS transistor 61-2. A current mirror circuit is formed by the N-channel MOS transistors 61-1 and 61-2.

  The drain of P-channel MOS transistor 60-2 and the drain of N-channel MOS transistor 61-1 are connected. The drain of the N-channel MOS transistor 61-2 is connected to one end of the constant current source 62, and the other end of the constant current source 62 is connected to the voltage VDD. The constant current source 62 supplies the read current Iread to the N channel type MOS transistor 61-2. The read current Iread is supplied to the memory cell array via the left and right nodes (A01 / A02 or A03 / A04) by a current mirror circuit composed of a P-channel MOS transistor and an N-channel MOS transistor. Thus, the read circuit 42 includes a current mirror circuit that supplies a current mirror current to each of two circuit nodes (nodes A01 and A03 or nodes A02 and A04 shown in FIG. 4).

  As described above, the current mirror circuit included in the readout circuit 42 includes the P-channel MOS transistors 60-1 to 60-3 and the N-channel MOS transistors 61-1 and 61-2. . The P-channel MOS transistor 60-1 is connected between the power supply VDD and the circuit node (node A01 or A02) and has a first control electrode. The P-channel MOS transistor 60-2 is connected between the power supply VDD and the first internal node (a connection node between the P-channel MOS transistor 60-2 and the N-channel MOS transistor 61-1). The first control electrode 60-1 and the second control electrode connected to the first internal node described above are included. The P-channel MOS transistor 60-3 is connected between the power supply VDD and the circuit node (node A03 or A04), and has a third control electrode connected to the first internal node described above. The N-channel MOS transistor 61-1 is connected between the ground VSS and the first internal node described above, and has a fourth control electrode. The N-channel MOS transistor 61-2 is connected between the power supply VDD and the ground VSS, and is connected to the fourth control electrode and the second internal node (the constant current source 62 and the N-channel MOS transistor of the N-channel MOS transistor 61-1). And a fifth control electrode connected to the connection node 61-2.

  The drain of P-channel MOS transistor 60-1 is connected to the input terminal of transfer gate 64-1. The other input terminal of the transfer gate 64-1 is connected to the input terminal of the transfer gate 64-2, and is also connected to the non-inverting input terminal of the sense amplifier 65. The other input terminal of the transfer gate 64-2 receives the variable reference voltage VR. The inverter circuit 63-1 inverts the reference voltage selection signal RL and outputs the inverted signal to the gate of the N-channel MOS transistor of the transfer gate 64-1. The inverter circuit 63-1 inverts the reference voltage selection signal RL and outputs the inverted signal to the gate of the P-channel MOS transistor of the transfer gate 64-2. The gate of the P-channel MOS transistor of the transfer gate 64-1 and the gate of the N-channel MOS transistor of the transfer gate 64-2 receive the reference voltage selection signal RL.

  Similarly, the drain of the P-channel MOS transistor 60-3 is connected to the input terminal of the transfer gate 64-4. The other input terminal of the transfer gate 64-4 is connected to the input terminal of the transfer gate 64-3, and is connected to the inverting input terminal of the sense amplifier 65. The other input terminal of the transfer gate 64-3 receives the variable reference voltage VR. The inverter circuit 63-2 inverts the reference voltage selection signal RR and outputs it to the gate of the N-channel MOS transistor of the transfer gate 64-4. The inverter circuit 63-2 inverts the reference voltage selection signal RL and outputs the inverted signal to the gate of the P-channel MOS transistor of the transfer gate 64-3. The gate of the P-channel MOS transistor of the transfer gate 64-4 and the gate of the N-channel MOS transistor of the transfer gate 64-3 accept the reference voltage selection signal RR. The P-channel MOS transistor is a typical example of the first conductivity type transistor, and the N-channel MOS transistor is a typical example of the second conductivity type transistor.

  The reference voltage selection signals RL and RR are signals that the chip control circuit 23 appropriately controls when selecting a reference bit line.

  The sense amplifier 65 is a circuit that compares and amplifies voltages input to two input terminals (a non-inverting input terminal and an inverting input terminal) and outputs the amplified voltage to the input / output line IO0 or IO1.

  When the read current Iread supplied from the constant current source 62 is supplied to the memory cell array (the memory cell array to be read and the memory cell array that generates the reference voltage) via the voltage clamp transistor shown in FIG. Due to the current-voltage conversion action, the read signal voltage and the reference voltage corresponding to the resistance value of the memory cell appear at the input terminals (node A01 / A02 and node A03 / A04) of the read circuit 42.

<Circuit Operation of Read Circuit 42 during Normal Operation (Data Read)>
Here, in the normal read operation, the reference voltage selection signals RL and RR are both controlled to a non-selected (inactive state) low level. Therefore, transfer gates 64-1 and 64-4 are turned on, and transfer gates 64-2 and 64-3 are turned off. As a result, the read signal voltage and the reference voltage are supplied to the differential amplification type sense amplifier 65, and are compared and amplified by the sense amplifier 65, and read data is output from the input / output lines IO0 and IO1.

<Circuit Operation of the Read Circuit 42 at the Test (At the Cell Characteristic Test)>
When evaluating the characteristics of the memory cells, for example, when evaluating the characteristics of the memory cells included in the left memory cell array 40-1, the reference voltage selection signal RR is controlled to the high level of the selected state (active state). The Therefore, transfer gates 64-1 and 64-3 are turned on, and transfer gates 64-2 and 64-4 are turned off. Then, the read signal voltage is input to the non-inverting input terminal of the sense amplifier 65 and the variable reference voltage VR is input to the inverting input terminal, and the read signal voltage and the variable reference voltage VR are compared. That is, the read signal voltage can be measured by changing the variable reference voltage VR and observing the state changes of the input / output lines IO0 and IO1. When evaluating the characteristics of the memory cells included in the right memory cell array 40-3, the reference voltage selection signal RL is controlled to the high level of the selected state, and the read signal voltage is measured.

  As described above, the read circuit 42 connects one of the variable reference voltage input terminal VR and the circuit node (node A01 or A02 shown in FIG. 4) to the sense amplifier 65 according to the reference voltage selection signal RL (first region signal). A first selection circuit (a circuit composed of an inverter circuit 63-1, transfer gates 64-1 and 64-2) connected to a first input terminal (non-inverting input terminal) is provided. In addition, the read circuit 42 uses one of the variable reference voltage input terminal VR and the circuit node (node A03 or A04 shown in FIG. 4) as the second of the sense amplifier 65 in accordance with the reference voltage selection signal RR (second region signal). A second selection circuit (a circuit composed of an inverter circuit 63-2 and transfer gates 64-3 and 64-4) connected to an input terminal (inverting input terminal) is provided.

  FIG. 9 is a diagram showing an example of the signal voltage obtained from the memory cell and its frequency distribution.

  In FIG. 9, the horizontal axis indicates the signal voltage, and the vertical axis indicates the frequency of the measured memory cell. The graph shown in FIG. 9 shows the frequency distribution of the read signal voltage obtained from the memory cell (low resistance state) whose leftmost graph corresponds to data “0”. The rightmost graph shows the frequency distribution of the read signal voltage obtained from the memory cell (high resistance state) corresponding to the data “1”.

  The graph shown in the center of FIG. 9 shows the frequency distribution of the reference voltage. Regarding generation of a reference resistance value (reference voltage), for example, (1) an example of using a memory cell A that shows a resistance value intermediate between a low resistance value (ideal value) and a high resistance value (ideal value) indicated by a normal memory cell Further, (2) an example in which an intermediate resistance value is generated from a low resistance state memory cell B exhibiting a low resistance value and a high resistance state memory cell C exhibiting a high resistance value, and (3) a low resistance value is represented. An example in which an intermediate resistance value is generated from one of the low-resistance state memory cell B or the high-resistance state memory cell C that exhibits a high resistance value and a resistance element that is not a memory cell is conceivable.

  In any of the above examples (1) to (3), it is necessary to prepare a plurality of memory cells used for generating the reference voltage, thereby obtaining the frequency distribution of the reference voltage shown in the center of FIG. As described here, it is necessary to extract an optimum reference cell.

  In any of the above examples (1) to (3), the reference voltage is positioned between the upper limit of the distribution of data “0” and the lower limit of the distribution of data “1”. It is ideal to do. Therefore, the lower limit value and the upper limit value define a range that can be allowed as a reference voltage with a certain margin around the midpoint between the upper limit of the distribution of data “0” and the lower limit of the distribution of data “1”. To do. Referring to FIG. 9, X1 is set as the lower limit value and X2 is set as the upper limit value.

  In selecting a reference bit line, the test apparatus 2 selects and determines a spare bit line in which the characteristics of the memory cell fall between the lower limit value X1 and the upper limit value X2 as the reference bit line. More specifically, a spare bit line corresponding to the distribution of the waveform 100 among the three graphs shown in FIG. 9 is selected as a reference bit line. In other words, spare bit lines corresponding to the graphs located on the left and right of the waveform 100 are not selected as reference bit lines.

  In particular, in the case of (2) above (when a reference voltage is generated from a reference cell of 0 information storage and a reference cell of 1 information storage), considering the decoding configuration for each memory area shown in FIG. Two cells of the line should be paired. This is because two bit lines are selected and one word line is activated, and two memory cells (for example, one of the SC areas of 40-1 and one of the SC areas of 40-2). This is because one is selectable.

<Test flowchart>
FIG. 10 is a flowchart showing an example of operations of the semiconductor device 1 and the test device 2. In this flow, an optimum reference cell is extracted from the reference cell group.

  When the reference bit line is selected in step S01, the test apparatus 2 previously stores reference data (data “0” or “1”) in the memory cells connected to the spare bit line included in the semiconductor device 1. Write. For example, in FIG. 4, among the sc spare bit lines, the spare bit lines included in the upper left memory cell array 40-1 and the spare bit lines included in the lower left memory cell array 40-2 are changed to the column decoder 32-1. Use to select simultaneously. In this state, when the write control signal WL and the reference data write signal RF are activated, data “1” is stored in the memory cell connected to the spare bit line included in the upper left memory cell array 40-1. Writing is performed by the writing circuit 44-1. Similarly, data “0” is written into the memory cell connected to the spare bit line included in the lower left memory cell array 40-2 by the first write circuit 43-2.

  In step S02, the test apparatus 2 measures the characteristics of the memory cell in which the reference data is written. That is, data is read from a plurality of memory cells connected to the spare bit line and / or spare word line, and the resistance value is measured. Details will be described in detail with reference to FIG.

  When the measurement of the characteristics of the memory cell in which the reference data is written is completed in step S03, it is determined whether or not each spare bit line can be adopted as a reference bit line. That is, the test apparatus 2 evaluates the characteristics of the spare bit line, and extracts those that can be used as reference bit lines (extracts a memory cell having an optimum resistance value as a reference cell). The test apparatus 2 determines the extracted spare bit line as a reference bit line.

  Thus, in this step, a process of extracting a plurality of reference cells (a plurality of memory cells connected to the reference bit line) from the memory cell group is executed. Address information indicating the position of the extracted reference bit line (reference cell) is stored in the second storage area of the control information storage area 35. As a result, the memory cell having the optimum reference resistance value can be used as the reference cell.

  In step S04, if necessary, the test apparatus 2 performs redundant repair of the bit line using the spare bit line that is not used as the reference bit line.

  In this step, if there is at least one defective memory cell in a memory cell group other than the extracted reference cell group (that is, a plurality of memory cells connected to a bit line not selected as a reference bit line), The data line is switched to replace such a defective memory cell with a memory cell other than the defective memory cell in the extracted reference cell group. Address information indicating the position of the defective memory cell is stored in the first storage area of the control information storage area 35. As a result, cells other than the extracted reference bit line (reference cell) can be used as redundant replacement destination memory cells.

  In the STT-RAM device, due to the characteristics of the memory cell, as described above, a memory cell that exhibits optimum characteristics (good in manufacturing process) is selected as a reference cell from a plurality of reference cell candidates. It is useful to determine. In this case, the remaining cells do not exhibit the optimum characteristics, but can be used for storing normal data if the characteristics are not so bad as to be defective cells. Therefore, by performing the above steps, a part of the spare area is used as a reference cell, and the other part is used as a redundant replacement destination.

  FIG. 11 is a flowchart illustrating an example of an operation related to selection / determination of the reference bit line by the test apparatus 2. Here, steps S02 and S03 in FIG. 10 will be described in detail.

  In step S101, the test apparatus 2 selects one spare bit line from the sc spare bit lines. Specifically, in FIG. 4, among the sc spare bit lines, one spare bit line included in the upper left memory cell array 40-1 and one spare bit line included in the lower left memory cell array 40-2. Are simultaneously selected as a spare bit line pair using the column decoder 32-1.

  In step S102, the test apparatus 2 sets the variable reference voltage VR to an initial value XL0 defined between the intermediate value between the lower limit value X1 and the upper limit value X2 and the lower limit value X1 shown in FIG.

  In step S103, all the memory cell pairs connected to the one pair of spare bit lines selected in step S101 are sequentially selected by the method described above, and the reference voltage obtained from the memory cell pair and the variable reference voltage VR are selected. And compare.

  In step S104, it is determined whether there is a memory cell pair whose reference voltage is lower than the variable reference voltage VR. In the case of Yes branch, the process proceeds to step S105. In the case of No branch, the process proceeds to step S106.

  If there is a memory cell pair whose reference voltage is lower than the variable reference voltage VR in step S105, the test apparatus 2 decreases the variable reference voltage VR by a predetermined width, and repeats the processing from step S103.

  In step S106, when the reference voltages of all memory cell pairs become higher than the variable reference voltage VR, the test apparatus 2 stores the variable reference voltage VR at that time.

  In step S107, the test apparatus 2 sets the variable reference voltage VR to an initial value XU0 determined between the intermediate value between the lower limit value X1 and the upper limit value X2 and the upper limit value X2 shown in FIG.

  In step S108, all the memory cell pairs connected to the pair of spare bit line pairs selected in step S101 are sequentially selected by the method described above, and the reference voltage obtained from the memory cell pair and the variable reference voltage VR are selected. And compare.

  In step S109, it is determined whether there is a memory cell pair whose reference voltage is higher than the variable reference voltage VR. In the case of Yes branch, the test apparatus 2 increases the variable reference voltage VR by a predetermined width (step S110), and repeats the processing from step S108.

  In the case of step S109, No branch, when the reference voltages of all memory cell pairs become lower than the variable reference voltage VR, the test apparatus 2 stores the variable reference voltage VR at that time (step S111).

In step S101, it is determined whether or not the selected spare bit line pair can be selected as a reference bit line pair. More specifically, it is determined whether the spare bit line can be selected as the reference bit line by making a determination according to the following narrowing conditions.
Narrowing conditions:
The variable reference voltage VR stored in step S106 is not less than the lower limit value X1, and
The variable reference voltage VR stored in step S111 is not more than the upper limit value X2.

  In step S112, the test apparatus 2 performs determination according to the narrowing-down condition for the spare bit line pair selected in step S101.

  If the narrow-down condition is not satisfied in step S112, No branch, the test apparatus 2 selects the next spare bit line (step S113), and repeats the processing from step S102 onward.

  If the narrow-down condition is satisfied in Step S112, Yes branch, the test apparatus 2 selects the selected spare bit line pair as the reference bit line pair (Step S114).

  FIG. 12 is a diagram illustrating an example of the reference bit line pair selection result according to the present embodiment. In the following description, among the memory cells included in the memory cell array, the reference cell is represented by a black circle. FIG. 12 shows a reference bit line pair obtained according to the flowcharts shown in FIGS.

<Reading method after reference bit line selection / setting>
The test apparatus 2 uses the corresponding spare bit line pair as the reference bit line pair for the selection circuit (see FIG. 6) corresponding to the spare bit line pair selected as the reference bit line pair via the chip control circuit 23. Write (program) things. More specifically, one reference bit line pair is selected from the spare bit line pairs included in the left memory cell arrays 40-1 and 40-2, and the corresponding selection circuit selects the reference bit line pair. Next, the selection circuit is programmed. Similarly, one reference bit line pair is selected from the spare bit line pairs included in the right side memory cell arrays 40-3 and 40-4, and selection of the reference bit line pair is set in the corresponding selection circuit.

  During a normal read operation of the semiconductor device 1, a word line at a symmetrical position with respect to the read circuit 42 is selected, and a read signal voltage from the memory cell to be read is input to the read circuit 42. At this time, a reference voltage is input to the read circuit 42 from two memory cells (reference cells) located at the intersection of the selected word line and reference bit line. Thereafter, the read signal voltage input to the read circuit 42 and the reference voltage are compared and amplified, and data is read from the memory cell.

  In such a read method, since the lengths of the bit lines to the selected memory cell as viewed from the read circuit 42 are substantially equal, a decrease in the sense margin due to the resistance difference between the bit lines is suppressed.

  In the present embodiment, the selection / determination of the reference bit line pair has been described. However, the reference word line can be determined by the same method as the selection / determination of the reference bit line pair.

  FIG. 13 is a diagram showing an example of a reference word line selection result according to the present embodiment. The selection of the reference word line may be performed, for example, by replacing the spare bit line pair with a spare word line and the reference bit line pair with a reference word line in the processing shown in FIGS.

  As described above, in a semiconductor device including a resistance change type memory cell, a plurality of spare bit lines and spare word lines are prepared, and based on the result of measuring the read signal of these memory cells, a pair of reference bit lines and One reference word line is selected. The semiconductor device 1 according to the present embodiment extracts a plurality of reference cells (reference cell group) in bit line units or word line units. As a result, the number of spare word lines and spare bit lines is not increased unnecessarily. That is, the utilization efficiency of the substrate area in the semiconductor device 1 is high. Further, the semiconductor device 1 can obtain a reference voltage that is close to ideal from the reference bit line pair and the reference word line, and the operation margin of the semiconductor device is improved. Further, redundancy repair is also realized by replacing a spare bit line or a spare word line that has not been selected as a reference bit line pair or a reference word line with a defective bit line or word line.

  Further, in the technology disclosed in Non-Patent Document 1, there is a degree of freedom in which a better reference cell characteristic can be selected as appropriate, but since there is no means for evaluating the reference cell characteristic in advance, the characteristic is good while performing an actual operation. It is necessary to sequentially select reference cells. Therefore, the technique disclosed in Non-Patent Document 1 has a problem that it takes a long time until an optimal solution is obtained. On the other hand, in the semiconductor device 1 and the test device 2 according to the present embodiment, since the read signal voltage of the memory cell can be measured efficiently, the selection of the reference bit line and the reference word line can be performed in a short time. As a result, the manufacturing cost of the semiconductor device can be reduced.

[Second Embodiment]
A second embodiment will be described in detail with reference to the drawings.

  In the first embodiment, the selection / determination for the reference bit line pair or the reference word line has been described. In the second embodiment, instead of the reference bit line pair or the reference word line, a reference is made. This is an example of selecting and determining a cell pair. One of the objects of the first embodiment and the second embodiment of the present invention is to select a reference cell pair that generates an optimal reference intermediate value. Only the flow of FIG. 11 may be sufficient, only the flow of FIG. 15 may be sufficient, and the flow of FIG. 15 may be performed after performing the flow of FIG.

  Regarding the semiconductor device 1a and the test apparatus 2a according to the second embodiment, there is no difference between the internal configuration and the like of the semiconductor device 1 and the test apparatus 2 according to the first embodiment. Therefore, the description corresponding to FIGS. 1 to 8 is omitted for the semiconductor device 1a and the test device 2a.

  Here, FIG. 14 is a diagram showing an example of the signal voltage obtained from the memory cell and its frequency distribution. In the first embodiment, a reference bit line pair or a reference word line from which a reference voltage corresponding to the waveform 100 is obtained is selected. However, as described above, the reference voltage is ideally located between the upper limit of the distribution of data “0” and the lower limit of the distribution of data “1”.

  However, the reference voltage obtained from the memory cell pair connected to the reference bit line pair may be greatly deviated from the intermediate value depending on the memory cell.

  Therefore, in the second embodiment, the range defined by the lower limit value X1 and the upper limit value X2 is further narrowed, and a memory cell pair with better characteristics is selected as the reference cell pair. The upper limit value and lower limit value shown in FIG. 14 are defined as a lower limit value Y1 and an upper limit value Y2. The lower limit value Y1 and the upper limit value Y2 are set to be narrower than the range defined by the lower limit value X1 and the upper limit value X2 shown in FIG.

  By using the narrower lower limit value Y1 and upper limit value Y2, it is possible to select and determine a reference cell pair that generates an intermediate value with higher accuracy instead of selecting and determining the reference bit line pair or reference word line described above. It becomes possible.

  FIG. 15 is a flowchart illustrating an example of an operation related to selection / determination of a reference cell pair by the test apparatus 2a. The test apparatus 2a may execute the process shown in FIG. 15 after executing the process of step S114 shown in FIG.

  In step S201, the test apparatus 2a selects one set of memory cells from the spare bit line pair selected in the process shown in FIG.

  In step S202, the test apparatus 2a sets the variable reference voltage VR to an initial value YL0 determined between the intermediate value between the lower limit value Y1 and the upper limit value Y2 and the lower limit value Y1 shown in FIG.

  In step S203, the reference voltage obtained from the memory cell pair selected in step S201 is compared with the variable reference voltage VR by the method described above.

  In step S204, Yes branch, that is, when the reference voltage is lower than the variable reference voltage VR, the test apparatus 2a decreases the variable reference voltage VR by a predetermined width (step S205), and repeats the processing from step S203.

  In step S204, No branch, that is, when the reference voltage becomes higher than the variable reference voltage VR, the test apparatus 2a stores the variable reference voltage VR at that time (step S206).

  In step S207, the test apparatus 2a sets the variable reference voltage VR to an initial value Y2 determined between the intermediate value between the lower limit value Y1 and the upper limit value Y2 and the upper limit value Y2 shown in FIG.

  In step S208, the reference voltage obtained from the memory cell pair selected in step S201 is compared with the variable reference voltage VR by the method described above.

  Step S209, Yes branch, that is, if the reference voltage is higher than the variable reference voltage VR, the test apparatus 2a increases the variable reference voltage VR by a predetermined width (step S210), and repeats the processing from step S208.

  Step S209, No branch, that is, when the reference voltage becomes lower than the variable reference voltage VR, the test apparatus 2a stores the variable reference voltage VR at that time (step S211).

In step S212, the test apparatus 2a determines whether or not the memory cell pair selected in step S201 can be selected as a reference cell pair. Specifically, it is determined whether a memory cell pair can be selected as a reference cell pair by making a determination according to the following narrowing conditions.
Narrowing conditions:
The variable reference voltage VR stored in step S206 is not less than the lower limit value Y1, and
The variable reference voltage VR stored in step S211 is equal to or lower than the upper limit value Y2.

  The test apparatus 2a performs determination according to the narrowing-down condition for the memory cell pair selected in step S201 (step S212).

  In step S212, No branch, that is, if the above narrowing condition is not satisfied, the test apparatus 2a selects the next memory cell pair (step S213), and repeats the processing after step S202.

  If step S212, Yes branch, that is, if the above-described narrowing condition is satisfied, the test apparatus 2a selects the selected memory cell pair as the reference cell pair (step S214).

  FIG. 16 is a diagram showing an example of reference cell selection results according to the present embodiment. FIG. 16 shows a reference cell pair obtained according to the flowchart shown in FIG.

  The test apparatus 2a uses the corresponding spare bit line as the reference bit line pair for the selection circuit (see FIG. 6) corresponding to the spare bit line pair selected as the reference bit line pair via the chip control circuit 23. Write (program). Further, the test apparatus 2a uses the chip control circuit 23 to select a spare word line or a normal word corresponding to a spare word line or a normal word line for selecting a memory cell pair determined as a reference cell. Write (program) to use the line to select the reference cell. When a memory cell pair determined as a reference cell is selected by a normal word line, a selector 71 described later with reference to FIG. 17 may be added to the row decoder 31, for example. At this time, when an address corresponding to the word line selected by the selector 31 is selected, the address is programmed into the address comparison circuit (50 in FIG. 6), and the word line is selected so that the spare word line is selected. It may be replaced. As a result, a memory cell having good characteristics can be carefully selected from the memory cells connected to the selected reference bit line and set as a reference cell.

  As described above, the semiconductor device 1a according to the present embodiment selects a set of memory cells from the plurality of spare bit lines and the plurality of spare word lines and uses them as reference cells. That is, the semiconductor device 1a according to the present embodiment extracts a plurality of reference cells (reference cell group) in units of memory cells. Therefore, a reference voltage closer to the ideal value can be obtained. As a result, the operation margin during the data read operation is further improved.

[Third Embodiment]
A third embodiment will be described in detail with reference to the drawings.

  In the third embodiment, a word line and a bit line are not first separated into a normal part and a spare part. In the first embodiment (FIG. 1), the spare area is determined in advance in terms of manufacturing, but in this third embodiment, m + sr word lines and n + sc bit lines are used. Therefore, the column decoder 32a shown in FIG. 17 (third embodiment) is different from the column decoder 32 shown in FIG. 6 (first embodiment). Other configurations are the same as those described in the first embodiment, and a description thereof will be omitted.

  In the memory cell array of the third embodiment, the bit lines and word lines included in the memory cell array 40 are not divided into normal bit lines and normal word lines, spare bit lines and spare word lines in advance. In FIG. 4 of the first embodiment, m and sr are separated and selected in advance, and n and sc are separated and selected in advance. In the third embodiment, the label descriptions of m and sr in FIG. 4 are unified and replaced with m + sr, and the label descriptions of m and sr in FIG. 4 are unified and replaced with n + sc.

  In the column selector 41 of the third embodiment, n + sc bit lines are formed by n + sc N-channel MOS transistors whose gates receive n + sc column selection signals that are not separated into normal bit lines and spare bit lines. One of these is selected. In order to avoid a voltage drop due to the threshold voltage Vt of the N-channel MOS transistor, the column selection line may be complementary and a CMOS transistor may be used. In FIG. 5 of the first embodiment, n and sc are separated and selected in advance. In the third embodiment, the label descriptions of n and sr in FIG. 5 are unified and referred to as n + sc.

  FIG. 17 is a diagram illustrating an example of a circuit configuration of the column decoder 32a. The column decoder 32a includes n + sc negative AND circuits (NAND), n + sc inverter circuits (INV), a shift relief circuit 70, and a selector 71.

  The column decoder 32a shown in FIG. 17 has a function of skipping column selection lines corresponding to bit lines having defects among n + sc bit lines. Specifically, the column decoder 32a skips a bit line having a defect by programming the shift relief circuit 70 to associate the decoder output with the column selection line. In FIG. 17, the bit lines 101 and 103 are skipped.

  The column decoder 32a can use one selected from n + sc bit lines as a reference bit line. Specifically, by programming the selector 71, when the reference timing signal FR is activated, one bit line is selected as the reference bit line. In FIG. 17, the bit line 102 is selected as the reference bit line. FIG. 17 is a diagram showing an example of the circuit configuration of the column decoder 32a, but the basic circuit configuration of the row decoder 31a is the same as that of the column decoder 32a. That is, the row decoder 31a is internally configured so as to be able to deal with m + sr address signals instead of n + sc address signals.

  As described above, the row decoder 31a and the column decoder 32a are defective based on the address information supplied to the address circuit (the column address buffer 29 or the bank and row address buffer 30) and the address information of the defective data line. A shift relief circuit for relieving a certain data line. In addition, the row decoder 31a and the column decoder 32a are connected to a data line (reference bit line or reference word) connected to a reference cell from a data line included in the memory cell array 40 according to a control signal (reference timing signal FL or FR). A circuit for selecting a line).

  In the third embodiment, the reference bit lines obtained according to the flowcharts shown in FIGS. 10 and 11 can be selected and set as shown in FIG.

  The third embodiment is different from the first embodiment in that the range of measuring the characteristics of the memory cell for selecting the reference bit line extends to n + sc bit lines. That is, according to the flowcharts shown in FIGS. 10 and 11, a bit line having a desired characteristic is programmed into the selector 71 and can be selected as described with reference to FIG. Although the reference bit line selection / determination method of the semiconductor device 1b according to the present embodiment increases the time required to select the reference bit line as compared with the semiconductor device 1 according to the first embodiment, There is an advantage that a reference bit line having more characteristics can be selected.

  Note that a reference word line can be selected instead of selecting a reference bit line. Alternatively, a reference cell can be selected as in the second embodiment. In this case, since the number of memory cells that can be selected as reference cells increases, a memory cell with good characteristics in which variation distribution of memory cell characteristics is suppressed can be used as a reference.

  As described above, in the third embodiment, the bit lines and the word lines included in the memory cell array can be distinguished from each other without distinguishing between normal bit lines and word lines and spare bit lines and word lines. Select the reference bit line, reference word line, and reference cell. That is, as the number of options increases, a reference voltage closer to the ideal can be obtained, so that the operation margin during the data read operation is further improved.

[Fourth Embodiment]
Next, a fourth embodiment will be described in detail with reference to the drawings.

  The semiconductor device 1c according to the present embodiment uses a memory cell in which a resistance value approximately in the middle of the resistance values corresponding to the data “0” and the data “1” can be written in the memory cell. Since there is no difference from the semiconductor device 1 in other respects, descriptions corresponding to FIGS. 1 to 3 and FIGS. 5 to 8 regarding the semiconductor device 1c are omitted.

  FIG. 18 is a diagram showing an example of the configuration of the main part of the memory cell array and its peripheral control circuit of the semiconductor device 1c. 18, the same components as those in FIG. 4 are denoted by the same reference numerals, and the description thereof is omitted.

  In the fourth embodiment, since the semiconductor device 1c uses one memory cell as a reference cell, the switch 45 that short-circuits the input terminals of the upper and lower readout circuits 42 is not necessary. Further, it is not necessary to separately write the reference data into data “0” and data “1”, and the circuit configuration of the write circuit 42a is simplified. The specific configuration of the write circuit 42a is selected in accordance with the characteristics of the resistance change type memory cell to be used.

  Each of the embodiments described above may be appropriately applied to a ReRAM (Resistive Random Access Memory) and a phase change memory PRAM (Phase Change Random Access Memory) without departing from the present invention.

  Each disclosure of the cited patent documents and the like cited above is incorporated herein by reference. Within the scope of the entire disclosure (including claims) of the present invention, the embodiments and examples can be changed and adjusted based on the basic technical concept. Various disclosed elements (including each element of each claim, each element of each embodiment or example, each element of each drawing, etc.) within the scope of the claims of the present invention, Selection is possible. That is, the present invention of course includes various variations and modifications that could be made by those skilled in the art according to the entire disclosure including the claims and the technical idea. In particular, with respect to the numerical ranges described in this document, any numerical value or small range included in the range should be construed as being specifically described even if there is no specific description.

DESCRIPTION OF SYMBOLS 1, 1a-1c Semiconductor device 2, 2a Test apparatus 10 Control part 11 Data control part 12 Memory device control part 13 VR voltage generation part 20a-20h, 40, 41-1 to 40-4 Memory cell array 21 Clock generation circuit 22 Command Decoder 23 Chip control circuit 24 Mode register 25 Array control circuit 26 RW (read / write) amplifier 27 Latch circuit 28 Data input / output buffer 29 Column address buffer 30 Bank and row address buffers 31, 31-1, 31-2, 31a, 31a -1, 31a-2 Row decoders 32, 32-1, 32-2, 32a, 32a-1, 32a-2 Column decoder 33 I / O line 34 Internal voltage generation circuit 35 Control information storage areas 41, 41-1 to 41-1 41-4, 41a, 41a-1 to 41a-4 Column selector 4 42-1, 42-2, 42a, 42a-1, 42a-2 Read circuits 43, 43-1, 43-2 First write circuits 44, 44-1, 44-2 Second write circuits 45, 45- 1, 45-2 switches 46, 46-1 to 46-4 voltage clamp transistors 50-1, 50-2 address comparison circuits 51-1 to 51-3 selection circuits 52-1 to 52-3, 71 selector 60-1 -60-3 P-channel MOS transistors 61-1 and 61-2 N-channel MOS transistor 62 Constant current sources 63-1 and 63-2 Inverter circuits 64-1 to 64-4 Transfer gate 65 Sense amplifier 70 Shift relief circuit 100 waveform 101-103 bit line

Claims (12)

A first memory cell array including a plurality of resistance change type first memory cells;
A second memory cell array including a plurality of resistance change type second memory cells;
A first circuit node;
A second circuit node;
An address circuit to which address information is supplied;
A first decoder circuit for connecting one memory cell of the plurality of first memory cells to the first circuit node according to the address information supplied to the address circuit;
A second decoder circuit for connecting one memory cell of the plurality of second memory cells to the second circuit node according to the address information supplied to the address circuit;
A first reference voltage input terminal to which a variable voltage is supplied;
A first sense amplifier circuit including first and second input terminals;
A first current mirror circuit for supplying a first current mirror current to each of the first and second circuit nodes;
A first selection circuit for connecting one of the first reference voltage input terminal and the first circuit node to the first input terminal of the first sense amplifier circuit in response to a first region signal;
A semiconductor device comprising: a second selection circuit that connects one of the first reference voltage input terminal and the second circuit node to the second input terminal of the first sense amplifier circuit according to a second region signal. The first selection circuit connects the first circuit node to the first input terminal of the first sense amplifier circuit according to a first level of the first region signal set during a read operation.
The second selection circuit connects the second circuit node to the second input terminal of the first sense amplifier circuit according to a first level of the second region signal set during the read operation. 1. A semiconductor device. The first selection circuit sets the first circuit node of the first sense amplifier circuit according to the first level of the first region signal set when extracting a reference cell from the first memory cell array. Connect to 1 input terminal,
The second selection circuit sets the first reference voltage input terminal to the first level according to a second level different from the first level of the second region signal set when extracting a reference cell from the first memory cell array. 3. The semiconductor device according to claim 2, wherein the semiconductor device is connected to the second input terminal of one sense amplifier circuit. A third memory cell array including a plurality of resistance change type third memory cells;
A fourth memory cell array including a plurality of resistance change type fourth memory cells;
A third circuit node;
A fourth circuit node;
A third decoder circuit connecting one memory cell of the plurality of third memory cells to the third circuit node according to the address information supplied to the address circuit;
A fourth decoder circuit for connecting one of the plurality of fourth memory cells to the fourth circuit node according to the address information supplied to the address circuit;
A second reference voltage input terminal to which a variable voltage is supplied;
A second sense amplifier circuit including first and second input terminals;
A second current mirror circuit for supplying a second current mirror current to each of the third and fourth circuit nodes;
A third selection circuit for connecting one of the second reference voltage input terminal and the third circuit node to the first input terminal of the second sense amplifier circuit in response to a third region signal;
A fourth selection circuit for connecting one of the second reference voltage input terminal and the fourth circuit node to the second input terminal of the second sense amplifier circuit in response to a fourth region signal;
The semiconductor device as described in any one of Claims 1 thru | or 3 provided with these. A first switch circuit connected between the first circuit node and the third circuit node;
A second switch circuit connected between the second circuit node and the fourth circuit node;
Further comprising
5. The semiconductor device according to claim 4, wherein during the read operation, one of the first switch circuit and the second switch circuit is in a conductive state, and the other of the first switch circuit and the second switch circuit is in a non-conductive state.   6. The semiconductor according to claim 1, wherein each of the plurality of first memory cells and the plurality of second memory cells is a memory cell including an STT (Spin Transfer Torque) type resistance change element. apparatus. The first current mirror circuit includes:
A first first conductivity type transistor connected between a power source and the first circuit node and having a first control electrode;
A second first conductivity type connected between the power source and a first internal node and having the first control electrode of the first first conductivity type transistor and the second control electrode connected to the first internal node. A transistor,
A third first conductivity type transistor having a third control electrode connected between the power source and the second circuit node and connected to the first internal node;
A first second conductivity type transistor connected between ground and the first internal node and having a fourth control electrode;
A second second conductivity type transistor connected between the power source and the ground and having a fifth control electrode connected to a fourth control electrode and a second internal node of the first second conductivity type transistor;
The semiconductor device as described in any one of Claims 1 thru | or 6 provided with these. The first and / or second decoder circuit includes:
An address comparison circuit for comparing the address information supplied to the address circuit with address information of a defective data line;
A circuit that switches between using a spare data line as a data line for relieving the defective data line or a data line to which a reference cell is connected in accordance with a control signal;
A semiconductor device according to claim 1, comprising: The first and / or second decoder circuit includes:
A relief circuit for relieving the defective data line based on the address information supplied to the address circuit and address information of the defective data line;
A circuit for selecting a data line connected to a reference cell from data lines included in the first and second memory cell arrays in response to a control signal;
A semiconductor device according to claim 1, comprising: Extracting a reference cell group from a plurality of resistance change type first memory cell groups arranged in a matrix at intersections of a plurality of word lines and a plurality of bit lines;
Extracting a first memory cell from the reference cell group as a reference cell;
When at least one defective memory cell is present in the remaining memory cell group other than the extracted reference cell group, the at least one defective memory cell is extracted as a reference cell of the extracted reference cell group. Replacing a memory cell other than the first memory cell,
Data line switching method including.   11. The data line switching method according to claim 10, wherein the reference cell group is a memory cell selected by a partial word line of the plurality of word lines and / or a partial bit line of the plurality of bit lines.   12. The data line switching method according to claim 10, wherein each of the first memory cell groups is a memory cell including an STT (Spin Transfer Torque) type resistance change element.

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