CN102013271A - Fast reading device and method of phase change memory - Google Patents
Fast reading device and method of phase change memory Download PDFInfo
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- CN102013271A CN102013271A CN 200910195367 CN200910195367A CN102013271A CN 102013271 A CN102013271 A CN 102013271A CN 200910195367 CN200910195367 CN 200910195367 CN 200910195367 A CN200910195367 A CN 200910195367A CN 102013271 A CN102013271 A CN 102013271A
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Abstract
The invention relates to a fast reading device of a phase change memory, which comprises a phase change memory cell to be read, a charging circuit, an overshoot recovery rate detecting circuit, a sensitive amplifier circuit and a reference level or a reference memory cell. On one hand, the phase change memory cell (which can be abstracted as a resistor in the circuit) and a parasitic capacitor on a digit line form a resistor-capacitor (RC) circuit, and on the other hand, a gated metal oxide semiconductor (MOS) pipe instantly enters a linear region from a saturation region when being switched on/of, thereby causing an overshoot phenomenon. For phase change resistors of different states, the corresponding recovery rates after the overshoot are different. By reading the recovery rate of the digit-line level after the overshoot and fast reading the state of the phase change memory cell, the reading rate of the whole memory is accelerated. In addition, fast reading is beneficial to avoiding the damage caused by reading operation to the phase change cell, thereby achieving the purpose of reducing reading interference.
Description
Technical field
The present invention relates to the micro-nano art of electronics, refer in particular to a kind of novel, phase transition storage method for quickly reading.
Background technology
The phase transition storage technology is based on Ovshinsky at late 1960s (Phys.Rev.Lett., 21,1450～1453,1968) beginning of the seventies (Appl.Phys.Lett., 18,254～257,1971) phase-change thin film of Ti Chuing can be applied to that the conception of phase change memory medium sets up, and is the memory device of a kind of low price, stable performance.Phase transition storage can be made on the silicon wafer substrate, its critical material is that the research focus of recordable phase-change thin film, heating electrode material, thermal insulation material and extraction electrode material also just launches around its device technology: the physical mechanism research of device comprises how reducing device material etc.The ultimate principle of phase transition storage is to utilize electric impulse signal to act on the device cell, make phase-change material between amorphous state and polycrystalline attitude, reversible transition take place, low-resistance when high resistant during by the resolution amorphous state and polycrystalline attitude can realize writing, wipe and read operation of information.
Phase transition storage owing to have reads at a high speed, high erasable number of times, non-volatile, advantages such as component size is little, strong motion low in energy consumption, anti-and radioresistance, is thought flash memories that most possible replacement is present by international semiconductor TIA and becomes following storer main product and become the device of commercial product at first.
The reading and writing of phase transition storage, wiping operation apply the voltage or the current pulse signal of different in width and height exactly on device cell: wipe operation (RESET), after phase-change material temperature in adding a weak point and strong pulse enable signal device cell is elevated to more than the temperature of fusion, through thereby cooling realization phase-change material polycrystalline attitude is to amorphous conversion fast, promptly one state is to the conversion of " 0 " attitude again; Write operation (SET), when apply one long and pulse enable signal phase-change material temperature medium tenacity is raised under the temperature of fusion, on the Tc after, and keep a period of time to impel nucleus growth, thus realize the conversion of amorphous state to the polycrystalline attitude, promptly " 0 " attitude is to the conversion of one state; Read operation after adding a very weak pulse signal that can not exert an influence to the state of phase-change material, is read its state by the resistance value of measuring element unit.
Although the phase transition storage great application prospect, and attracted industry to pay close attention to widely, still there are several gordian technique points not to be well solved.One of them reads problem exactly.The process that reads of phase transition storage generally can be divided into two parts: precharge, amplification level.Precharge section sends electric current (voltage) pulse to phase-change memory cell, makes its bit-line voltage (electric current) rise, and its ascending velocity is subjected to stray capacitance and the resistance value influences of phase change cells own.When rising to certain value, the amplification level part is amplified to full width of cloth signal output by sense amplifier with bit-line levels.This process must have destructiveness to phase change cells itself, and after repeatedly reading, the state of phase change cells must be affected.Minimum for destructiveness is dropped to, current circuit design is had to depend on the sacrifice read margin and is got in return.Secondly, bigger bit line stray capacitance makes reading speed comparatively slow, has hindered the application of phase transition storage.
Given this, be necessary to design the quick reading phase change memories of a kind of new apparatus and method.
Summary of the invention
Technical matters to be solved by this invention provides quick reading device of a kind of phase transition storage and method, on the one hand, under the prerequisite of not sacrificing read margin, makes read operation drop to minimum to the influence of phase change cells; On the other hand, under the prerequisite of having considered the bit line stray capacitance, promote reading speed significantly.
For addressing the above problem, the present invention adopts following technical scheme:
The quick reading device of a kind of phase-change memory cell is characterized in that: this device comprises the phase-change memory cell that continues, links to each other with the phase-change memory cell that continues
Charging circuit is used to send fixing current impulse to continuing phase-change memory cell or keep bit-line voltage to fixed level;
The overshoot recovery rate testing circuit that links to each other with the phase-change memory cell that continues, be used to read continue phase-change memory cell bit-line levels recovery rate and with the output of the form of level;
What link to each other with the phase-change memory cell that continues drags down bit line circuit, is used for after finishing read operation, drags down bit line circuit rapidly, makes the phase-change memory cell that continues carry out next read-write operation;
The sensitive amplifying circuit that is connected with overshoot recovery rate testing circuit output terminal, described sensitive amplifying circuit comprises two input ends at least, an input end is connected with overshoot recovery rate testing circuit output terminal, another input end links to each other with datum or reference memory unit, is used for the signal magnitude of two input ends of comparison and amplifies the output comparative result;
With the latch circuit that sensitive amplification circuit output end is connected, be used for when overshoot rejuvenation also finishes, the correct result that reads not being locked latch, use for subordinate's circuit;
The latch control signal generation circuit that is connected with latch circuit is used to produce the signal controlling latch circuit.
The invention still further relates to the read method of the quick reading device of a kind of phase-change memory cell, it is characterized in that: this method may further comprise the steps:
1) utilize overshoot recovery rate testing circuit to read the overshoot recovery rate afterwards of the phase-change memory cell that continues;
2) this recovery rate is compared with the recovery rate or the datum of the reference memory unit of setting;
3) if the output level of overshoot recovery rate testing circuit greater than the level of datum or reference memory unit, then sensitive amplifying circuit output high level signal, so, the phase-change memory cell that continues is in high-impedance state, if the output level of overshoot recovery rate testing circuit is less than the level of datum or reference memory unit, then sensitive amplifying circuit output low level signal, so, the phase-change memory cell that continues is in low resistance state;
4) latch circuit recovers to latch before phenomenon finishes the high level signal or the low level signal of sensitive amplifying circuit output in overshoot.
This method is by after reading overshoot, and the regeneration rate of bit-line levels reads the state of phase-change memory cell fast, thereby accelerates the whole reading rate of storer.In addition, read fast and help avoid the destruction of read operation, reach and reduce the purpose of reading to disturb phase change cells.
Description of drawings:
Fig. 1 is the phase-change memory cell structure synoptic diagram that continues among the present invention;
Fig. 2 is a kind of structural representation of the quick reading device of phase transition storage of the present invention;
Fig. 3 is a kind of possible circuit diagram of charging circuit among the present invention;
Fig. 4 is a kind of possible circuit diagram of overshoot recovery rate testing circuit among the present invention;
Fig. 5 drags down a kind of possible circuit diagram of bit line circuit among the present invention;
Fig. 6 is a kind of possible circuit diagram of latch control signal generation circuit among the present invention;
Fig. 7 is for utilizing the figure as a result of the industry member standard Spectre of simulation software emulation gained among the present invention;
Fig. 8 is reference memory unit circuit diagram among the present invention;
Fig. 9 is the another kind of structural representation of the quick reading device of phase transition storage of the present invention;
Figure 10 is a kind of possible circuit diagram of latch circuit among the present invention;
Figure 11 is a kind of possible circuit diagram of sensitive amplifying circuit among the present invention.
Embodiment
Embodiment 1
Please refer to shown in Figure 2, the invention provides the quick reading device of a kind of phase transition storage, this device comprise the phase-change memory cell 104 that continues, with the charging circuit 101 that the phase-change memory cell 104 that continues links to each other, be used to send fixing current impulse to continuing phase-change memory cell 104 or keep bit-line voltage to fixed level; The overshoot recovery rate testing circuit 102 that links to each other with the phase-change memory cell that continues, be used to read continue phase-change memory cell bit-line levels recovery rate and with the output of the form of level; What link to each other with the phase-change memory cell that continues drags down bit line circuit 106, is used for after finishing read operation, drags down bit line circuit rapidly, makes the phase-change memory cell that continues carry out next read-write operation; The sensitive amplifying circuit 103 that is connected with overshoot recovery rate testing circuit 102 output terminals, described sensitive amplifying circuit 103 comprises two input ends at least, an input end is connected with overshoot recovery rate testing circuit 102 output terminals, another input end links to each other with datum, is used for the signal of two input ends of comparison and amplifies the output comparative result; With the latch circuit 107 that sensitive amplifying circuit 103 output terminals are connected, be used for when overshoot rejuvenation also finishes, the correct result that reads not being locked latch, use for subordinate's circuit; The latch control signal generation circuit 108 that is connected with latch circuit 107 is used to produce the signal controlling latch circuit.
Fig. 1 is a phase-change memory cell 104, comprises gating metal-oxide-semiconductor 202 and phase-change storage material 201.An end of 201 links to each other with 202 drain terminal, and the other end is a bit line.202 grid end is a word line.
Fig. 2 provides a kind of novel phase transition storage to read circuit fast.It comprises charging circuit 101, overshoot recovery rate testing circuit 102, and sensitive amplifier circuit 103, phase-change memory cell 104 to be measured drags down bit line circuit 106, latch circuit 107, latch control signal generation circuit 108.One end of sensitive amplifier circuit 103 connects overshoot recovery rate testing circuit 102, and the other end connects datum.If phase-change memory cell 104 to be measured is in high-impedance state, then overshoot recovery rate testing circuit 102 output levels are greater than datum, sensitive amplifier circuit 103 output high level signals, 107 of latch circuits latch this high level signal before overshoot recovers the phenomenon end; If phase-change memory cell 104 to be measured is in low resistance state, then overshoot recovery rate testing circuit 102 output levels are less than datum, sensitive amplifier circuit 103 output low level signals, 107 of latch circuits latch low level signal before overshoot recovers the phenomenon end.
Charging circuit comprises and sends fixing current impulse to phase-change memory cell to be measured or keep bit-line voltage to fixed level.Fig. 3 is a kind of possible circuit form of charging circuit 101.By PMOS pipe 204 and 205 and current source 206 constituted one group of current mirror.NMOS pipe 203 is as gate tube, and its drain terminal connects the drain terminal of PMOS pipe 205, and its source end connects the bit line of phase change cells 104 to be measured, and its grid end connects reads enable signal.
Under reading to enable to low level situation, gate tube 203 source end level are floating or ground connection, and the drain terminal level has with VDD and is communicated with, and should be VDD.Become moment of high level by low level reading enable signal, its grid end electrical level rising surpasses threshold voltage.In this case, because the drain terminal level is in most significant digit, so gate tube 203 is forced into the saturation region.To occur one bigger saturation region electric current like this and flow through gate tube 203, this electric current will cause bit-line levels an overshoot phenomenon that makes progress to occur.Gate tube 203 is opened with the path on ground, and its drain terminal level can descend, and finally makes gate tube 203 enter linear zone, thereby makes the electric current that flows through gate tube 203 diminish, and overshoot phenomenon recovers.
Overshoot recovery rate testing circuit can be the differentiating circuit that is made of operational amplifier, resistance, electric capacity.Also can be that other have the circuit form that detects level or electric current slope.As shown in Figure 4, since ideal operational amplificr " empty short, empty disconnected " characteristic, V1=V2=0.The electric current that then flows through resistance 207 must equal to flow through the electric current of electric capacity 210.According to the capacitor charge and discharge formula.
Wherein, u
0Be voltage, R is a resistance, i
RFor flowing through the electric current of resistance R, i
CElectric current for capacitor C.Shown in following formula, the output voltage of overshoot recovery rate testing circuit 102 is input voltage slope value to the time.
Fig. 4 is a kind of possible circuit form 102 of overshoot recovery rate testing circuit, comprises electric capacity 210, resistance 207,209, and operational amplification circuit 208.Because electric capacity, resistance and operational amplifier are circuit form known in the art, are not described further at this.Overshoot recovery rate testing circuit 102 be in the nature differentiating circuit, its principle also is well known to those skilled in the art, and does not repeat them here.
Fig. 5 drags down a kind of possible circuit form of bit line circuit.Dragging down bit line circuit 106 uses a NMOS pipe as dragging down bit line circuit.NMOS source end ground connection, the grid end is for dragging down control signal, and drain terminal connects bit line.In case drag down control signal for high, the NMOS pipe can be with the direct ground connection of bit line.
Latch control signal generation circuit, comprise can the control lag time the delay circuit module.Its input signal is to read enable signal, and output signal promptly is a latch control signal.By the control lag time, can make whole read method adapt to different process conditions.Fig. 6 is a kind of possible circuit form of latch control signal generation circuit 108, comprises a plurality of delay circuits 211 and a MUX 212 of connecting successively.Latch control signal generation circuit 108 will be read enable signal and postpone to produce the latch control signal.By MUX 212 to regulating this time delay, to adapt to different process conditions.
Figure 10 is used for when overshoot rejuvenation does not also finish the correct result that reads being locked latch for a kind of possible circuit structure of latch circuit among the present invention, uses for subordinate's circuit, and when the G end is high level, Q=D, QN=
-D; When the G end was low level, Q and QN kept original state, realize latching.
Sensitive amplifier circuit is used for the signal of two input ends of comparison and amplifies the output comparative result.It can be that the current mode comparator circuit also can be the voltage-type comparator circuit.Figure 11 is a kind of possible circuit structure of sensitive amplifier circuit 103 among the present invention, if the level of BIT# is higher than BIT, because the current mirror effect of M3 and M4, the electric current that flows through M4 will be greater than the electric current of M2, the stray capacitance of DATA# node is a charged state, and electrical level rising is to high level; Vice versa.
Fig. 7 is the result who utilizes the industry member standard Spectre of simulation software emulation gained.In overshoot rejuvenation, bit-line levels only differs 0.1v as figure shows, and recovers testing circuit through overshoot, and its level differs and reaches more than the 1.3v.
Embodiment 2
Please refer to shown in Figure 9, the invention provides the quick reading device of a kind of phase transition storage, this device comprise the phase-change memory cell 104 that continues, with the charging circuit 101 that the phase-change memory cell 104 that continues links to each other, be used to send fixing current impulse to continuing phase-change memory cell 104 or keep bit-line voltage to fixed level; The overshoot recovery rate testing circuit 102 that links to each other with the phase-change memory cell that continues, be used for form with the electric current slope read the phase-change memory cell that continues bit-line levels recovery rate and with the form output of level; What link to each other with the phase-change memory cell that continues drags down bit line circuit 106, is used for after finishing read operation, drags down bit line circuit rapidly, makes the phase-change memory cell that continues carry out next read-write operation; The sensitive amplifying circuit 103 that is connected with overshoot recovery rate testing circuit 102 output terminals, described sensitive amplifying circuit 103 comprises two input ends at least, an input end is connected with overshoot recovery rate testing circuit 102 output terminals, another input end links to each other with datum, is used for the signal of two input ends of comparison and amplifies the output comparative result; With the latch circuit 107 that sensitive amplifying circuit 103 output terminals are connected, be used for when overshoot rejuvenation also finishes, the correct result that reads not being locked latch, use for subordinate's circuit; The latch control signal generation circuit 108 that is connected with latch circuit 107 is used to produce the signal controlling latch circuit.
Describedly comprise with reference to phase transition storage 105, the charging circuit 101 that links to each other with reference phase transition storage 105, be used to send fixing current impulse to reference to phase transition storage or keep bit-line voltage to fixed level with reference to phase-change memory cell; The overshoot recovery rate testing circuit 102 that links to each other with the reference phase transition storage is used to detect level or electric current slope and output; What link to each other with the reference phase transition storage drags down bit line circuit 106, be used for after finishing read operation, drag down bit line circuit rapidly, make with reference to phase transition storage and carry out next read-write operation, overshoot recovery rate testing circuit 102 output terminals link to each other with the input end of sensitive amplifying circuit 103.
Embodiment 3
The quick reading device of a kind of phase transition storage, thus can be with recovery rate with set datum and compare and determine the state of phase-change memory cell; Also can be that the recovery rate of the storage unit of two similar structures is compared, one of them be for determining the storage unit of state, thereby determines the state of another phase-change memory cell.The storage unit of two similar structures, one of them is the phase-change memory cell that continues; Another can be
B) resistance of fixed resistance value;
C) can determine the phase-change memory cell of state;
D) can not determine the phase-change memory cell of state equally.
The invention still further relates to the read method of the quick reading device of a kind of phase-change memory cell, it is characterized in that: this method may further comprise the steps:
1) utilize overshoot recovery rate testing circuit to read the overshoot recovery rate afterwards of the phase-change memory cell that continues;
In actual reading phase change memories process because bit line gating metal-oxide-semiconductor is in the moment of opening, can experience by the process of saturation region to linear zone, cause open the moment bit-line levels can be above the level value of reading under the steady state (SS).So bit-line levels must experience the process that a mistake is flushed to recovery.Discharge and recharge theory according to RC, under the certain situation of bit line capacitance, if phase-change memory cell (can abstractly be a resistance) resistance is bigger, then bit line recovers slowly, if resistance is very big, even might make the overshoot level also be lower than the level value of reading under the steady state (SS), then bit-line levels continues to rise; If resistance is less, then bit-line levels is recovered rapidly.So, by reading the regeneration rate of overshoot bit-line levels afterwards, can judge the resistance of phase-change memory cell, thereby realize read operation.
2) this recovery rate is compared with the recovery rate or the datum of the reference memory unit of setting;
3) if the output level of overshoot recovery rate testing circuit greater than the level of datum or reference memory unit, then sensitive amplifying circuit output high level signal, so, the phase-change memory cell that continues is in high-impedance state, if the output level of overshoot recovery rate testing circuit is less than the level of datum or reference memory unit, then sensitive amplifying circuit output low level signal, so, the phase-change memory cell that continues is in low resistance state;
4) latch circuit recovers to latch before phenomenon finishes the high level signal or the low level signal of sensitive amplifying circuit output in overshoot.
Owing to only in bit-line levels variation (overshoot recovers phenomenon and still exists), just can judge the state of phase-change memory cell.If bit-line levels has been stablized, the testing circuit of overshoot recovery rate so can't be distinguished the phase-change memory cell of different conditions.So, must adopt latch technique, before overshoot recovers the phenomenon end, the signal latch of being read is lived.Principle of the present invention is as follows:
1) the RC loop of phase change resistor and bit line capacitance formation;
2) the gating metal-oxide-semiconductor enters linear zone in switch moment by the saturation region, thereby causes overshoot;
3) after overshoot, the phase change resistor of different conditions, the regeneration rate after its overshoot is different;
According to these three characteristics,, read the state of phase-change memory cell by the recovery rate of reading bit line level (electric current) after overshoot.
At first open bit line gating metal-oxide-semiconductor, make and read electric current (voltage) and enter into phase-change memory cell.Gating metal-oxide-semiconductor (being assumed to be NMOS) is not being opened under the situation, and its source end level is floating or ground connection, and the drain terminal level has with VDD and is communicated with, and should be VDD.In opening procedure, its grid end electrical level rising surpasses threshold voltage.In this case, because the drain terminal level is in most significant digit, so gating MOS is forced into the saturation region.To occur one bigger saturation region electric current like this and flow through the gating metal-oxide-semiconductor, this electric current will cause bit-line levels an overshoot phenomenon that makes progress to occur.The gating metal-oxide-semiconductor is opened with the path on ground, and its drain terminal level can descend, and finally makes metal-oxide-semiconductor enter linear zone, thereby makes the electric current that flows through the gating metal-oxide-semiconductor diminish, and overshoot phenomenon recovers.In this course, if the resistance of phase change cells is less, then the overshoot recovery is very fast; If resistance is bigger, then the overshoot recovery is slow; If resistance is very big, gating metal-oxide-semiconductor drain terminal will not have itself and the path " by force " of VDD with the path on ground, will not have overshoot phenomenon, perhaps not recover bit-line levels continuation rising after the overshoot phenomenon.
Utilize this characteristic, after overshoot phenomenon, can utilize overshoot recovery rate testing circuit (perhaps slope detection circuit), the slope meter of bit-line levels is calculated, and show with the form of level.Please refer to shown in Figure 4, the differentiating circuit that overshoot recovery rate testing circuit can adopt operational amplifier, resistance, electric capacity to constitute.The output terminal of slope detection circuit is connected to sense amplifier.The other end of sense amplifier can be a datum, also can be that to have the storage unit of similar structures for referencial use.The storage unit of this class can be the resistance of fixed resistance value, also can be the phase-change memory cell that can not determine state equally.
Because it is very fast that overshoot recovers.So, must read the result when overshoot rejuvenation does not also finish, to latch connecting latch cicuit behind the sense amplifier output terminal.Can directly adopt the inhibit signal of reading to enable as control signal.By the control lag time, can make whole read method adapt to different process conditions like this.
The material of the phase transition storage among the present invention can be a phase-change storage material, its material system can be (Ge, Sb, Te), (Si, Sb, Te), (Si, Sb) or other high performance material systems.
Apparatus and method of the present invention also can be used for reading of multidigit memory technology.
The present invention reads the state of phase-change memory cell fast by reading the overshoot regeneration rate of bit-line levels later on, thereby accelerates the whole reading rate of storer.In addition, read fast and help avoid the destruction of read operation, reach and reduce the purpose of reading to disturb phase change cells.
The foregoing description just lists expressivity principle of the present invention and effect is described, but not is used to limit the present invention.Any personnel that are familiar with this technology all can make amendment to the foregoing description under spirit of the present invention and scope.Therefore, the scope of the present invention should be listed as claims.
Claims (10)
1. quick reading device of phase-change memory cell is characterized in that: this device comprises the phase-change memory cell that continues, links to each other with the phase-change memory cell that continues
Charging circuit is used to send fixing current impulse to continuing phase-change memory cell or keep bit-line voltage to fixed level;
The overshoot recovery rate testing circuit that links to each other with the phase-change memory cell that continues is used to read the recovery rate of bit-line levels of phase-change memory cell of continuing, and with the form output of level;
What link to each other with the phase-change memory cell that continues drags down bit line circuit, is used for after finishing read operation, drags down bit line circuit rapidly, makes the phase-change memory cell that continues carry out next read-write operation;
The sensitive amplifying circuit that is connected with overshoot recovery rate testing circuit output terminal, described sensitive amplifying circuit comprises two input ends at least, an input end is connected with overshoot recovery rate testing circuit output terminal, another input end links to each other with datum or reference memory unit, is used for the signal magnitude of two input ends of comparison and amplifies the output comparative result;
With the latch circuit that sensitive amplification circuit output end is connected, be used for when overshoot rejuvenation also finishes, the correct result that reads not being locked latch, use for subordinate's circuit;
The latch control signal generation circuit that is connected with latch circuit is used to produce the signal controlling latch circuit.
2. the quick reading device of a kind of phase-change memory cell as claimed in claim 1 is characterized in that: described reference memory unit is the resistance of fixed resistance value.
3. the quick reading device of a kind of phase-change memory cell as claimed in claim 1 is characterized in that: describedly comprise with reference to phase transition storage, link to each other with the reference phase transition storage with reference to phase-change memory cell
Charging circuit is used to send fixing current impulse to reference to phase transition storage or keep bit-line voltage to fixed level;
The overshoot recovery rate testing circuit that links to each other with the reference phase transition storage, be used to read continue phase-change memory cell bit-line levels recovery rate and with the output of the form of level;
What link to each other with the reference phase transition storage drags down bit line circuit, is used for after finishing read operation, drags down bit line circuit rapidly, makes with reference to phase transition storage and carries out next read-write operation, and overshoot recovery rate testing circuit output terminal links to each other with the input end of sensitive amplifying circuit.
4. the quick reading device of a kind of phase-change memory cell as claimed in claim 1, it is characterized in that: described charging circuit comprises that the one group of current mirror and the gate tube NMOS that are made of two PMOS pipe and the current source that is connected with the drain terminal of a PMOS pipe manage, the drain terminal of gate tube NMOS pipe connects the drain terminal of another PMOS pipe, the source end of gate tube NMOS pipe connects the bit line of the phase-change memory cell that continues, and the grid end of gate tube NMOS pipe connects reads enable signal.
5. the quick reading device of a kind of phase-change memory cell as claimed in claim 1 is characterized in that: described overshoot recovery rate testing circuit is a differentiating circuit.
6. the quick reading device of a kind of phase-change memory cell as claimed in claim 5 is characterized in that: described differentiating circuit comprises first resistance of operational amplifier, concatenation operation amplifier out and input end, the electric capacity of concatenation operation amp.in and second resistance of another input end of concatenation operation amplifier.
7. the quick reading device of a kind of phase-change memory cell as claimed in claim 1 is characterized in that: the described bit line circuit that drags down comprises a NMOS pipe, the source end ground connection of NMOS pipe, the grid end is for dragging down control signal, drain terminal connects bit line, when dragging down control signal for high, the direct ground connection of NMOS pipe bit line.
8. the quick reading device of a kind of phase-change memory cell as claimed in claim 1, it is characterized in that: described latch signal produces circuit, comprise a delay circuit module that is used for the control lag time, its input signal is to read enable signal, and output signal is a latch control signal.
9. as the read method of any quick reading device of described a kind of phase-change memory cell of claim 1 to 8, it is characterized in that: this method may further comprise the steps:
1) utilize overshoot recovery rate testing circuit to read the overshoot recovery rate afterwards of the phase-change memory cell that continues;
2) this recovery rate is compared with the recovery rate or the datum of the reference memory unit of setting;
3) if the output level of overshoot recovery rate testing circuit greater than the level of datum or reference memory unit, then sensitive amplifying circuit output high level signal, so, the phase-change memory cell that continues is in high-impedance state, if the output level of overshoot recovery rate testing circuit is less than the level of datum or reference memory unit, then sensitive amplifying circuit output low level signal, so, the phase-change memory cell that continues is in low resistance state;
4) latch circuit recovers to latch before phenomenon finishes the high level signal or the low level signal of sensitive amplifying circuit output in overshoot.
10. the read method of the quick reading device of a kind of phase-change memory cell as claimed in claim 8 is characterized in that: described reference memory unit is the resistance of fixed resistance value.
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| WO2012167456A1 (en) * | 2011-06-07 | 2012-12-13 | 中国科学院上海微系统与信息技术研究所 | Data readout circuit of phase change memory |
| CN103187089A (en) * | 2011-12-27 | 2013-07-03 | 中国科学院微电子研究所 | Bit line strobe unit and strobe method |
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Family Cites Families (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
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| CN101404179B (en) * | 2008-11-07 | 2011-04-20 | 中国科学院上海微系统与信息技术研究所 | Method for improving programming speed of phase-change memory and realization method |
-
2009
- 2009-09-08 CN CN 200910195367 patent/CN102013271B/en active Active
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